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1 | ;------------------------------------------------------------------------------\r |
2 | ;\r | |
3 | ; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r | |
4 | ; This program and the accompanying materials\r | |
5 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
6 | ; which accompanies this distribution. The full text of the license may be found at\r | |
7 | ; http://opensource.org/licenses/bsd-license.php.\r | |
8 | ;\r | |
9 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | ;\r | |
12 | ; Module Name:\r | |
13 | ;\r | |
14 | ; DisableCache.Asm\r | |
15 | ;\r | |
16 | ; Abstract:\r | |
17 | ;\r | |
18 | ; Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a\r | |
19 | ; WBINVD instruction.\r | |
20 | ;\r | |
21 | ; Notes:\r | |
22 | ;\r | |
23 | ;------------------------------------------------------------------------------\r | |
24 | \r | |
25 | DEFAULT REL\r | |
26 | SECTION .text\r | |
27 | \r | |
28 | ;------------------------------------------------------------------------------\r | |
29 | ; VOID\r | |
30 | ; EFIAPI\r | |
31 | ; AsmDisableCache (\r | |
32 | ; VOID\r | |
33 | ; );\r | |
34 | ;------------------------------------------------------------------------------\r | |
35 | global ASM_PFX(AsmDisableCache)\r | |
36 | ASM_PFX(AsmDisableCache):\r | |
37 | mov rax, cr0\r | |
38 | bts rax, 30\r | |
39 | btr rax, 29\r | |
40 | mov cr0, rax\r | |
41 | wbinvd\r | |
42 | ret\r | |
43 | \r |