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540fd45f MK |
1 | /** @file\r |
2 | IA32/X64 specific Unit Test Host functions.\r | |
3 | \r | |
4 | Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
7 | **/\r | |
8 | \r | |
9 | #include "UnitTestHost.h"\r | |
10 | \r | |
11 | ///\r | |
12 | /// Defines for mUnitTestHostBaseLibSegment indexes\r | |
13 | ///\r | |
14 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0\r | |
15 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1\r | |
16 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2\r | |
17 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3\r | |
18 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4\r | |
19 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5\r | |
20 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6\r | |
21 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7\r | |
22 | \r | |
23 | ///\r | |
24 | /// Module global variables for simple system emulation of MSRs, CRx, DRx,\r | |
25 | /// GDTR, IDTR, and Segment Selectors.\r | |
26 | ///\r | |
27 | STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000];\r | |
28 | STATIC UINTN mUnitTestHostBaseLibCr[5];\r | |
29 | STATIC UINTN mUnitTestHostBaseLibDr[8];\r | |
30 | STATIC UINT16 mUnitTestHostBaseLibSegment[8];\r | |
31 | STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr;\r | |
32 | STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr;\r | |
33 | \r | |
34 | /**\r | |
35 | Retrieves CPUID information.\r | |
36 | \r | |
37 | Executes the CPUID instruction with EAX set to the value specified by Index.\r | |
38 | This function always returns Index.\r | |
39 | If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r | |
40 | If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r | |
41 | If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r | |
42 | If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r | |
43 | This function is only available on IA-32 and x64.\r | |
44 | \r | |
45 | @param Index The 32-bit value to load into EAX prior to invoking the CPUID\r | |
46 | instruction.\r | |
47 | @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r | |
48 | instruction. This is an optional parameter that may be NULL.\r | |
49 | @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r | |
50 | instruction. This is an optional parameter that may be NULL.\r | |
51 | @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r | |
52 | instruction. This is an optional parameter that may be NULL.\r | |
53 | @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r | |
54 | instruction. This is an optional parameter that may be NULL.\r | |
55 | \r | |
56 | @return Index.\r | |
57 | \r | |
58 | **/\r | |
59 | UINT32\r | |
60 | EFIAPI\r | |
61 | UnitTestHostBaseLibAsmCpuid (\r | |
2f88bd3a MK |
62 | IN UINT32 Index,\r |
63 | OUT UINT32 *Eax OPTIONAL,\r | |
64 | OUT UINT32 *Ebx OPTIONAL,\r | |
65 | OUT UINT32 *Ecx OPTIONAL,\r | |
66 | OUT UINT32 *Edx OPTIONAL\r | |
540fd45f MK |
67 | )\r |
68 | {\r | |
69 | if (Eax != NULL) {\r | |
70 | *Eax = 0;\r | |
71 | }\r | |
2f88bd3a | 72 | \r |
540fd45f MK |
73 | if (Ebx != NULL) {\r |
74 | *Ebx = 0;\r | |
75 | }\r | |
2f88bd3a | 76 | \r |
540fd45f MK |
77 | if (Ecx != NULL) {\r |
78 | *Ecx = 0;\r | |
79 | }\r | |
2f88bd3a | 80 | \r |
540fd45f MK |
81 | if (Edx != NULL) {\r |
82 | *Edx = 0;\r | |
83 | }\r | |
2f88bd3a | 84 | \r |
540fd45f MK |
85 | return Index;\r |
86 | }\r | |
87 | \r | |
88 | /**\r | |
89 | Retrieves CPUID information using an extended leaf identifier.\r | |
90 | \r | |
91 | Executes the CPUID instruction with EAX set to the value specified by Index\r | |
92 | and ECX set to the value specified by SubIndex. This function always returns\r | |
93 | Index. This function is only available on IA-32 and x64.\r | |
94 | \r | |
95 | If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r | |
96 | If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r | |
97 | If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r | |
98 | If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r | |
99 | \r | |
100 | @param Index The 32-bit value to load into EAX prior to invoking the\r | |
101 | CPUID instruction.\r | |
102 | @param SubIndex The 32-bit value to load into ECX prior to invoking the\r | |
103 | CPUID instruction.\r | |
104 | @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r | |
105 | instruction. This is an optional parameter that may be\r | |
106 | NULL.\r | |
107 | @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r | |
108 | instruction. This is an optional parameter that may be\r | |
109 | NULL.\r | |
110 | @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r | |
111 | instruction. This is an optional parameter that may be\r | |
112 | NULL.\r | |
113 | @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r | |
114 | instruction. This is an optional parameter that may be\r | |
115 | NULL.\r | |
116 | \r | |
117 | @return Index.\r | |
118 | \r | |
119 | **/\r | |
120 | UINT32\r | |
121 | EFIAPI\r | |
122 | UnitTestHostBaseLibAsmCpuidEx (\r | |
2f88bd3a MK |
123 | IN UINT32 Index,\r |
124 | IN UINT32 SubIndex,\r | |
125 | OUT UINT32 *Eax OPTIONAL,\r | |
126 | OUT UINT32 *Ebx OPTIONAL,\r | |
127 | OUT UINT32 *Ecx OPTIONAL,\r | |
128 | OUT UINT32 *Edx OPTIONAL\r | |
540fd45f MK |
129 | )\r |
130 | {\r | |
131 | if (Eax != NULL) {\r | |
132 | *Eax = 0;\r | |
133 | }\r | |
2f88bd3a | 134 | \r |
540fd45f MK |
135 | if (Ebx != NULL) {\r |
136 | *Ebx = 0;\r | |
137 | }\r | |
2f88bd3a | 138 | \r |
540fd45f MK |
139 | if (Ecx != NULL) {\r |
140 | *Ecx = 0;\r | |
141 | }\r | |
2f88bd3a | 142 | \r |
540fd45f MK |
143 | if (Edx != NULL) {\r |
144 | *Edx = 0;\r | |
145 | }\r | |
2f88bd3a | 146 | \r |
540fd45f MK |
147 | return Index;\r |
148 | }\r | |
149 | \r | |
150 | /**\r | |
151 | Set CD bit and clear NW bit of CR0 followed by a WBINVD.\r | |
152 | \r | |
153 | Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,\r | |
154 | and executing a WBINVD instruction. This function is only available on IA-32 and x64.\r | |
155 | \r | |
156 | **/\r | |
157 | VOID\r | |
158 | EFIAPI\r | |
159 | UnitTestHostBaseLibAsmDisableCache (\r | |
160 | VOID\r | |
161 | )\r | |
162 | {\r | |
163 | }\r | |
164 | \r | |
165 | /**\r | |
166 | Perform a WBINVD and clear both the CD and NW bits of CR0.\r | |
167 | \r | |
168 | Enables the caches by executing a WBINVD instruction and then clear both the CD and NW\r | |
169 | bits of CR0 to 0. This function is only available on IA-32 and x64.\r | |
170 | \r | |
171 | **/\r | |
172 | VOID\r | |
173 | EFIAPI\r | |
174 | UnitTestHostBaseLibAsmEnableCache (\r | |
175 | VOID\r | |
176 | )\r | |
177 | {\r | |
178 | }\r | |
179 | \r | |
180 | /**\r | |
181 | Returns a 64-bit Machine Specific Register(MSR).\r | |
182 | \r | |
183 | Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r | |
184 | performed on Index, and some Index values may cause CPU exceptions. The\r | |
185 | caller must either guarantee that Index is valid, or the caller must set up\r | |
186 | exception handlers to catch the exceptions. This function is only available\r | |
187 | on IA-32 and x64.\r | |
188 | \r | |
189 | @param Index The 32-bit MSR index to read.\r | |
190 | \r | |
191 | @return The value of the MSR identified by Index.\r | |
192 | \r | |
193 | **/\r | |
194 | UINT64\r | |
195 | EFIAPI\r | |
196 | UnitTestHostBaseLibAsmReadMsr64 (\r | |
2f88bd3a | 197 | IN UINT32 Index\r |
540fd45f MK |
198 | )\r |
199 | {\r | |
200 | if (Index < 0x1000) {\r | |
201 | return mUnitTestHostBaseLibMsr[0][Index];\r | |
202 | }\r | |
2f88bd3a MK |
203 | \r |
204 | if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {\r | |
540fd45f MK |
205 | return mUnitTestHostBaseLibMsr[1][Index];\r |
206 | }\r | |
2f88bd3a | 207 | \r |
540fd45f MK |
208 | return 0;\r |
209 | }\r | |
210 | \r | |
211 | /**\r | |
212 | Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r | |
213 | value.\r | |
214 | \r | |
215 | Writes the 64-bit value specified by Value to the MSR specified by Index. The\r | |
216 | 64-bit value written to the MSR is returned. No parameter checking is\r | |
217 | performed on Index or Value, and some of these may cause CPU exceptions. The\r | |
218 | caller must either guarantee that Index and Value are valid, or the caller\r | |
219 | must establish proper exception handlers. This function is only available on\r | |
220 | IA-32 and x64.\r | |
221 | \r | |
222 | @param Index The 32-bit MSR index to write.\r | |
223 | @param Value The 64-bit value to write to the MSR.\r | |
224 | \r | |
225 | @return Value\r | |
226 | \r | |
227 | **/\r | |
228 | UINT64\r | |
229 | EFIAPI\r | |
230 | UnitTestHostBaseLibAsmWriteMsr64 (\r | |
2f88bd3a MK |
231 | IN UINT32 Index,\r |
232 | IN UINT64 Value\r | |
540fd45f MK |
233 | )\r |
234 | {\r | |
235 | if (Index < 0x1000) {\r | |
236 | mUnitTestHostBaseLibMsr[0][Index] = Value;\r | |
237 | }\r | |
2f88bd3a MK |
238 | \r |
239 | if ((Index >= 0xC0000000) && (Index < 0xC0001000)) {\r | |
540fd45f MK |
240 | mUnitTestHostBaseLibMsr[1][Index - 0xC00000000] = Value;\r |
241 | }\r | |
2f88bd3a | 242 | \r |
540fd45f MK |
243 | return Value;\r |
244 | }\r | |
245 | \r | |
246 | /**\r | |
247 | Reads the current value of the Control Register 0 (CR0).\r | |
248 | \r | |
249 | Reads and returns the current value of CR0. This function is only available\r | |
250 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
251 | x64.\r | |
252 | \r | |
253 | @return The value of the Control Register 0 (CR0).\r | |
254 | \r | |
255 | **/\r | |
256 | UINTN\r | |
257 | EFIAPI\r | |
258 | UnitTestHostBaseLibAsmReadCr0 (\r | |
259 | VOID\r | |
260 | )\r | |
261 | {\r | |
262 | return mUnitTestHostBaseLibCr[0];\r | |
263 | }\r | |
264 | \r | |
265 | /**\r | |
266 | Reads the current value of the Control Register 2 (CR2).\r | |
267 | \r | |
268 | Reads and returns the current value of CR2. This function is only available\r | |
269 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
270 | x64.\r | |
271 | \r | |
272 | @return The value of the Control Register 2 (CR2).\r | |
273 | \r | |
274 | **/\r | |
275 | UINTN\r | |
276 | EFIAPI\r | |
277 | UnitTestHostBaseLibAsmReadCr2 (\r | |
278 | VOID\r | |
279 | )\r | |
280 | {\r | |
281 | return mUnitTestHostBaseLibCr[2];\r | |
282 | }\r | |
283 | \r | |
284 | /**\r | |
285 | Reads the current value of the Control Register 3 (CR3).\r | |
286 | \r | |
287 | Reads and returns the current value of CR3. This function is only available\r | |
288 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
289 | x64.\r | |
290 | \r | |
291 | @return The value of the Control Register 3 (CR3).\r | |
292 | \r | |
293 | **/\r | |
294 | UINTN\r | |
295 | EFIAPI\r | |
296 | UnitTestHostBaseLibAsmReadCr3 (\r | |
297 | VOID\r | |
298 | )\r | |
299 | {\r | |
300 | return mUnitTestHostBaseLibCr[3];\r | |
301 | }\r | |
302 | \r | |
303 | /**\r | |
304 | Reads the current value of the Control Register 4 (CR4).\r | |
305 | \r | |
306 | Reads and returns the current value of CR4. This function is only available\r | |
307 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
308 | x64.\r | |
309 | \r | |
310 | @return The value of the Control Register 4 (CR4).\r | |
311 | \r | |
312 | **/\r | |
313 | UINTN\r | |
314 | EFIAPI\r | |
315 | UnitTestHostBaseLibAsmReadCr4 (\r | |
316 | VOID\r | |
317 | )\r | |
318 | {\r | |
319 | return mUnitTestHostBaseLibCr[4];\r | |
320 | }\r | |
321 | \r | |
322 | /**\r | |
323 | Writes a value to Control Register 0 (CR0).\r | |
324 | \r | |
325 | Writes and returns a new value to CR0. This function is only available on\r | |
326 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
327 | \r | |
328 | @param Cr0 The value to write to CR0.\r | |
329 | \r | |
330 | @return The value written to CR0.\r | |
331 | \r | |
332 | **/\r | |
333 | UINTN\r | |
334 | EFIAPI\r | |
335 | UnitTestHostBaseLibAsmWriteCr0 (\r | |
336 | UINTN Cr0\r | |
337 | )\r | |
338 | {\r | |
339 | mUnitTestHostBaseLibCr[0] = Cr0;\r | |
340 | return Cr0;\r | |
341 | }\r | |
342 | \r | |
343 | /**\r | |
344 | Writes a value to Control Register 2 (CR2).\r | |
345 | \r | |
346 | Writes and returns a new value to CR2. This function is only available on\r | |
347 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
348 | \r | |
349 | @param Cr2 The value to write to CR2.\r | |
350 | \r | |
351 | @return The value written to CR2.\r | |
352 | \r | |
353 | **/\r | |
354 | UINTN\r | |
355 | EFIAPI\r | |
356 | UnitTestHostBaseLibAsmWriteCr2 (\r | |
357 | UINTN Cr2\r | |
358 | )\r | |
359 | {\r | |
360 | mUnitTestHostBaseLibCr[2] = Cr2;\r | |
361 | return Cr2;\r | |
362 | }\r | |
363 | \r | |
364 | /**\r | |
365 | Writes a value to Control Register 3 (CR3).\r | |
366 | \r | |
367 | Writes and returns a new value to CR3. This function is only available on\r | |
368 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
369 | \r | |
370 | @param Cr3 The value to write to CR3.\r | |
371 | \r | |
372 | @return The value written to CR3.\r | |
373 | \r | |
374 | **/\r | |
375 | UINTN\r | |
376 | EFIAPI\r | |
377 | UnitTestHostBaseLibAsmWriteCr3 (\r | |
378 | UINTN Cr3\r | |
379 | )\r | |
380 | {\r | |
381 | mUnitTestHostBaseLibCr[3] = Cr3;\r | |
382 | return Cr3;\r | |
383 | }\r | |
384 | \r | |
385 | /**\r | |
386 | Writes a value to Control Register 4 (CR4).\r | |
387 | \r | |
388 | Writes and returns a new value to CR4. This function is only available on\r | |
389 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
390 | \r | |
391 | @param Cr4 The value to write to CR4.\r | |
392 | \r | |
393 | @return The value written to CR4.\r | |
394 | \r | |
395 | **/\r | |
396 | UINTN\r | |
397 | EFIAPI\r | |
398 | UnitTestHostBaseLibAsmWriteCr4 (\r | |
399 | UINTN Cr4\r | |
400 | )\r | |
401 | {\r | |
402 | mUnitTestHostBaseLibCr[4] = Cr4;\r | |
403 | return Cr4;\r | |
404 | }\r | |
405 | \r | |
406 | /**\r | |
407 | Reads the current value of Debug Register 0 (DR0).\r | |
408 | \r | |
409 | Reads and returns the current value of DR0. This function is only available\r | |
410 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
411 | x64.\r | |
412 | \r | |
413 | @return The value of Debug Register 0 (DR0).\r | |
414 | \r | |
415 | **/\r | |
416 | UINTN\r | |
417 | EFIAPI\r | |
418 | UnitTestHostBaseLibAsmReadDr0 (\r | |
419 | VOID\r | |
420 | )\r | |
421 | {\r | |
422 | return mUnitTestHostBaseLibDr[0];\r | |
423 | }\r | |
424 | \r | |
425 | /**\r | |
426 | Reads the current value of Debug Register 1 (DR1).\r | |
427 | \r | |
428 | Reads and returns the current value of DR1. This function is only available\r | |
429 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
430 | x64.\r | |
431 | \r | |
432 | @return The value of Debug Register 1 (DR1).\r | |
433 | \r | |
434 | **/\r | |
435 | UINTN\r | |
436 | EFIAPI\r | |
437 | UnitTestHostBaseLibAsmReadDr1 (\r | |
438 | VOID\r | |
439 | )\r | |
440 | {\r | |
441 | return mUnitTestHostBaseLibDr[1];\r | |
442 | }\r | |
443 | \r | |
444 | /**\r | |
445 | Reads the current value of Debug Register 2 (DR2).\r | |
446 | \r | |
447 | Reads and returns the current value of DR2. This function is only available\r | |
448 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
449 | x64.\r | |
450 | \r | |
451 | @return The value of Debug Register 2 (DR2).\r | |
452 | \r | |
453 | **/\r | |
454 | UINTN\r | |
455 | EFIAPI\r | |
456 | UnitTestHostBaseLibAsmReadDr2 (\r | |
457 | VOID\r | |
458 | )\r | |
459 | {\r | |
460 | return mUnitTestHostBaseLibDr[2];\r | |
461 | }\r | |
462 | \r | |
463 | /**\r | |
464 | Reads the current value of Debug Register 3 (DR3).\r | |
465 | \r | |
466 | Reads and returns the current value of DR3. This function is only available\r | |
467 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
468 | x64.\r | |
469 | \r | |
470 | @return The value of Debug Register 3 (DR3).\r | |
471 | \r | |
472 | **/\r | |
473 | UINTN\r | |
474 | EFIAPI\r | |
475 | UnitTestHostBaseLibAsmReadDr3 (\r | |
476 | VOID\r | |
477 | )\r | |
478 | {\r | |
479 | return mUnitTestHostBaseLibDr[3];\r | |
480 | }\r | |
481 | \r | |
482 | /**\r | |
483 | Reads the current value of Debug Register 4 (DR4).\r | |
484 | \r | |
485 | Reads and returns the current value of DR4. This function is only available\r | |
486 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
487 | x64.\r | |
488 | \r | |
489 | @return The value of Debug Register 4 (DR4).\r | |
490 | \r | |
491 | **/\r | |
492 | UINTN\r | |
493 | EFIAPI\r | |
494 | UnitTestHostBaseLibAsmReadDr4 (\r | |
495 | VOID\r | |
496 | )\r | |
497 | {\r | |
498 | return mUnitTestHostBaseLibDr[4];\r | |
499 | }\r | |
500 | \r | |
501 | /**\r | |
502 | Reads the current value of Debug Register 5 (DR5).\r | |
503 | \r | |
504 | Reads and returns the current value of DR5. This function is only available\r | |
505 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
506 | x64.\r | |
507 | \r | |
508 | @return The value of Debug Register 5 (DR5).\r | |
509 | \r | |
510 | **/\r | |
511 | UINTN\r | |
512 | EFIAPI\r | |
513 | UnitTestHostBaseLibAsmReadDr5 (\r | |
514 | VOID\r | |
515 | )\r | |
516 | {\r | |
517 | return mUnitTestHostBaseLibDr[5];\r | |
518 | }\r | |
519 | \r | |
520 | /**\r | |
521 | Reads the current value of Debug Register 6 (DR6).\r | |
522 | \r | |
523 | Reads and returns the current value of DR6. This function is only available\r | |
524 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
525 | x64.\r | |
526 | \r | |
527 | @return The value of Debug Register 6 (DR6).\r | |
528 | \r | |
529 | **/\r | |
530 | UINTN\r | |
531 | EFIAPI\r | |
532 | UnitTestHostBaseLibAsmReadDr6 (\r | |
533 | VOID\r | |
534 | )\r | |
535 | {\r | |
536 | return mUnitTestHostBaseLibDr[6];\r | |
537 | }\r | |
538 | \r | |
539 | /**\r | |
540 | Reads the current value of Debug Register 7 (DR7).\r | |
541 | \r | |
542 | Reads and returns the current value of DR7. This function is only available\r | |
543 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
544 | x64.\r | |
545 | \r | |
546 | @return The value of Debug Register 7 (DR7).\r | |
547 | \r | |
548 | **/\r | |
549 | UINTN\r | |
550 | EFIAPI\r | |
551 | UnitTestHostBaseLibAsmReadDr7 (\r | |
552 | VOID\r | |
553 | )\r | |
554 | {\r | |
555 | return mUnitTestHostBaseLibDr[7];\r | |
556 | }\r | |
557 | \r | |
558 | /**\r | |
559 | Writes a value to Debug Register 0 (DR0).\r | |
560 | \r | |
561 | Writes and returns a new value to DR0. This function is only available on\r | |
562 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
563 | \r | |
564 | @param Dr0 The value to write to Dr0.\r | |
565 | \r | |
566 | @return The value written to Debug Register 0 (DR0).\r | |
567 | \r | |
568 | **/\r | |
569 | UINTN\r | |
570 | EFIAPI\r | |
571 | UnitTestHostBaseLibAsmWriteDr0 (\r | |
572 | UINTN Dr0\r | |
573 | )\r | |
574 | {\r | |
575 | mUnitTestHostBaseLibDr[0] = Dr0;\r | |
576 | return Dr0;\r | |
577 | }\r | |
578 | \r | |
579 | /**\r | |
580 | Writes a value to Debug Register 1 (DR1).\r | |
581 | \r | |
582 | Writes and returns a new value to DR1. This function is only available on\r | |
583 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
584 | \r | |
585 | @param Dr1 The value to write to Dr1.\r | |
586 | \r | |
587 | @return The value written to Debug Register 1 (DR1).\r | |
588 | \r | |
589 | **/\r | |
590 | UINTN\r | |
591 | EFIAPI\r | |
592 | UnitTestHostBaseLibAsmWriteDr1 (\r | |
593 | UINTN Dr1\r | |
594 | )\r | |
595 | {\r | |
596 | mUnitTestHostBaseLibDr[1] = Dr1;\r | |
597 | return Dr1;\r | |
598 | }\r | |
599 | \r | |
600 | /**\r | |
601 | Writes a value to Debug Register 2 (DR2).\r | |
602 | \r | |
603 | Writes and returns a new value to DR2. This function is only available on\r | |
604 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
605 | \r | |
606 | @param Dr2 The value to write to Dr2.\r | |
607 | \r | |
608 | @return The value written to Debug Register 2 (DR2).\r | |
609 | \r | |
610 | **/\r | |
611 | UINTN\r | |
612 | EFIAPI\r | |
613 | UnitTestHostBaseLibAsmWriteDr2 (\r | |
614 | UINTN Dr2\r | |
615 | )\r | |
616 | {\r | |
617 | mUnitTestHostBaseLibDr[2] = Dr2;\r | |
618 | return Dr2;\r | |
619 | }\r | |
620 | \r | |
621 | /**\r | |
622 | Writes a value to Debug Register 3 (DR3).\r | |
623 | \r | |
624 | Writes and returns a new value to DR3. This function is only available on\r | |
625 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
626 | \r | |
627 | @param Dr3 The value to write to Dr3.\r | |
628 | \r | |
629 | @return The value written to Debug Register 3 (DR3).\r | |
630 | \r | |
631 | **/\r | |
632 | UINTN\r | |
633 | EFIAPI\r | |
634 | UnitTestHostBaseLibAsmWriteDr3 (\r | |
635 | UINTN Dr3\r | |
636 | )\r | |
637 | {\r | |
638 | mUnitTestHostBaseLibDr[3] = Dr3;\r | |
639 | return Dr3;\r | |
640 | }\r | |
641 | \r | |
642 | /**\r | |
643 | Writes a value to Debug Register 4 (DR4).\r | |
644 | \r | |
645 | Writes and returns a new value to DR4. This function is only available on\r | |
646 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
647 | \r | |
648 | @param Dr4 The value to write to Dr4.\r | |
649 | \r | |
650 | @return The value written to Debug Register 4 (DR4).\r | |
651 | \r | |
652 | **/\r | |
653 | UINTN\r | |
654 | EFIAPI\r | |
655 | UnitTestHostBaseLibAsmWriteDr4 (\r | |
656 | UINTN Dr4\r | |
657 | )\r | |
658 | {\r | |
659 | mUnitTestHostBaseLibDr[4] = Dr4;\r | |
660 | return Dr4;\r | |
661 | }\r | |
662 | \r | |
663 | /**\r | |
664 | Writes a value to Debug Register 5 (DR5).\r | |
665 | \r | |
666 | Writes and returns a new value to DR5. This function is only available on\r | |
667 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
668 | \r | |
669 | @param Dr5 The value to write to Dr5.\r | |
670 | \r | |
671 | @return The value written to Debug Register 5 (DR5).\r | |
672 | \r | |
673 | **/\r | |
674 | UINTN\r | |
675 | EFIAPI\r | |
676 | UnitTestHostBaseLibAsmWriteDr5 (\r | |
677 | UINTN Dr5\r | |
678 | )\r | |
679 | {\r | |
680 | mUnitTestHostBaseLibDr[5] = Dr5;\r | |
681 | return Dr5;\r | |
682 | }\r | |
683 | \r | |
684 | /**\r | |
685 | Writes a value to Debug Register 6 (DR6).\r | |
686 | \r | |
687 | Writes and returns a new value to DR6. This function is only available on\r | |
688 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
689 | \r | |
690 | @param Dr6 The value to write to Dr6.\r | |
691 | \r | |
692 | @return The value written to Debug Register 6 (DR6).\r | |
693 | \r | |
694 | **/\r | |
695 | UINTN\r | |
696 | EFIAPI\r | |
697 | UnitTestHostBaseLibAsmWriteDr6 (\r | |
698 | UINTN Dr6\r | |
699 | )\r | |
700 | {\r | |
701 | mUnitTestHostBaseLibDr[6] = Dr6;\r | |
702 | return Dr6;\r | |
703 | }\r | |
704 | \r | |
705 | /**\r | |
706 | Writes a value to Debug Register 7 (DR7).\r | |
707 | \r | |
708 | Writes and returns a new value to DR7. This function is only available on\r | |
709 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
710 | \r | |
711 | @param Dr7 The value to write to Dr7.\r | |
712 | \r | |
713 | @return The value written to Debug Register 7 (DR7).\r | |
714 | \r | |
715 | **/\r | |
716 | UINTN\r | |
717 | EFIAPI\r | |
718 | UnitTestHostBaseLibAsmWriteDr7 (\r | |
719 | UINTN Dr7\r | |
720 | )\r | |
721 | {\r | |
722 | mUnitTestHostBaseLibDr[7] = Dr7;\r | |
723 | return Dr7;\r | |
724 | }\r | |
725 | \r | |
726 | /**\r | |
727 | Reads the current value of Code Segment Register (CS).\r | |
728 | \r | |
729 | Reads and returns the current value of CS. This function is only available on\r | |
730 | IA-32 and x64.\r | |
731 | \r | |
732 | @return The current value of CS.\r | |
733 | \r | |
734 | **/\r | |
735 | UINT16\r | |
736 | EFIAPI\r | |
737 | UnitTestHostBaseLibAsmReadCs (\r | |
738 | VOID\r | |
739 | )\r | |
740 | {\r | |
741 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS];\r | |
742 | }\r | |
743 | \r | |
744 | /**\r | |
745 | Reads the current value of Data Segment Register (DS).\r | |
746 | \r | |
747 | Reads and returns the current value of DS. This function is only available on\r | |
748 | IA-32 and x64.\r | |
749 | \r | |
750 | @return The current value of DS.\r | |
751 | \r | |
752 | **/\r | |
753 | UINT16\r | |
754 | EFIAPI\r | |
755 | UnitTestHostBaseLibAsmReadDs (\r | |
756 | VOID\r | |
757 | )\r | |
758 | {\r | |
759 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS];\r | |
760 | }\r | |
761 | \r | |
762 | /**\r | |
763 | Reads the current value of Extra Segment Register (ES).\r | |
764 | \r | |
765 | Reads and returns the current value of ES. This function is only available on\r | |
766 | IA-32 and x64.\r | |
767 | \r | |
768 | @return The current value of ES.\r | |
769 | \r | |
770 | **/\r | |
771 | UINT16\r | |
772 | EFIAPI\r | |
773 | UnitTestHostBaseLibAsmReadEs (\r | |
774 | VOID\r | |
775 | )\r | |
776 | {\r | |
777 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES];\r | |
778 | }\r | |
779 | \r | |
780 | /**\r | |
781 | Reads the current value of FS Data Segment Register (FS).\r | |
782 | \r | |
783 | Reads and returns the current value of FS. This function is only available on\r | |
784 | IA-32 and x64.\r | |
785 | \r | |
786 | @return The current value of FS.\r | |
787 | \r | |
788 | **/\r | |
789 | UINT16\r | |
790 | EFIAPI\r | |
791 | UnitTestHostBaseLibAsmReadFs (\r | |
792 | VOID\r | |
793 | )\r | |
794 | {\r | |
795 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS];\r | |
796 | }\r | |
797 | \r | |
798 | /**\r | |
799 | Reads the current value of GS Data Segment Register (GS).\r | |
800 | \r | |
801 | Reads and returns the current value of GS. This function is only available on\r | |
802 | IA-32 and x64.\r | |
803 | \r | |
804 | @return The current value of GS.\r | |
805 | \r | |
806 | **/\r | |
807 | UINT16\r | |
808 | EFIAPI\r | |
809 | UnitTestHostBaseLibAsmReadGs (\r | |
810 | VOID\r | |
811 | )\r | |
812 | {\r | |
813 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS];\r | |
814 | }\r | |
815 | \r | |
816 | /**\r | |
817 | Reads the current value of Stack Segment Register (SS).\r | |
818 | \r | |
819 | Reads and returns the current value of SS. This function is only available on\r | |
820 | IA-32 and x64.\r | |
821 | \r | |
822 | @return The current value of SS.\r | |
823 | \r | |
824 | **/\r | |
825 | UINT16\r | |
826 | EFIAPI\r | |
827 | UnitTestHostBaseLibAsmReadSs (\r | |
828 | VOID\r | |
829 | )\r | |
830 | {\r | |
831 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS];\r | |
832 | }\r | |
833 | \r | |
834 | /**\r | |
835 | Reads the current value of Task Register (TR).\r | |
836 | \r | |
837 | Reads and returns the current value of TR. This function is only available on\r | |
838 | IA-32 and x64.\r | |
839 | \r | |
840 | @return The current value of TR.\r | |
841 | \r | |
842 | **/\r | |
843 | UINT16\r | |
844 | EFIAPI\r | |
845 | UnitTestHostBaseLibAsmReadTr (\r | |
846 | VOID\r | |
847 | )\r | |
848 | {\r | |
849 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR];\r | |
850 | }\r | |
851 | \r | |
852 | /**\r | |
853 | Reads the current Global Descriptor Table Register(GDTR) descriptor.\r | |
854 | \r | |
855 | Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r | |
856 | function is only available on IA-32 and x64.\r | |
857 | \r | |
858 | If Gdtr is NULL, then ASSERT().\r | |
859 | \r | |
860 | @param Gdtr The pointer to a GDTR descriptor.\r | |
861 | \r | |
862 | **/\r | |
863 | VOID\r | |
864 | EFIAPI\r | |
865 | UnitTestHostBaseLibAsmReadGdtr (\r | |
2f88bd3a | 866 | OUT IA32_DESCRIPTOR *Gdtr\r |
540fd45f MK |
867 | )\r |
868 | {\r | |
869 | Gdtr = &mUnitTestHostBaseLibGdtr;\r | |
870 | }\r | |
871 | \r | |
872 | /**\r | |
873 | Writes the current Global Descriptor Table Register (GDTR) descriptor.\r | |
874 | \r | |
875 | Writes and the current GDTR descriptor specified by Gdtr. This function is\r | |
876 | only available on IA-32 and x64.\r | |
877 | \r | |
878 | If Gdtr is NULL, then ASSERT().\r | |
879 | \r | |
880 | @param Gdtr The pointer to a GDTR descriptor.\r | |
881 | \r | |
882 | **/\r | |
883 | VOID\r | |
884 | EFIAPI\r | |
885 | UnitTestHostBaseLibAsmWriteGdtr (\r | |
2f88bd3a | 886 | IN CONST IA32_DESCRIPTOR *Gdtr\r |
540fd45f MK |
887 | )\r |
888 | {\r | |
889 | CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr, sizeof (IA32_DESCRIPTOR));\r | |
890 | }\r | |
891 | \r | |
892 | /**\r | |
893 | Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.\r | |
894 | \r | |
895 | Reads and returns the current IDTR descriptor and returns it in Idtr. This\r | |
896 | function is only available on IA-32 and x64.\r | |
897 | \r | |
898 | If Idtr is NULL, then ASSERT().\r | |
899 | \r | |
900 | @param Idtr The pointer to a IDTR descriptor.\r | |
901 | \r | |
902 | **/\r | |
903 | VOID\r | |
904 | EFIAPI\r | |
905 | UnitTestHostBaseLibAsmReadIdtr (\r | |
2f88bd3a | 906 | OUT IA32_DESCRIPTOR *Idtr\r |
540fd45f MK |
907 | )\r |
908 | {\r | |
909 | Idtr = &mUnitTestHostBaseLibIdtr;\r | |
910 | }\r | |
911 | \r | |
912 | /**\r | |
913 | Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.\r | |
914 | \r | |
915 | Writes the current IDTR descriptor and returns it in Idtr. This function is\r | |
916 | only available on IA-32 and x64.\r | |
917 | \r | |
918 | If Idtr is NULL, then ASSERT().\r | |
919 | \r | |
920 | @param Idtr The pointer to a IDTR descriptor.\r | |
921 | \r | |
922 | **/\r | |
923 | VOID\r | |
924 | EFIAPI\r | |
925 | UnitTestHostBaseLibAsmWriteIdtr (\r | |
2f88bd3a | 926 | IN CONST IA32_DESCRIPTOR *Idtr\r |
540fd45f MK |
927 | )\r |
928 | {\r | |
929 | CopyMem (&mUnitTestHostBaseLibIdtr, Idtr, sizeof (IA32_DESCRIPTOR));\r | |
930 | }\r | |
931 | \r | |
932 | /**\r | |
933 | Reads the current Local Descriptor Table Register(LDTR) selector.\r | |
934 | \r | |
935 | Reads and returns the current 16-bit LDTR descriptor value. This function is\r | |
936 | only available on IA-32 and x64.\r | |
937 | \r | |
938 | @return The current selector of LDT.\r | |
939 | \r | |
940 | **/\r | |
941 | UINT16\r | |
942 | EFIAPI\r | |
943 | UnitTestHostBaseLibAsmReadLdtr (\r | |
944 | VOID\r | |
945 | )\r | |
946 | {\r | |
947 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR];\r | |
948 | }\r | |
949 | \r | |
950 | /**\r | |
951 | Writes the current Local Descriptor Table Register (LDTR) selector.\r | |
952 | \r | |
953 | Writes and the current LDTR descriptor specified by Ldtr. This function is\r | |
954 | only available on IA-32 and x64.\r | |
955 | \r | |
956 | @param Ldtr 16-bit LDTR selector value.\r | |
957 | \r | |
958 | **/\r | |
959 | VOID\r | |
960 | EFIAPI\r | |
961 | UnitTestHostBaseLibAsmWriteLdtr (\r | |
2f88bd3a | 962 | IN UINT16 Ldtr\r |
540fd45f MK |
963 | )\r |
964 | {\r | |
965 | mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] = Ldtr;\r | |
966 | }\r | |
967 | \r | |
968 | /**\r | |
969 | Reads the current value of a Performance Counter (PMC).\r | |
970 | \r | |
971 | Reads and returns the current value of performance counter specified by\r | |
972 | Index. This function is only available on IA-32 and x64.\r | |
973 | \r | |
974 | @param Index The 32-bit Performance Counter index to read.\r | |
975 | \r | |
976 | @return The value of the PMC specified by Index.\r | |
977 | \r | |
978 | **/\r | |
979 | UINT64\r | |
980 | EFIAPI\r | |
981 | UnitTestHostBaseLibAsmReadPmc (\r | |
2f88bd3a | 982 | IN UINT32 Index\r |
540fd45f MK |
983 | )\r |
984 | {\r | |
985 | return 0;\r | |
986 | }\r | |
987 | \r | |
988 | /**\r | |
989 | Sets up a monitor buffer that is used by AsmMwait().\r | |
990 | \r | |
991 | Executes a MONITOR instruction with the register state specified by Eax, Ecx\r | |
992 | and Edx. Returns Eax. This function is only available on IA-32 and x64.\r | |
993 | \r | |
994 | @param Eax The value to load into EAX or RAX before executing the MONITOR\r | |
995 | instruction.\r | |
996 | @param Ecx The value to load into ECX or RCX before executing the MONITOR\r | |
997 | instruction.\r | |
998 | @param Edx The value to load into EDX or RDX before executing the MONITOR\r | |
999 | instruction.\r | |
1000 | \r | |
1001 | @return Eax\r | |
1002 | \r | |
1003 | **/\r | |
1004 | UINTN\r | |
1005 | EFIAPI\r | |
1006 | UnitTestHostBaseLibAsmMonitor (\r | |
2f88bd3a MK |
1007 | IN UINTN Eax,\r |
1008 | IN UINTN Ecx,\r | |
1009 | IN UINTN Edx\r | |
540fd45f MK |
1010 | )\r |
1011 | {\r | |
1012 | return Eax;\r | |
1013 | }\r | |
1014 | \r | |
1015 | /**\r | |
1016 | Executes an MWAIT instruction.\r | |
1017 | \r | |
1018 | Executes an MWAIT instruction with the register state specified by Eax and\r | |
1019 | Ecx. Returns Eax. This function is only available on IA-32 and x64.\r | |
1020 | \r | |
1021 | @param Eax The value to load into EAX or RAX before executing the MONITOR\r | |
1022 | instruction.\r | |
1023 | @param Ecx The value to load into ECX or RCX before executing the MONITOR\r | |
1024 | instruction.\r | |
1025 | \r | |
1026 | @return Eax\r | |
1027 | \r | |
1028 | **/\r | |
1029 | UINTN\r | |
1030 | EFIAPI\r | |
1031 | UnitTestHostBaseLibAsmMwait (\r | |
2f88bd3a MK |
1032 | IN UINTN Eax,\r |
1033 | IN UINTN Ecx\r | |
540fd45f MK |
1034 | )\r |
1035 | {\r | |
1036 | return Eax;\r | |
1037 | }\r | |
1038 | \r | |
1039 | /**\r | |
1040 | Executes a WBINVD instruction.\r | |
1041 | \r | |
1042 | Executes a WBINVD instruction. This function is only available on IA-32 and\r | |
1043 | x64.\r | |
1044 | \r | |
1045 | **/\r | |
1046 | VOID\r | |
1047 | EFIAPI\r | |
1048 | UnitTestHostBaseLibAsmWbinvd (\r | |
1049 | VOID\r | |
1050 | )\r | |
1051 | {\r | |
1052 | }\r | |
1053 | \r | |
1054 | /**\r | |
1055 | Executes a INVD instruction.\r | |
1056 | \r | |
1057 | Executes a INVD instruction. This function is only available on IA-32 and\r | |
1058 | x64.\r | |
1059 | \r | |
1060 | **/\r | |
1061 | VOID\r | |
1062 | EFIAPI\r | |
1063 | UnitTestHostBaseLibAsmInvd (\r | |
1064 | VOID\r | |
1065 | )\r | |
1066 | {\r | |
1067 | }\r | |
1068 | \r | |
1069 | /**\r | |
1070 | Flushes a cache line from all the instruction and data caches within the\r | |
1071 | coherency domain of the CPU.\r | |
1072 | \r | |
1073 | Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r | |
1074 | This function is only available on IA-32 and x64.\r | |
1075 | \r | |
1076 | @param LinearAddress The address of the cache line to flush. If the CPU is\r | |
1077 | in a physical addressing mode, then LinearAddress is a\r | |
1078 | physical address. If the CPU is in a virtual\r | |
1079 | addressing mode, then LinearAddress is a virtual\r | |
1080 | address.\r | |
1081 | \r | |
1082 | @return LinearAddress.\r | |
1083 | **/\r | |
1084 | VOID *\r | |
1085 | EFIAPI\r | |
1086 | UnitTestHostBaseLibAsmFlushCacheLine (\r | |
2f88bd3a | 1087 | IN VOID *LinearAddress\r |
540fd45f MK |
1088 | )\r |
1089 | {\r | |
1090 | return LinearAddress;\r | |
1091 | }\r | |
1092 | \r | |
1093 | /**\r | |
1094 | Enables the 32-bit paging mode on the CPU.\r | |
1095 | \r | |
1096 | Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r | |
1097 | must be properly initialized prior to calling this service. This function\r | |
1098 | assumes the current execution mode is 32-bit protected mode. This function is\r | |
1099 | only available on IA-32. After the 32-bit paging mode is enabled, control is\r | |
1100 | transferred to the function specified by EntryPoint using the new stack\r | |
1101 | specified by NewStack and passing in the parameters specified by Context1 and\r | |
1102 | Context2. Context1 and Context2 are optional and may be NULL. The function\r | |
1103 | EntryPoint must never return.\r | |
1104 | \r | |
1105 | If the current execution mode is not 32-bit protected mode, then ASSERT().\r | |
1106 | If EntryPoint is NULL, then ASSERT().\r | |
1107 | If NewStack is NULL, then ASSERT().\r | |
1108 | \r | |
1109 | There are a number of constraints that must be followed before calling this\r | |
1110 | function:\r | |
1111 | 1) Interrupts must be disabled.\r | |
1112 | 2) The caller must be in 32-bit protected mode with flat descriptors. This\r | |
1113 | means all descriptors must have a base of 0 and a limit of 4GB.\r | |
1114 | 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat\r | |
1115 | descriptors.\r | |
1116 | 4) CR3 must point to valid page tables that will be used once the transition\r | |
1117 | is complete, and those page tables must guarantee that the pages for this\r | |
1118 | function and the stack are identity mapped.\r | |
1119 | \r | |
1120 | @param EntryPoint A pointer to function to call with the new stack after\r | |
1121 | paging is enabled.\r | |
1122 | @param Context1 A pointer to the context to pass into the EntryPoint\r | |
1123 | function as the first parameter after paging is enabled.\r | |
1124 | @param Context2 A pointer to the context to pass into the EntryPoint\r | |
1125 | function as the second parameter after paging is enabled.\r | |
1126 | @param NewStack A pointer to the new stack to use for the EntryPoint\r | |
1127 | function after paging is enabled.\r | |
1128 | \r | |
1129 | **/\r | |
1130 | VOID\r | |
1131 | EFIAPI\r | |
1132 | UnitTestHostBaseLibAsmEnablePaging32 (\r | |
1133 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r | |
d0e2f823 MK |
1134 | IN VOID *Context1 OPTIONAL,\r |
1135 | IN VOID *Context2 OPTIONAL,\r | |
540fd45f MK |
1136 | IN VOID *NewStack\r |
1137 | )\r | |
1138 | {\r | |
1139 | EntryPoint (Context1, Context2);\r | |
1140 | }\r | |
1141 | \r | |
1142 | /**\r | |
1143 | Disables the 32-bit paging mode on the CPU.\r | |
1144 | \r | |
1145 | Disables the 32-bit paging mode on the CPU and returns to 32-bit protected\r | |
1146 | mode. This function assumes the current execution mode is 32-paged protected\r | |
1147 | mode. This function is only available on IA-32. After the 32-bit paging mode\r | |
1148 | is disabled, control is transferred to the function specified by EntryPoint\r | |
1149 | using the new stack specified by NewStack and passing in the parameters\r | |
1150 | specified by Context1 and Context2. Context1 and Context2 are optional and\r | |
1151 | may be NULL. The function EntryPoint must never return.\r | |
1152 | \r | |
1153 | If the current execution mode is not 32-bit paged mode, then ASSERT().\r | |
1154 | If EntryPoint is NULL, then ASSERT().\r | |
1155 | If NewStack is NULL, then ASSERT().\r | |
1156 | \r | |
1157 | There are a number of constraints that must be followed before calling this\r | |
1158 | function:\r | |
1159 | 1) Interrupts must be disabled.\r | |
1160 | 2) The caller must be in 32-bit paged mode.\r | |
1161 | 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.\r | |
1162 | 4) CR3 must point to valid page tables that guarantee that the pages for\r | |
1163 | this function and the stack are identity mapped.\r | |
1164 | \r | |
1165 | @param EntryPoint A pointer to function to call with the new stack after\r | |
1166 | paging is disabled.\r | |
1167 | @param Context1 A pointer to the context to pass into the EntryPoint\r | |
1168 | function as the first parameter after paging is disabled.\r | |
1169 | @param Context2 A pointer to the context to pass into the EntryPoint\r | |
1170 | function as the second parameter after paging is\r | |
1171 | disabled.\r | |
1172 | @param NewStack A pointer to the new stack to use for the EntryPoint\r | |
1173 | function after paging is disabled.\r | |
1174 | \r | |
1175 | **/\r | |
1176 | VOID\r | |
1177 | EFIAPI\r | |
1178 | UnitTestHostBaseLibAsmDisablePaging32 (\r | |
1179 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r | |
d0e2f823 MK |
1180 | IN VOID *Context1 OPTIONAL,\r |
1181 | IN VOID *Context2 OPTIONAL,\r | |
540fd45f MK |
1182 | IN VOID *NewStack\r |
1183 | )\r | |
1184 | {\r | |
1185 | EntryPoint (Context1, Context2);\r | |
1186 | }\r | |
1187 | \r | |
1188 | /**\r | |
1189 | Enables the 64-bit paging mode on the CPU.\r | |
1190 | \r | |
1191 | Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r | |
1192 | must be properly initialized prior to calling this service. This function\r | |
1193 | assumes the current execution mode is 32-bit protected mode with flat\r | |
1194 | descriptors. This function is only available on IA-32. After the 64-bit\r | |
1195 | paging mode is enabled, control is transferred to the function specified by\r | |
1196 | EntryPoint using the new stack specified by NewStack and passing in the\r | |
1197 | parameters specified by Context1 and Context2. Context1 and Context2 are\r | |
1198 | optional and may be 0. The function EntryPoint must never return.\r | |
1199 | \r | |
1200 | If the current execution mode is not 32-bit protected mode with flat\r | |
1201 | descriptors, then ASSERT().\r | |
1202 | If EntryPoint is 0, then ASSERT().\r | |
1203 | If NewStack is 0, then ASSERT().\r | |
1204 | \r | |
1205 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r | |
1206 | is called. The descriptor in the GDT that this selector\r | |
1207 | references must be setup for long mode.\r | |
1208 | @param EntryPoint The 64-bit virtual address of the function to call with\r | |
1209 | the new stack after paging is enabled.\r | |
1210 | @param Context1 The 64-bit virtual address of the context to pass into\r | |
1211 | the EntryPoint function as the first parameter after\r | |
1212 | paging is enabled.\r | |
1213 | @param Context2 The 64-bit virtual address of the context to pass into\r | |
1214 | the EntryPoint function as the second parameter after\r | |
1215 | paging is enabled.\r | |
1216 | @param NewStack The 64-bit virtual address of the new stack to use for\r | |
1217 | the EntryPoint function after paging is enabled.\r | |
1218 | \r | |
1219 | **/\r | |
1220 | VOID\r | |
1221 | EFIAPI\r | |
1222 | UnitTestHostBaseLibAsmEnablePaging64 (\r | |
2f88bd3a MK |
1223 | IN UINT16 Cs,\r |
1224 | IN UINT64 EntryPoint,\r | |
1225 | IN UINT64 Context1 OPTIONAL,\r | |
1226 | IN UINT64 Context2 OPTIONAL,\r | |
1227 | IN UINT64 NewStack\r | |
540fd45f MK |
1228 | )\r |
1229 | {\r | |
1230 | SWITCH_STACK_ENTRY_POINT NewEntryPoint;\r | |
1231 | \r | |
1232 | NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);\r | |
1233 | NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);\r | |
1234 | }\r | |
1235 | \r | |
1236 | /**\r | |
1237 | Disables the 64-bit paging mode on the CPU.\r | |
1238 | \r | |
1239 | Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r | |
1240 | mode. This function assumes the current execution mode is 64-paging mode.\r | |
1241 | This function is only available on x64. After the 64-bit paging mode is\r | |
1242 | disabled, control is transferred to the function specified by EntryPoint\r | |
1243 | using the new stack specified by NewStack and passing in the parameters\r | |
1244 | specified by Context1 and Context2. Context1 and Context2 are optional and\r | |
1245 | may be 0. The function EntryPoint must never return.\r | |
1246 | \r | |
1247 | If the current execution mode is not 64-bit paged mode, then ASSERT().\r | |
1248 | If EntryPoint is 0, then ASSERT().\r | |
1249 | If NewStack is 0, then ASSERT().\r | |
1250 | \r | |
1251 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r | |
1252 | is called. The descriptor in the GDT that this selector\r | |
1253 | references must be setup for 32-bit protected mode.\r | |
1254 | @param EntryPoint The 64-bit virtual address of the function to call with\r | |
1255 | the new stack after paging is disabled.\r | |
1256 | @param Context1 The 64-bit virtual address of the context to pass into\r | |
1257 | the EntryPoint function as the first parameter after\r | |
1258 | paging is disabled.\r | |
1259 | @param Context2 The 64-bit virtual address of the context to pass into\r | |
1260 | the EntryPoint function as the second parameter after\r | |
1261 | paging is disabled.\r | |
1262 | @param NewStack The 64-bit virtual address of the new stack to use for\r | |
1263 | the EntryPoint function after paging is disabled.\r | |
1264 | \r | |
1265 | **/\r | |
1266 | VOID\r | |
1267 | EFIAPI\r | |
1268 | UnitTestHostBaseLibAsmDisablePaging64 (\r | |
2f88bd3a MK |
1269 | IN UINT16 Cs,\r |
1270 | IN UINT32 EntryPoint,\r | |
1271 | IN UINT32 Context1 OPTIONAL,\r | |
1272 | IN UINT32 Context2 OPTIONAL,\r | |
1273 | IN UINT32 NewStack\r | |
540fd45f MK |
1274 | )\r |
1275 | {\r | |
1276 | SWITCH_STACK_ENTRY_POINT NewEntryPoint;\r | |
1277 | \r | |
1278 | NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);\r | |
1279 | NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);\r | |
1280 | }\r | |
1281 | \r | |
1282 | /**\r | |
1283 | Retrieves the properties for 16-bit thunk functions.\r | |
1284 | \r | |
1285 | Computes the size of the buffer and stack below 1MB required to use the\r | |
1286 | AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This\r | |
1287 | buffer size is returned in RealModeBufferSize, and the stack size is returned\r | |
1288 | in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r | |
1289 | then the actual minimum stack size is ExtraStackSize plus the maximum number\r | |
1290 | of bytes that need to be passed to the 16-bit real mode code.\r | |
1291 | \r | |
1292 | If RealModeBufferSize is NULL, then ASSERT().\r | |
1293 | If ExtraStackSize is NULL, then ASSERT().\r | |
1294 | \r | |
1295 | @param RealModeBufferSize A pointer to the size of the buffer below 1MB\r | |
1296 | required to use the 16-bit thunk functions.\r | |
1297 | @param ExtraStackSize A pointer to the extra size of stack below 1MB\r | |
1298 | that the 16-bit thunk functions require for\r | |
1299 | temporary storage in the transition to and from\r | |
1300 | 16-bit real mode.\r | |
1301 | \r | |
1302 | **/\r | |
1303 | VOID\r | |
1304 | EFIAPI\r | |
1305 | UnitTestHostBaseLibAsmGetThunk16Properties (\r | |
2f88bd3a MK |
1306 | OUT UINT32 *RealModeBufferSize,\r |
1307 | OUT UINT32 *ExtraStackSize\r | |
540fd45f MK |
1308 | )\r |
1309 | {\r | |
1310 | *RealModeBufferSize = 0;\r | |
1311 | *ExtraStackSize = 0;\r | |
1312 | }\r | |
1313 | \r | |
1314 | /**\r | |
1315 | Prepares all structures a code required to use AsmThunk16().\r | |
1316 | \r | |
1317 | Prepares all structures and code required to use AsmThunk16().\r | |
1318 | \r | |
1319 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
1320 | virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r | |
1321 | \r | |
1322 | If ThunkContext is NULL, then ASSERT().\r | |
1323 | \r | |
1324 | @param ThunkContext A pointer to the context structure that describes the\r | |
1325 | 16-bit real mode code to call.\r | |
1326 | \r | |
1327 | **/\r | |
1328 | VOID\r | |
1329 | EFIAPI\r | |
1330 | UnitTestHostBaseLibAsmPrepareThunk16 (\r | |
2f88bd3a | 1331 | IN OUT THUNK_CONTEXT *ThunkContext\r |
540fd45f MK |
1332 | )\r |
1333 | {\r | |
1334 | }\r | |
1335 | \r | |
1336 | /**\r | |
1337 | Transfers control to a 16-bit real mode entry point and returns the results.\r | |
1338 | \r | |
1339 | Transfers control to a 16-bit real mode entry point and returns the results.\r | |
1340 | AsmPrepareThunk16() must be called with ThunkContext before this function is used.\r | |
1341 | This function must be called with interrupts disabled.\r | |
1342 | \r | |
1343 | The register state from the RealModeState field of ThunkContext is restored just prior\r | |
1344 | to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,\r | |
1345 | which is used to set the interrupt state when a 16-bit real mode entry point is called.\r | |
1346 | Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.\r | |
1347 | The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to\r | |
1348 | the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.\r | |
1349 | The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,\r | |
1350 | so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment\r | |
1351 | and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry\r | |
1352 | point must exit with a RETF instruction. The register state is captured into RealModeState immediately\r | |
1353 | after the RETF instruction is executed.\r | |
1354 | \r | |
1355 | If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r | |
1356 | or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure\r | |
1357 | the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.\r | |
1358 | \r | |
1359 | If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r | |
1360 | then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.\r | |
1361 | This includes the base vectors, the interrupt masks, and the edge/level trigger mode.\r | |
1362 | \r | |
1363 | If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code\r | |
1364 | is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.\r | |
1365 | \r | |
1366 | If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r | |
1367 | ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to\r | |
1368 | disable the A20 mask.\r | |
1369 | \r | |
1370 | If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in\r | |
1371 | ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,\r | |
1372 | then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r | |
1373 | \r | |
1374 | If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in\r | |
1375 | ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r | |
1376 | \r | |
1377 | If ThunkContext is NULL, then ASSERT().\r | |
1378 | If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().\r | |
1379 | If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r | |
1380 | ThunkAttributes, then ASSERT().\r | |
1381 | \r | |
1382 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
1383 | virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.\r | |
1384 | \r | |
1385 | @param ThunkContext A pointer to the context structure that describes the\r | |
1386 | 16-bit real mode code to call.\r | |
1387 | \r | |
1388 | **/\r | |
1389 | VOID\r | |
1390 | EFIAPI\r | |
1391 | UnitTestHostBaseLibAsmThunk16 (\r | |
2f88bd3a | 1392 | IN OUT THUNK_CONTEXT *ThunkContext\r |
540fd45f MK |
1393 | )\r |
1394 | {\r | |
1395 | }\r | |
1396 | \r | |
1397 | /**\r | |
1398 | Prepares all structures and code for a 16-bit real mode thunk, transfers\r | |
1399 | control to a 16-bit real mode entry point, and returns the results.\r | |
1400 | \r | |
1401 | Prepares all structures and code for a 16-bit real mode thunk, transfers\r | |
1402 | control to a 16-bit real mode entry point, and returns the results. If the\r | |
1403 | caller only need to perform a single 16-bit real mode thunk, then this\r | |
1404 | service should be used. If the caller intends to make more than one 16-bit\r | |
1405 | real mode thunk, then it is more efficient if AsmPrepareThunk16() is called\r | |
1406 | once and AsmThunk16() can be called for each 16-bit real mode thunk.\r | |
1407 | \r | |
1408 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
1409 | virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r | |
1410 | \r | |
1411 | See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.\r | |
1412 | \r | |
1413 | @param ThunkContext A pointer to the context structure that describes the\r | |
1414 | 16-bit real mode code to call.\r | |
1415 | \r | |
1416 | **/\r | |
1417 | VOID\r | |
1418 | EFIAPI\r | |
1419 | UnitTestHostBaseLibAsmPrepareAndThunk16 (\r | |
2f88bd3a | 1420 | IN OUT THUNK_CONTEXT *ThunkContext\r |
540fd45f MK |
1421 | )\r |
1422 | {\r | |
1423 | }\r | |
1424 | \r | |
1425 | /**\r | |
1426 | Load given selector into TR register.\r | |
1427 | \r | |
1428 | @param[in] Selector Task segment selector\r | |
1429 | **/\r | |
1430 | VOID\r | |
1431 | EFIAPI\r | |
1432 | UnitTestHostBaseLibAsmWriteTr (\r | |
2f88bd3a | 1433 | IN UINT16 Selector\r |
540fd45f MK |
1434 | )\r |
1435 | {\r | |
1436 | mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] = Selector;\r | |
1437 | }\r | |
1438 | \r | |
1439 | /**\r | |
1440 | Performs a serializing operation on all load-from-memory instructions that\r | |
1441 | were issued prior the AsmLfence function.\r | |
1442 | \r | |
1443 | Executes a LFENCE instruction. This function is only available on IA-32 and x64.\r | |
1444 | \r | |
1445 | **/\r | |
1446 | VOID\r | |
1447 | EFIAPI\r | |
1448 | UnitTestHostBaseLibAsmLfence (\r | |
1449 | VOID\r | |
1450 | )\r | |
1451 | {\r | |
1452 | }\r | |
1453 | \r | |
1454 | /**\r | |
1455 | Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r | |
1456 | word, dword or qword operand is encoded at the end of the instruction's\r | |
1457 | binary representation.\r | |
1458 | \r | |
1459 | This function should be used to update object code that was compiled with\r | |
1460 | NASM from assembly source code. Example:\r | |
1461 | \r | |
1462 | NASM source code:\r | |
1463 | \r | |
1464 | mov eax, strict dword 0 ; the imm32 zero operand will be patched\r | |
1465 | ASM_PFX(gPatchCr3):\r | |
1466 | mov cr3, eax\r | |
1467 | \r | |
1468 | C source code:\r | |
1469 | \r | |
1470 | X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r | |
1471 | PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r | |
1472 | \r | |
1473 | @param[out] InstructionEnd Pointer right past the instruction to patch. The\r | |
1474 | immediate operand to patch is expected to\r | |
1475 | comprise the trailing bytes of the instruction.\r | |
1476 | If InstructionEnd is closer to address 0 than\r | |
1477 | ValueSize permits, then ASSERT().\r | |
1478 | \r | |
1479 | @param[in] PatchValue The constant to write to the immediate operand.\r | |
1480 | The caller is responsible for ensuring that\r | |
1481 | PatchValue can be represented in the byte, word,\r | |
1482 | dword or qword operand (as indicated through\r | |
1483 | ValueSize); otherwise ASSERT().\r | |
1484 | \r | |
1485 | @param[in] ValueSize The size of the operand in bytes; must be 1, 2,\r | |
1486 | 4, or 8. ASSERT() otherwise.\r | |
1487 | **/\r | |
1488 | VOID\r | |
1489 | EFIAPI\r | |
1490 | UnitTestHostBaseLibPatchInstructionX86 (\r | |
2f88bd3a MK |
1491 | OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r |
1492 | IN UINT64 PatchValue,\r | |
1493 | IN UINTN ValueSize\r | |
540fd45f MK |
1494 | )\r |
1495 | {\r | |
1496 | }\r | |
1497 | \r | |
1498 | /**\r | |
1499 | Retrieves CPUID information.\r | |
1500 | \r | |
1501 | Executes the CPUID instruction with EAX set to the value specified by Index.\r | |
1502 | This function always returns Index.\r | |
1503 | If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r | |
1504 | If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r | |
1505 | If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r | |
1506 | If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r | |
1507 | This function is only available on IA-32 and x64.\r | |
1508 | \r | |
1509 | @param Index The 32-bit value to load into EAX prior to invoking the CPUID\r | |
1510 | instruction.\r | |
1511 | @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r | |
1512 | instruction. This is an optional parameter that may be NULL.\r | |
1513 | @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r | |
1514 | instruction. This is an optional parameter that may be NULL.\r | |
1515 | @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r | |
1516 | instruction. This is an optional parameter that may be NULL.\r | |
1517 | @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r | |
1518 | instruction. This is an optional parameter that may be NULL.\r | |
1519 | \r | |
1520 | @return Index.\r | |
1521 | \r | |
1522 | **/\r | |
1523 | UINT32\r | |
1524 | EFIAPI\r | |
1525 | AsmCpuid (\r | |
2f88bd3a MK |
1526 | IN UINT32 Index,\r |
1527 | OUT UINT32 *Eax OPTIONAL,\r | |
1528 | OUT UINT32 *Ebx OPTIONAL,\r | |
1529 | OUT UINT32 *Ecx OPTIONAL,\r | |
1530 | OUT UINT32 *Edx OPTIONAL\r | |
540fd45f MK |
1531 | )\r |
1532 | {\r | |
1533 | return gUnitTestHostBaseLib.X86->AsmCpuid (Index, Eax, Ebx, Ecx, Edx);\r | |
1534 | }\r | |
1535 | \r | |
1536 | /**\r | |
1537 | Retrieves CPUID information using an extended leaf identifier.\r | |
1538 | \r | |
1539 | Executes the CPUID instruction with EAX set to the value specified by Index\r | |
1540 | and ECX set to the value specified by SubIndex. This function always returns\r | |
1541 | Index. This function is only available on IA-32 and x64.\r | |
1542 | \r | |
1543 | If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r | |
1544 | If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r | |
1545 | If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r | |
1546 | If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r | |
1547 | \r | |
1548 | @param Index The 32-bit value to load into EAX prior to invoking the\r | |
1549 | CPUID instruction.\r | |
1550 | @param SubIndex The 32-bit value to load into ECX prior to invoking the\r | |
1551 | CPUID instruction.\r | |
1552 | @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r | |
1553 | instruction. This is an optional parameter that may be\r | |
1554 | NULL.\r | |
1555 | @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r | |
1556 | instruction. This is an optional parameter that may be\r | |
1557 | NULL.\r | |
1558 | @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r | |
1559 | instruction. This is an optional parameter that may be\r | |
1560 | NULL.\r | |
1561 | @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r | |
1562 | instruction. This is an optional parameter that may be\r | |
1563 | NULL.\r | |
1564 | \r | |
1565 | @return Index.\r | |
1566 | \r | |
1567 | **/\r | |
1568 | UINT32\r | |
1569 | EFIAPI\r | |
1570 | AsmCpuidEx (\r | |
2f88bd3a MK |
1571 | IN UINT32 Index,\r |
1572 | IN UINT32 SubIndex,\r | |
1573 | OUT UINT32 *Eax OPTIONAL,\r | |
1574 | OUT UINT32 *Ebx OPTIONAL,\r | |
1575 | OUT UINT32 *Ecx OPTIONAL,\r | |
1576 | OUT UINT32 *Edx OPTIONAL\r | |
540fd45f MK |
1577 | )\r |
1578 | {\r | |
1579 | return gUnitTestHostBaseLib.X86->AsmCpuidEx (Index, SubIndex, Eax, Ebx, Ecx, Edx);\r | |
1580 | }\r | |
1581 | \r | |
1582 | /**\r | |
1583 | Set CD bit and clear NW bit of CR0 followed by a WBINVD.\r | |
1584 | \r | |
1585 | Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,\r | |
1586 | and executing a WBINVD instruction. This function is only available on IA-32 and x64.\r | |
1587 | \r | |
1588 | **/\r | |
1589 | VOID\r | |
1590 | EFIAPI\r | |
1591 | AsmDisableCache (\r | |
1592 | VOID\r | |
1593 | )\r | |
1594 | {\r | |
1595 | gUnitTestHostBaseLib.X86->AsmDisableCache ();\r | |
1596 | }\r | |
1597 | \r | |
1598 | /**\r | |
1599 | Perform a WBINVD and clear both the CD and NW bits of CR0.\r | |
1600 | \r | |
1601 | Enables the caches by executing a WBINVD instruction and then clear both the CD and NW\r | |
1602 | bits of CR0 to 0. This function is only available on IA-32 and x64.\r | |
1603 | \r | |
1604 | **/\r | |
1605 | VOID\r | |
1606 | EFIAPI\r | |
1607 | AsmEnableCache (\r | |
1608 | VOID\r | |
1609 | )\r | |
1610 | {\r | |
1611 | gUnitTestHostBaseLib.X86->AsmEnableCache ();\r | |
1612 | }\r | |
1613 | \r | |
1614 | /**\r | |
1615 | Returns a 64-bit Machine Specific Register(MSR).\r | |
1616 | \r | |
1617 | Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r | |
1618 | performed on Index, and some Index values may cause CPU exceptions. The\r | |
1619 | caller must either guarantee that Index is valid, or the caller must set up\r | |
1620 | exception handlers to catch the exceptions. This function is only available\r | |
1621 | on IA-32 and x64.\r | |
1622 | \r | |
1623 | @param Index The 32-bit MSR index to read.\r | |
1624 | \r | |
1625 | @return The value of the MSR identified by Index.\r | |
1626 | \r | |
1627 | **/\r | |
1628 | UINT64\r | |
1629 | EFIAPI\r | |
1630 | AsmReadMsr64 (\r | |
2f88bd3a | 1631 | IN UINT32 Index\r |
540fd45f MK |
1632 | )\r |
1633 | {\r | |
1634 | return gUnitTestHostBaseLib.X86->AsmReadMsr64 (Index);\r | |
1635 | }\r | |
1636 | \r | |
1637 | /**\r | |
1638 | Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r | |
1639 | value.\r | |
1640 | \r | |
1641 | Writes the 64-bit value specified by Value to the MSR specified by Index. The\r | |
1642 | 64-bit value written to the MSR is returned. No parameter checking is\r | |
1643 | performed on Index or Value, and some of these may cause CPU exceptions. The\r | |
1644 | caller must either guarantee that Index and Value are valid, or the caller\r | |
1645 | must establish proper exception handlers. This function is only available on\r | |
1646 | IA-32 and x64.\r | |
1647 | \r | |
1648 | @param Index The 32-bit MSR index to write.\r | |
1649 | @param Value The 64-bit value to write to the MSR.\r | |
1650 | \r | |
1651 | @return Value\r | |
1652 | \r | |
1653 | **/\r | |
1654 | UINT64\r | |
1655 | EFIAPI\r | |
1656 | AsmWriteMsr64 (\r | |
2f88bd3a MK |
1657 | IN UINT32 Index,\r |
1658 | IN UINT64 Value\r | |
540fd45f MK |
1659 | )\r |
1660 | {\r | |
1661 | return gUnitTestHostBaseLib.X86->AsmWriteMsr64 (Index, Value);\r | |
1662 | }\r | |
1663 | \r | |
1664 | /**\r | |
1665 | Reads the current value of the Control Register 0 (CR0).\r | |
1666 | \r | |
1667 | Reads and returns the current value of CR0. This function is only available\r | |
1668 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1669 | x64.\r | |
1670 | \r | |
1671 | @return The value of the Control Register 0 (CR0).\r | |
1672 | \r | |
1673 | **/\r | |
1674 | UINTN\r | |
1675 | EFIAPI\r | |
1676 | AsmReadCr0 (\r | |
1677 | VOID\r | |
1678 | )\r | |
1679 | {\r | |
1680 | return gUnitTestHostBaseLib.X86->AsmReadCr0 ();\r | |
1681 | }\r | |
1682 | \r | |
1683 | /**\r | |
1684 | Reads the current value of the Control Register 2 (CR2).\r | |
1685 | \r | |
1686 | Reads and returns the current value of CR2. This function is only available\r | |
1687 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1688 | x64.\r | |
1689 | \r | |
1690 | @return The value of the Control Register 2 (CR2).\r | |
1691 | \r | |
1692 | **/\r | |
1693 | UINTN\r | |
1694 | EFIAPI\r | |
1695 | AsmReadCr2 (\r | |
1696 | VOID\r | |
1697 | )\r | |
1698 | {\r | |
1699 | return gUnitTestHostBaseLib.X86->AsmReadCr2 ();\r | |
1700 | }\r | |
1701 | \r | |
1702 | /**\r | |
1703 | Reads the current value of the Control Register 3 (CR3).\r | |
1704 | \r | |
1705 | Reads and returns the current value of CR3. This function is only available\r | |
1706 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1707 | x64.\r | |
1708 | \r | |
1709 | @return The value of the Control Register 3 (CR3).\r | |
1710 | \r | |
1711 | **/\r | |
1712 | UINTN\r | |
1713 | EFIAPI\r | |
1714 | AsmReadCr3 (\r | |
1715 | VOID\r | |
1716 | )\r | |
1717 | {\r | |
1718 | return gUnitTestHostBaseLib.X86->AsmReadCr3 ();\r | |
1719 | }\r | |
1720 | \r | |
1721 | /**\r | |
1722 | Reads the current value of the Control Register 4 (CR4).\r | |
1723 | \r | |
1724 | Reads and returns the current value of CR4. This function is only available\r | |
1725 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1726 | x64.\r | |
1727 | \r | |
1728 | @return The value of the Control Register 4 (CR4).\r | |
1729 | \r | |
1730 | **/\r | |
1731 | UINTN\r | |
1732 | EFIAPI\r | |
1733 | AsmReadCr4 (\r | |
1734 | VOID\r | |
1735 | )\r | |
1736 | {\r | |
1737 | return gUnitTestHostBaseLib.X86->AsmReadCr4 ();\r | |
1738 | }\r | |
1739 | \r | |
1740 | /**\r | |
1741 | Writes a value to Control Register 0 (CR0).\r | |
1742 | \r | |
1743 | Writes and returns a new value to CR0. This function is only available on\r | |
1744 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
1745 | \r | |
1746 | @param Cr0 The value to write to CR0.\r | |
1747 | \r | |
1748 | @return The value written to CR0.\r | |
1749 | \r | |
1750 | **/\r | |
1751 | UINTN\r | |
1752 | EFIAPI\r | |
1753 | AsmWriteCr0 (\r | |
1754 | UINTN Cr0\r | |
1755 | )\r | |
1756 | {\r | |
1757 | return gUnitTestHostBaseLib.X86->AsmWriteCr0 (Cr0);\r | |
1758 | }\r | |
1759 | \r | |
1760 | /**\r | |
1761 | Writes a value to Control Register 2 (CR2).\r | |
1762 | \r | |
1763 | Writes and returns a new value to CR2. This function is only available on\r | |
1764 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
1765 | \r | |
1766 | @param Cr2 The value to write to CR2.\r | |
1767 | \r | |
1768 | @return The value written to CR2.\r | |
1769 | \r | |
1770 | **/\r | |
1771 | UINTN\r | |
1772 | EFIAPI\r | |
1773 | AsmWriteCr2 (\r | |
1774 | UINTN Cr2\r | |
1775 | )\r | |
1776 | {\r | |
1777 | return gUnitTestHostBaseLib.X86->AsmWriteCr2 (Cr2);\r | |
1778 | }\r | |
1779 | \r | |
1780 | /**\r | |
1781 | Writes a value to Control Register 3 (CR3).\r | |
1782 | \r | |
1783 | Writes and returns a new value to CR3. This function is only available on\r | |
1784 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
1785 | \r | |
1786 | @param Cr3 The value to write to CR3.\r | |
1787 | \r | |
1788 | @return The value written to CR3.\r | |
1789 | \r | |
1790 | **/\r | |
1791 | UINTN\r | |
1792 | EFIAPI\r | |
1793 | AsmWriteCr3 (\r | |
1794 | UINTN Cr3\r | |
1795 | )\r | |
1796 | {\r | |
1797 | return gUnitTestHostBaseLib.X86->AsmWriteCr3 (Cr3);\r | |
1798 | }\r | |
1799 | \r | |
1800 | /**\r | |
1801 | Writes a value to Control Register 4 (CR4).\r | |
1802 | \r | |
1803 | Writes and returns a new value to CR4. This function is only available on\r | |
1804 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
1805 | \r | |
1806 | @param Cr4 The value to write to CR4.\r | |
1807 | \r | |
1808 | @return The value written to CR4.\r | |
1809 | \r | |
1810 | **/\r | |
1811 | UINTN\r | |
1812 | EFIAPI\r | |
1813 | AsmWriteCr4 (\r | |
1814 | UINTN Cr4\r | |
1815 | )\r | |
1816 | {\r | |
1817 | return gUnitTestHostBaseLib.X86->AsmWriteCr4 (Cr4);\r | |
1818 | }\r | |
1819 | \r | |
1820 | /**\r | |
1821 | Reads the current value of Debug Register 0 (DR0).\r | |
1822 | \r | |
1823 | Reads and returns the current value of DR0. This function is only available\r | |
1824 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1825 | x64.\r | |
1826 | \r | |
1827 | @return The value of Debug Register 0 (DR0).\r | |
1828 | \r | |
1829 | **/\r | |
1830 | UINTN\r | |
1831 | EFIAPI\r | |
1832 | AsmReadDr0 (\r | |
1833 | VOID\r | |
1834 | )\r | |
1835 | {\r | |
1836 | return gUnitTestHostBaseLib.X86->AsmReadDr0 ();\r | |
1837 | }\r | |
1838 | \r | |
1839 | /**\r | |
1840 | Reads the current value of Debug Register 1 (DR1).\r | |
1841 | \r | |
1842 | Reads and returns the current value of DR1. This function is only available\r | |
1843 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1844 | x64.\r | |
1845 | \r | |
1846 | @return The value of Debug Register 1 (DR1).\r | |
1847 | \r | |
1848 | **/\r | |
1849 | UINTN\r | |
1850 | EFIAPI\r | |
1851 | AsmReadDr1 (\r | |
1852 | VOID\r | |
1853 | )\r | |
1854 | {\r | |
1855 | return gUnitTestHostBaseLib.X86->AsmReadDr1 ();\r | |
1856 | }\r | |
1857 | \r | |
1858 | /**\r | |
1859 | Reads the current value of Debug Register 2 (DR2).\r | |
1860 | \r | |
1861 | Reads and returns the current value of DR2. This function is only available\r | |
1862 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1863 | x64.\r | |
1864 | \r | |
1865 | @return The value of Debug Register 2 (DR2).\r | |
1866 | \r | |
1867 | **/\r | |
1868 | UINTN\r | |
1869 | EFIAPI\r | |
1870 | AsmReadDr2 (\r | |
1871 | VOID\r | |
1872 | )\r | |
1873 | {\r | |
1874 | return gUnitTestHostBaseLib.X86->AsmReadDr2 ();\r | |
1875 | }\r | |
1876 | \r | |
1877 | /**\r | |
1878 | Reads the current value of Debug Register 3 (DR3).\r | |
1879 | \r | |
1880 | Reads and returns the current value of DR3. This function is only available\r | |
1881 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1882 | x64.\r | |
1883 | \r | |
1884 | @return The value of Debug Register 3 (DR3).\r | |
1885 | \r | |
1886 | **/\r | |
1887 | UINTN\r | |
1888 | EFIAPI\r | |
1889 | AsmReadDr3 (\r | |
1890 | VOID\r | |
1891 | )\r | |
1892 | {\r | |
1893 | return gUnitTestHostBaseLib.X86->AsmReadDr3 ();\r | |
1894 | }\r | |
1895 | \r | |
1896 | /**\r | |
1897 | Reads the current value of Debug Register 4 (DR4).\r | |
1898 | \r | |
1899 | Reads and returns the current value of DR4. This function is only available\r | |
1900 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1901 | x64.\r | |
1902 | \r | |
1903 | @return The value of Debug Register 4 (DR4).\r | |
1904 | \r | |
1905 | **/\r | |
1906 | UINTN\r | |
1907 | EFIAPI\r | |
1908 | AsmReadDr4 (\r | |
1909 | VOID\r | |
1910 | )\r | |
1911 | {\r | |
1912 | return gUnitTestHostBaseLib.X86->AsmReadDr4 ();\r | |
1913 | }\r | |
1914 | \r | |
1915 | /**\r | |
1916 | Reads the current value of Debug Register 5 (DR5).\r | |
1917 | \r | |
1918 | Reads and returns the current value of DR5. This function is only available\r | |
1919 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1920 | x64.\r | |
1921 | \r | |
1922 | @return The value of Debug Register 5 (DR5).\r | |
1923 | \r | |
1924 | **/\r | |
1925 | UINTN\r | |
1926 | EFIAPI\r | |
1927 | AsmReadDr5 (\r | |
1928 | VOID\r | |
1929 | )\r | |
1930 | {\r | |
1931 | return gUnitTestHostBaseLib.X86->AsmReadDr5 ();\r | |
1932 | }\r | |
1933 | \r | |
1934 | /**\r | |
1935 | Reads the current value of Debug Register 6 (DR6).\r | |
1936 | \r | |
1937 | Reads and returns the current value of DR6. This function is only available\r | |
1938 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1939 | x64.\r | |
1940 | \r | |
1941 | @return The value of Debug Register 6 (DR6).\r | |
1942 | \r | |
1943 | **/\r | |
1944 | UINTN\r | |
1945 | EFIAPI\r | |
1946 | AsmReadDr6 (\r | |
1947 | VOID\r | |
1948 | )\r | |
1949 | {\r | |
1950 | return gUnitTestHostBaseLib.X86->AsmReadDr6 ();\r | |
1951 | }\r | |
1952 | \r | |
1953 | /**\r | |
1954 | Reads the current value of Debug Register 7 (DR7).\r | |
1955 | \r | |
1956 | Reads and returns the current value of DR7. This function is only available\r | |
1957 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
1958 | x64.\r | |
1959 | \r | |
1960 | @return The value of Debug Register 7 (DR7).\r | |
1961 | \r | |
1962 | **/\r | |
1963 | UINTN\r | |
1964 | EFIAPI\r | |
1965 | AsmReadDr7 (\r | |
1966 | VOID\r | |
1967 | )\r | |
1968 | {\r | |
1969 | return gUnitTestHostBaseLib.X86->AsmReadDr7 ();\r | |
1970 | }\r | |
1971 | \r | |
1972 | /**\r | |
1973 | Writes a value to Debug Register 0 (DR0).\r | |
1974 | \r | |
1975 | Writes and returns a new value to DR0. This function is only available on\r | |
1976 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
1977 | \r | |
1978 | @param Dr0 The value to write to Dr0.\r | |
1979 | \r | |
1980 | @return The value written to Debug Register 0 (DR0).\r | |
1981 | \r | |
1982 | **/\r | |
1983 | UINTN\r | |
1984 | EFIAPI\r | |
1985 | AsmWriteDr0 (\r | |
1986 | UINTN Dr0\r | |
1987 | )\r | |
1988 | {\r | |
1989 | return gUnitTestHostBaseLib.X86->AsmWriteDr0 (Dr0);\r | |
1990 | }\r | |
1991 | \r | |
1992 | /**\r | |
1993 | Writes a value to Debug Register 1 (DR1).\r | |
1994 | \r | |
1995 | Writes and returns a new value to DR1. This function is only available on\r | |
1996 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
1997 | \r | |
1998 | @param Dr1 The value to write to Dr1.\r | |
1999 | \r | |
2000 | @return The value written to Debug Register 1 (DR1).\r | |
2001 | \r | |
2002 | **/\r | |
2003 | UINTN\r | |
2004 | EFIAPI\r | |
2005 | AsmWriteDr1 (\r | |
2006 | UINTN Dr1\r | |
2007 | )\r | |
2008 | {\r | |
2009 | return gUnitTestHostBaseLib.X86->AsmWriteDr1 (Dr1);\r | |
2010 | }\r | |
2011 | \r | |
2012 | /**\r | |
2013 | Writes a value to Debug Register 2 (DR2).\r | |
2014 | \r | |
2015 | Writes and returns a new value to DR2. This function is only available on\r | |
2016 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
2017 | \r | |
2018 | @param Dr2 The value to write to Dr2.\r | |
2019 | \r | |
2020 | @return The value written to Debug Register 2 (DR2).\r | |
2021 | \r | |
2022 | **/\r | |
2023 | UINTN\r | |
2024 | EFIAPI\r | |
2025 | AsmWriteDr2 (\r | |
2026 | UINTN Dr2\r | |
2027 | )\r | |
2028 | {\r | |
2029 | return gUnitTestHostBaseLib.X86->AsmWriteDr2 (Dr2);\r | |
2030 | }\r | |
2031 | \r | |
2032 | /**\r | |
2033 | Writes a value to Debug Register 3 (DR3).\r | |
2034 | \r | |
2035 | Writes and returns a new value to DR3. This function is only available on\r | |
2036 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
2037 | \r | |
2038 | @param Dr3 The value to write to Dr3.\r | |
2039 | \r | |
2040 | @return The value written to Debug Register 3 (DR3).\r | |
2041 | \r | |
2042 | **/\r | |
2043 | UINTN\r | |
2044 | EFIAPI\r | |
2045 | AsmWriteDr3 (\r | |
2046 | UINTN Dr3\r | |
2047 | )\r | |
2048 | {\r | |
2049 | return gUnitTestHostBaseLib.X86->AsmWriteDr3 (Dr3);\r | |
2050 | }\r | |
2051 | \r | |
2052 | /**\r | |
2053 | Writes a value to Debug Register 4 (DR4).\r | |
2054 | \r | |
2055 | Writes and returns a new value to DR4. This function is only available on\r | |
2056 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
2057 | \r | |
2058 | @param Dr4 The value to write to Dr4.\r | |
2059 | \r | |
2060 | @return The value written to Debug Register 4 (DR4).\r | |
2061 | \r | |
2062 | **/\r | |
2063 | UINTN\r | |
2064 | EFIAPI\r | |
2065 | AsmWriteDr4 (\r | |
2066 | UINTN Dr4\r | |
2067 | )\r | |
2068 | {\r | |
2069 | return gUnitTestHostBaseLib.X86->AsmWriteDr4 (Dr4);\r | |
2070 | }\r | |
2071 | \r | |
2072 | /**\r | |
2073 | Writes a value to Debug Register 5 (DR5).\r | |
2074 | \r | |
2075 | Writes and returns a new value to DR5. This function is only available on\r | |
2076 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
2077 | \r | |
2078 | @param Dr5 The value to write to Dr5.\r | |
2079 | \r | |
2080 | @return The value written to Debug Register 5 (DR5).\r | |
2081 | \r | |
2082 | **/\r | |
2083 | UINTN\r | |
2084 | EFIAPI\r | |
2085 | AsmWriteDr5 (\r | |
2086 | UINTN Dr5\r | |
2087 | )\r | |
2088 | {\r | |
2089 | return gUnitTestHostBaseLib.X86->AsmWriteDr5 (Dr5);\r | |
2090 | }\r | |
2091 | \r | |
2092 | /**\r | |
2093 | Writes a value to Debug Register 6 (DR6).\r | |
2094 | \r | |
2095 | Writes and returns a new value to DR6. This function is only available on\r | |
2096 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
2097 | \r | |
2098 | @param Dr6 The value to write to Dr6.\r | |
2099 | \r | |
2100 | @return The value written to Debug Register 6 (DR6).\r | |
2101 | \r | |
2102 | **/\r | |
2103 | UINTN\r | |
2104 | EFIAPI\r | |
2105 | AsmWriteDr6 (\r | |
2106 | UINTN Dr6\r | |
2107 | )\r | |
2108 | {\r | |
2109 | return gUnitTestHostBaseLib.X86->AsmWriteDr6 (Dr6);\r | |
2110 | }\r | |
2111 | \r | |
2112 | /**\r | |
2113 | Writes a value to Debug Register 7 (DR7).\r | |
2114 | \r | |
2115 | Writes and returns a new value to DR7. This function is only available on\r | |
2116 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
2117 | \r | |
2118 | @param Dr7 The value to write to Dr7.\r | |
2119 | \r | |
2120 | @return The value written to Debug Register 7 (DR7).\r | |
2121 | \r | |
2122 | **/\r | |
2123 | UINTN\r | |
2124 | EFIAPI\r | |
2125 | AsmWriteDr7 (\r | |
2126 | UINTN Dr7\r | |
2127 | )\r | |
2128 | {\r | |
2129 | return gUnitTestHostBaseLib.X86->AsmWriteDr7 (Dr7);\r | |
2130 | }\r | |
2131 | \r | |
2132 | /**\r | |
2133 | Reads the current value of Code Segment Register (CS).\r | |
2134 | \r | |
2135 | Reads and returns the current value of CS. This function is only available on\r | |
2136 | IA-32 and x64.\r | |
2137 | \r | |
2138 | @return The current value of CS.\r | |
2139 | \r | |
2140 | **/\r | |
2141 | UINT16\r | |
2142 | EFIAPI\r | |
2143 | AsmReadCs (\r | |
2144 | VOID\r | |
2145 | )\r | |
2146 | {\r | |
2147 | return gUnitTestHostBaseLib.X86->AsmReadCs ();\r | |
2148 | }\r | |
2149 | \r | |
2150 | /**\r | |
2151 | Reads the current value of Data Segment Register (DS).\r | |
2152 | \r | |
2153 | Reads and returns the current value of DS. This function is only available on\r | |
2154 | IA-32 and x64.\r | |
2155 | \r | |
2156 | @return The current value of DS.\r | |
2157 | \r | |
2158 | **/\r | |
2159 | UINT16\r | |
2160 | EFIAPI\r | |
2161 | AsmReadDs (\r | |
2162 | VOID\r | |
2163 | )\r | |
2164 | {\r | |
2165 | return gUnitTestHostBaseLib.X86->AsmReadDs ();\r | |
2166 | }\r | |
2167 | \r | |
2168 | /**\r | |
2169 | Reads the current value of Extra Segment Register (ES).\r | |
2170 | \r | |
2171 | Reads and returns the current value of ES. This function is only available on\r | |
2172 | IA-32 and x64.\r | |
2173 | \r | |
2174 | @return The current value of ES.\r | |
2175 | \r | |
2176 | **/\r | |
2177 | UINT16\r | |
2178 | EFIAPI\r | |
2179 | AsmReadEs (\r | |
2180 | VOID\r | |
2181 | )\r | |
2182 | {\r | |
2183 | return gUnitTestHostBaseLib.X86->AsmReadEs ();\r | |
2184 | }\r | |
2185 | \r | |
2186 | /**\r | |
2187 | Reads the current value of FS Data Segment Register (FS).\r | |
2188 | \r | |
2189 | Reads and returns the current value of FS. This function is only available on\r | |
2190 | IA-32 and x64.\r | |
2191 | \r | |
2192 | @return The current value of FS.\r | |
2193 | \r | |
2194 | **/\r | |
2195 | UINT16\r | |
2196 | EFIAPI\r | |
2197 | AsmReadFs (\r | |
2198 | VOID\r | |
2199 | )\r | |
2200 | {\r | |
2201 | return gUnitTestHostBaseLib.X86->AsmReadFs ();\r | |
2202 | }\r | |
2203 | \r | |
2204 | /**\r | |
2205 | Reads the current value of GS Data Segment Register (GS).\r | |
2206 | \r | |
2207 | Reads and returns the current value of GS. This function is only available on\r | |
2208 | IA-32 and x64.\r | |
2209 | \r | |
2210 | @return The current value of GS.\r | |
2211 | \r | |
2212 | **/\r | |
2213 | UINT16\r | |
2214 | EFIAPI\r | |
2215 | AsmReadGs (\r | |
2216 | VOID\r | |
2217 | )\r | |
2218 | {\r | |
2219 | return gUnitTestHostBaseLib.X86->AsmReadGs ();\r | |
2220 | }\r | |
2221 | \r | |
2222 | /**\r | |
2223 | Reads the current value of Stack Segment Register (SS).\r | |
2224 | \r | |
2225 | Reads and returns the current value of SS. This function is only available on\r | |
2226 | IA-32 and x64.\r | |
2227 | \r | |
2228 | @return The current value of SS.\r | |
2229 | \r | |
2230 | **/\r | |
2231 | UINT16\r | |
2232 | EFIAPI\r | |
2233 | AsmReadSs (\r | |
2234 | VOID\r | |
2235 | )\r | |
2236 | {\r | |
2237 | return gUnitTestHostBaseLib.X86->AsmReadSs ();\r | |
2238 | }\r | |
2239 | \r | |
2240 | /**\r | |
2241 | Reads the current value of Task Register (TR).\r | |
2242 | \r | |
2243 | Reads and returns the current value of TR. This function is only available on\r | |
2244 | IA-32 and x64.\r | |
2245 | \r | |
2246 | @return The current value of TR.\r | |
2247 | \r | |
2248 | **/\r | |
2249 | UINT16\r | |
2250 | EFIAPI\r | |
2251 | AsmReadTr (\r | |
2252 | VOID\r | |
2253 | )\r | |
2254 | {\r | |
2255 | return gUnitTestHostBaseLib.X86->AsmReadTr ();\r | |
2256 | }\r | |
2257 | \r | |
2258 | /**\r | |
2259 | Reads the current Global Descriptor Table Register(GDTR) descriptor.\r | |
2260 | \r | |
2261 | Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r | |
2262 | function is only available on IA-32 and x64.\r | |
2263 | \r | |
2264 | If Gdtr is NULL, then ASSERT().\r | |
2265 | \r | |
2266 | @param Gdtr The pointer to a GDTR descriptor.\r | |
2267 | \r | |
2268 | **/\r | |
2269 | VOID\r | |
2270 | EFIAPI\r | |
2271 | AsmReadGdtr (\r | |
2f88bd3a | 2272 | OUT IA32_DESCRIPTOR *Gdtr\r |
540fd45f MK |
2273 | )\r |
2274 | {\r | |
2275 | gUnitTestHostBaseLib.X86->AsmReadGdtr (Gdtr);\r | |
2276 | }\r | |
2277 | \r | |
2278 | /**\r | |
2279 | Writes the current Global Descriptor Table Register (GDTR) descriptor.\r | |
2280 | \r | |
2281 | Writes and the current GDTR descriptor specified by Gdtr. This function is\r | |
2282 | only available on IA-32 and x64.\r | |
2283 | \r | |
2284 | If Gdtr is NULL, then ASSERT().\r | |
2285 | \r | |
2286 | @param Gdtr The pointer to a GDTR descriptor.\r | |
2287 | \r | |
2288 | **/\r | |
2289 | VOID\r | |
2290 | EFIAPI\r | |
2291 | AsmWriteGdtr (\r | |
2f88bd3a | 2292 | IN CONST IA32_DESCRIPTOR *Gdtr\r |
540fd45f MK |
2293 | )\r |
2294 | {\r | |
2295 | gUnitTestHostBaseLib.X86->AsmWriteGdtr (Gdtr);\r | |
2296 | }\r | |
2297 | \r | |
2298 | /**\r | |
2299 | Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.\r | |
2300 | \r | |
2301 | Reads and returns the current IDTR descriptor and returns it in Idtr. This\r | |
2302 | function is only available on IA-32 and x64.\r | |
2303 | \r | |
2304 | If Idtr is NULL, then ASSERT().\r | |
2305 | \r | |
2306 | @param Idtr The pointer to a IDTR descriptor.\r | |
2307 | \r | |
2308 | **/\r | |
2309 | VOID\r | |
2310 | EFIAPI\r | |
2311 | AsmReadIdtr (\r | |
2f88bd3a | 2312 | OUT IA32_DESCRIPTOR *Idtr\r |
540fd45f MK |
2313 | )\r |
2314 | {\r | |
2315 | gUnitTestHostBaseLib.X86->AsmReadIdtr (Idtr);\r | |
2316 | }\r | |
2317 | \r | |
2318 | /**\r | |
2319 | Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.\r | |
2320 | \r | |
2321 | Writes the current IDTR descriptor and returns it in Idtr. This function is\r | |
2322 | only available on IA-32 and x64.\r | |
2323 | \r | |
2324 | If Idtr is NULL, then ASSERT().\r | |
2325 | \r | |
2326 | @param Idtr The pointer to a IDTR descriptor.\r | |
2327 | \r | |
2328 | **/\r | |
2329 | VOID\r | |
2330 | EFIAPI\r | |
2331 | AsmWriteIdtr (\r | |
2f88bd3a | 2332 | IN CONST IA32_DESCRIPTOR *Idtr\r |
540fd45f MK |
2333 | )\r |
2334 | {\r | |
2335 | gUnitTestHostBaseLib.X86->AsmWriteIdtr (Idtr);\r | |
2336 | }\r | |
2337 | \r | |
2338 | /**\r | |
2339 | Reads the current Local Descriptor Table Register(LDTR) selector.\r | |
2340 | \r | |
2341 | Reads and returns the current 16-bit LDTR descriptor value. This function is\r | |
2342 | only available on IA-32 and x64.\r | |
2343 | \r | |
2344 | @return The current selector of LDT.\r | |
2345 | \r | |
2346 | **/\r | |
2347 | UINT16\r | |
2348 | EFIAPI\r | |
2349 | AsmReadLdtr (\r | |
2350 | VOID\r | |
2351 | )\r | |
2352 | {\r | |
2353 | return gUnitTestHostBaseLib.X86->AsmReadLdtr ();\r | |
2354 | }\r | |
2355 | \r | |
2356 | /**\r | |
2357 | Writes the current Local Descriptor Table Register (LDTR) selector.\r | |
2358 | \r | |
2359 | Writes and the current LDTR descriptor specified by Ldtr. This function is\r | |
2360 | only available on IA-32 and x64.\r | |
2361 | \r | |
2362 | @param Ldtr 16-bit LDTR selector value.\r | |
2363 | \r | |
2364 | **/\r | |
2365 | VOID\r | |
2366 | EFIAPI\r | |
2367 | AsmWriteLdtr (\r | |
2f88bd3a | 2368 | IN UINT16 Ldtr\r |
540fd45f MK |
2369 | )\r |
2370 | {\r | |
2371 | gUnitTestHostBaseLib.X86->AsmWriteLdtr (Ldtr);\r | |
2372 | }\r | |
2373 | \r | |
2374 | /**\r | |
2375 | Reads the current value of a Performance Counter (PMC).\r | |
2376 | \r | |
2377 | Reads and returns the current value of performance counter specified by\r | |
2378 | Index. This function is only available on IA-32 and x64.\r | |
2379 | \r | |
2380 | @param Index The 32-bit Performance Counter index to read.\r | |
2381 | \r | |
2382 | @return The value of the PMC specified by Index.\r | |
2383 | \r | |
2384 | **/\r | |
2385 | UINT64\r | |
2386 | EFIAPI\r | |
2387 | AsmReadPmc (\r | |
2f88bd3a | 2388 | IN UINT32 Index\r |
540fd45f MK |
2389 | )\r |
2390 | {\r | |
2391 | return gUnitTestHostBaseLib.X86->AsmReadPmc (Index);\r | |
2392 | }\r | |
2393 | \r | |
2394 | /**\r | |
2395 | Sets up a monitor buffer that is used by AsmMwait().\r | |
2396 | \r | |
2397 | Executes a MONITOR instruction with the register state specified by Eax, Ecx\r | |
2398 | and Edx. Returns Eax. This function is only available on IA-32 and x64.\r | |
2399 | \r | |
2400 | @param Eax The value to load into EAX or RAX before executing the MONITOR\r | |
2401 | instruction.\r | |
2402 | @param Ecx The value to load into ECX or RCX before executing the MONITOR\r | |
2403 | instruction.\r | |
2404 | @param Edx The value to load into EDX or RDX before executing the MONITOR\r | |
2405 | instruction.\r | |
2406 | \r | |
2407 | @return Eax\r | |
2408 | \r | |
2409 | **/\r | |
2410 | UINTN\r | |
2411 | EFIAPI\r | |
2412 | AsmMonitor (\r | |
2f88bd3a MK |
2413 | IN UINTN Eax,\r |
2414 | IN UINTN Ecx,\r | |
2415 | IN UINTN Edx\r | |
540fd45f MK |
2416 | )\r |
2417 | {\r | |
2418 | return gUnitTestHostBaseLib.X86->AsmMonitor (Eax, Ecx, Edx);\r | |
2419 | }\r | |
2420 | \r | |
2421 | /**\r | |
2422 | Executes an MWAIT instruction.\r | |
2423 | \r | |
2424 | Executes an MWAIT instruction with the register state specified by Eax and\r | |
2425 | Ecx. Returns Eax. This function is only available on IA-32 and x64.\r | |
2426 | \r | |
2427 | @param Eax The value to load into EAX or RAX before executing the MONITOR\r | |
2428 | instruction.\r | |
2429 | @param Ecx The value to load into ECX or RCX before executing the MONITOR\r | |
2430 | instruction.\r | |
2431 | \r | |
2432 | @return Eax\r | |
2433 | \r | |
2434 | **/\r | |
2435 | UINTN\r | |
2436 | EFIAPI\r | |
2437 | AsmMwait (\r | |
2f88bd3a MK |
2438 | IN UINTN Eax,\r |
2439 | IN UINTN Ecx\r | |
540fd45f MK |
2440 | )\r |
2441 | {\r | |
2442 | return gUnitTestHostBaseLib.X86->AsmMwait (Eax, Ecx);\r | |
2443 | }\r | |
2444 | \r | |
2445 | /**\r | |
2446 | Executes a WBINVD instruction.\r | |
2447 | \r | |
2448 | Executes a WBINVD instruction. This function is only available on IA-32 and\r | |
2449 | x64.\r | |
2450 | \r | |
2451 | **/\r | |
2452 | VOID\r | |
2453 | EFIAPI\r | |
2454 | AsmWbinvd (\r | |
2455 | VOID\r | |
2456 | )\r | |
2457 | {\r | |
2458 | gUnitTestHostBaseLib.X86->AsmWbinvd ();\r | |
2459 | }\r | |
2460 | \r | |
2461 | /**\r | |
2462 | Executes a INVD instruction.\r | |
2463 | \r | |
2464 | Executes a INVD instruction. This function is only available on IA-32 and\r | |
2465 | x64.\r | |
2466 | \r | |
2467 | **/\r | |
2468 | VOID\r | |
2469 | EFIAPI\r | |
2470 | AsmInvd (\r | |
2471 | VOID\r | |
2472 | )\r | |
2473 | {\r | |
2474 | gUnitTestHostBaseLib.X86->AsmInvd ();\r | |
2475 | }\r | |
2476 | \r | |
2477 | /**\r | |
2478 | Flushes a cache line from all the instruction and data caches within the\r | |
2479 | coherency domain of the CPU.\r | |
2480 | \r | |
2481 | Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r | |
2482 | This function is only available on IA-32 and x64.\r | |
2483 | \r | |
2484 | @param LinearAddress The address of the cache line to flush. If the CPU is\r | |
2485 | in a physical addressing mode, then LinearAddress is a\r | |
2486 | physical address. If the CPU is in a virtual\r | |
2487 | addressing mode, then LinearAddress is a virtual\r | |
2488 | address.\r | |
2489 | \r | |
2490 | @return LinearAddress.\r | |
2491 | **/\r | |
2492 | VOID *\r | |
2493 | EFIAPI\r | |
2494 | AsmFlushCacheLine (\r | |
2f88bd3a | 2495 | IN VOID *LinearAddress\r |
540fd45f MK |
2496 | )\r |
2497 | {\r | |
2498 | return gUnitTestHostBaseLib.X86->AsmFlushCacheLine (LinearAddress);\r | |
2499 | }\r | |
2500 | \r | |
2501 | /**\r | |
2502 | Enables the 32-bit paging mode on the CPU.\r | |
2503 | \r | |
2504 | Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r | |
2505 | must be properly initialized prior to calling this service. This function\r | |
2506 | assumes the current execution mode is 32-bit protected mode. This function is\r | |
2507 | only available on IA-32. After the 32-bit paging mode is enabled, control is\r | |
2508 | transferred to the function specified by EntryPoint using the new stack\r | |
2509 | specified by NewStack and passing in the parameters specified by Context1 and\r | |
2510 | Context2. Context1 and Context2 are optional and may be NULL. The function\r | |
2511 | EntryPoint must never return.\r | |
2512 | \r | |
2513 | If the current execution mode is not 32-bit protected mode, then ASSERT().\r | |
2514 | If EntryPoint is NULL, then ASSERT().\r | |
2515 | If NewStack is NULL, then ASSERT().\r | |
2516 | \r | |
2517 | There are a number of constraints that must be followed before calling this\r | |
2518 | function:\r | |
2519 | 1) Interrupts must be disabled.\r | |
2520 | 2) The caller must be in 32-bit protected mode with flat descriptors. This\r | |
2521 | means all descriptors must have a base of 0 and a limit of 4GB.\r | |
2522 | 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat\r | |
2523 | descriptors.\r | |
2524 | 4) CR3 must point to valid page tables that will be used once the transition\r | |
2525 | is complete, and those page tables must guarantee that the pages for this\r | |
2526 | function and the stack are identity mapped.\r | |
2527 | \r | |
2528 | @param EntryPoint A pointer to function to call with the new stack after\r | |
2529 | paging is enabled.\r | |
2530 | @param Context1 A pointer to the context to pass into the EntryPoint\r | |
2531 | function as the first parameter after paging is enabled.\r | |
2532 | @param Context2 A pointer to the context to pass into the EntryPoint\r | |
2533 | function as the second parameter after paging is enabled.\r | |
2534 | @param NewStack A pointer to the new stack to use for the EntryPoint\r | |
2535 | function after paging is enabled.\r | |
2536 | \r | |
2537 | **/\r | |
2538 | VOID\r | |
2539 | EFIAPI\r | |
2540 | AsmEnablePaging32 (\r | |
2541 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r | |
d0e2f823 MK |
2542 | IN VOID *Context1 OPTIONAL,\r |
2543 | IN VOID *Context2 OPTIONAL,\r | |
540fd45f MK |
2544 | IN VOID *NewStack\r |
2545 | )\r | |
2546 | {\r | |
2547 | gUnitTestHostBaseLib.X86->AsmEnablePaging32 (EntryPoint, Context1, Context2, NewStack);\r | |
2548 | }\r | |
2549 | \r | |
2550 | /**\r | |
2551 | Disables the 32-bit paging mode on the CPU.\r | |
2552 | \r | |
2553 | Disables the 32-bit paging mode on the CPU and returns to 32-bit protected\r | |
2554 | mode. This function assumes the current execution mode is 32-paged protected\r | |
2555 | mode. This function is only available on IA-32. After the 32-bit paging mode\r | |
2556 | is disabled, control is transferred to the function specified by EntryPoint\r | |
2557 | using the new stack specified by NewStack and passing in the parameters\r | |
2558 | specified by Context1 and Context2. Context1 and Context2 are optional and\r | |
2559 | may be NULL. The function EntryPoint must never return.\r | |
2560 | \r | |
2561 | If the current execution mode is not 32-bit paged mode, then ASSERT().\r | |
2562 | If EntryPoint is NULL, then ASSERT().\r | |
2563 | If NewStack is NULL, then ASSERT().\r | |
2564 | \r | |
2565 | There are a number of constraints that must be followed before calling this\r | |
2566 | function:\r | |
2567 | 1) Interrupts must be disabled.\r | |
2568 | 2) The caller must be in 32-bit paged mode.\r | |
2569 | 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.\r | |
2570 | 4) CR3 must point to valid page tables that guarantee that the pages for\r | |
2571 | this function and the stack are identity mapped.\r | |
2572 | \r | |
2573 | @param EntryPoint A pointer to function to call with the new stack after\r | |
2574 | paging is disabled.\r | |
2575 | @param Context1 A pointer to the context to pass into the EntryPoint\r | |
2576 | function as the first parameter after paging is disabled.\r | |
2577 | @param Context2 A pointer to the context to pass into the EntryPoint\r | |
2578 | function as the second parameter after paging is\r | |
2579 | disabled.\r | |
2580 | @param NewStack A pointer to the new stack to use for the EntryPoint\r | |
2581 | function after paging is disabled.\r | |
2582 | \r | |
2583 | **/\r | |
2584 | VOID\r | |
2585 | EFIAPI\r | |
2586 | AsmDisablePaging32 (\r | |
2587 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r | |
d0e2f823 MK |
2588 | IN VOID *Context1 OPTIONAL,\r |
2589 | IN VOID *Context2 OPTIONAL,\r | |
540fd45f MK |
2590 | IN VOID *NewStack\r |
2591 | )\r | |
2592 | {\r | |
2593 | gUnitTestHostBaseLib.X86->AsmDisablePaging32 (EntryPoint, Context1, Context2, NewStack);\r | |
2594 | }\r | |
2595 | \r | |
2596 | /**\r | |
2597 | Enables the 64-bit paging mode on the CPU.\r | |
2598 | \r | |
2599 | Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r | |
2600 | must be properly initialized prior to calling this service. This function\r | |
2601 | assumes the current execution mode is 32-bit protected mode with flat\r | |
2602 | descriptors. This function is only available on IA-32. After the 64-bit\r | |
2603 | paging mode is enabled, control is transferred to the function specified by\r | |
2604 | EntryPoint using the new stack specified by NewStack and passing in the\r | |
2605 | parameters specified by Context1 and Context2. Context1 and Context2 are\r | |
2606 | optional and may be 0. The function EntryPoint must never return.\r | |
2607 | \r | |
2608 | If the current execution mode is not 32-bit protected mode with flat\r | |
2609 | descriptors, then ASSERT().\r | |
2610 | If EntryPoint is 0, then ASSERT().\r | |
2611 | If NewStack is 0, then ASSERT().\r | |
2612 | \r | |
2613 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r | |
2614 | is called. The descriptor in the GDT that this selector\r | |
2615 | references must be setup for long mode.\r | |
2616 | @param EntryPoint The 64-bit virtual address of the function to call with\r | |
2617 | the new stack after paging is enabled.\r | |
2618 | @param Context1 The 64-bit virtual address of the context to pass into\r | |
2619 | the EntryPoint function as the first parameter after\r | |
2620 | paging is enabled.\r | |
2621 | @param Context2 The 64-bit virtual address of the context to pass into\r | |
2622 | the EntryPoint function as the second parameter after\r | |
2623 | paging is enabled.\r | |
2624 | @param NewStack The 64-bit virtual address of the new stack to use for\r | |
2625 | the EntryPoint function after paging is enabled.\r | |
2626 | \r | |
2627 | **/\r | |
2628 | VOID\r | |
2629 | EFIAPI\r | |
2630 | AsmEnablePaging64 (\r | |
2f88bd3a MK |
2631 | IN UINT16 Cs,\r |
2632 | IN UINT64 EntryPoint,\r | |
2633 | IN UINT64 Context1 OPTIONAL,\r | |
2634 | IN UINT64 Context2 OPTIONAL,\r | |
2635 | IN UINT64 NewStack\r | |
540fd45f MK |
2636 | )\r |
2637 | {\r | |
2638 | gUnitTestHostBaseLib.X86->AsmEnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r | |
2639 | }\r | |
2640 | \r | |
2641 | /**\r | |
2642 | Disables the 64-bit paging mode on the CPU.\r | |
2643 | \r | |
2644 | Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r | |
2645 | mode. This function assumes the current execution mode is 64-paging mode.\r | |
2646 | This function is only available on x64. After the 64-bit paging mode is\r | |
2647 | disabled, control is transferred to the function specified by EntryPoint\r | |
2648 | using the new stack specified by NewStack and passing in the parameters\r | |
2649 | specified by Context1 and Context2. Context1 and Context2 are optional and\r | |
2650 | may be 0. The function EntryPoint must never return.\r | |
2651 | \r | |
2652 | If the current execution mode is not 64-bit paged mode, then ASSERT().\r | |
2653 | If EntryPoint is 0, then ASSERT().\r | |
2654 | If NewStack is 0, then ASSERT().\r | |
2655 | \r | |
2656 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r | |
2657 | is called. The descriptor in the GDT that this selector\r | |
2658 | references must be setup for 32-bit protected mode.\r | |
2659 | @param EntryPoint The 64-bit virtual address of the function to call with\r | |
2660 | the new stack after paging is disabled.\r | |
2661 | @param Context1 The 64-bit virtual address of the context to pass into\r | |
2662 | the EntryPoint function as the first parameter after\r | |
2663 | paging is disabled.\r | |
2664 | @param Context2 The 64-bit virtual address of the context to pass into\r | |
2665 | the EntryPoint function as the second parameter after\r | |
2666 | paging is disabled.\r | |
2667 | @param NewStack The 64-bit virtual address of the new stack to use for\r | |
2668 | the EntryPoint function after paging is disabled.\r | |
2669 | \r | |
2670 | **/\r | |
2671 | VOID\r | |
2672 | EFIAPI\r | |
2673 | AsmDisablePaging64 (\r | |
2f88bd3a MK |
2674 | IN UINT16 Cs,\r |
2675 | IN UINT32 EntryPoint,\r | |
2676 | IN UINT32 Context1 OPTIONAL,\r | |
2677 | IN UINT32 Context2 OPTIONAL,\r | |
2678 | IN UINT32 NewStack\r | |
540fd45f MK |
2679 | )\r |
2680 | {\r | |
2681 | gUnitTestHostBaseLib.X86->AsmDisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r | |
2682 | }\r | |
2683 | \r | |
2684 | /**\r | |
2685 | Retrieves the properties for 16-bit thunk functions.\r | |
2686 | \r | |
2687 | Computes the size of the buffer and stack below 1MB required to use the\r | |
2688 | AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This\r | |
2689 | buffer size is returned in RealModeBufferSize, and the stack size is returned\r | |
2690 | in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r | |
2691 | then the actual minimum stack size is ExtraStackSize plus the maximum number\r | |
2692 | of bytes that need to be passed to the 16-bit real mode code.\r | |
2693 | \r | |
2694 | If RealModeBufferSize is NULL, then ASSERT().\r | |
2695 | If ExtraStackSize is NULL, then ASSERT().\r | |
2696 | \r | |
2697 | @param RealModeBufferSize A pointer to the size of the buffer below 1MB\r | |
2698 | required to use the 16-bit thunk functions.\r | |
2699 | @param ExtraStackSize A pointer to the extra size of stack below 1MB\r | |
2700 | that the 16-bit thunk functions require for\r | |
2701 | temporary storage in the transition to and from\r | |
2702 | 16-bit real mode.\r | |
2703 | \r | |
2704 | **/\r | |
2705 | VOID\r | |
2706 | EFIAPI\r | |
2707 | AsmGetThunk16Properties (\r | |
2f88bd3a MK |
2708 | OUT UINT32 *RealModeBufferSize,\r |
2709 | OUT UINT32 *ExtraStackSize\r | |
540fd45f MK |
2710 | )\r |
2711 | {\r | |
2712 | gUnitTestHostBaseLib.X86->AsmGetThunk16Properties (RealModeBufferSize, ExtraStackSize);\r | |
2713 | }\r | |
2714 | \r | |
2715 | /**\r | |
2716 | Prepares all structures a code required to use AsmThunk16().\r | |
2717 | \r | |
2718 | Prepares all structures and code required to use AsmThunk16().\r | |
2719 | \r | |
2720 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
2721 | virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r | |
2722 | \r | |
2723 | If ThunkContext is NULL, then ASSERT().\r | |
2724 | \r | |
2725 | @param ThunkContext A pointer to the context structure that describes the\r | |
2726 | 16-bit real mode code to call.\r | |
2727 | \r | |
2728 | **/\r | |
2729 | VOID\r | |
2730 | EFIAPI\r | |
2731 | AsmPrepareThunk16 (\r | |
2f88bd3a | 2732 | IN OUT THUNK_CONTEXT *ThunkContext\r |
540fd45f MK |
2733 | )\r |
2734 | {\r | |
2735 | gUnitTestHostBaseLib.X86->AsmPrepareThunk16 (ThunkContext);\r | |
2736 | }\r | |
2737 | \r | |
2738 | /**\r | |
2739 | Transfers control to a 16-bit real mode entry point and returns the results.\r | |
2740 | \r | |
2741 | Transfers control to a 16-bit real mode entry point and returns the results.\r | |
2742 | AsmPrepareThunk16() must be called with ThunkContext before this function is used.\r | |
2743 | This function must be called with interrupts disabled.\r | |
2744 | \r | |
2745 | The register state from the RealModeState field of ThunkContext is restored just prior\r | |
2746 | to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,\r | |
2747 | which is used to set the interrupt state when a 16-bit real mode entry point is called.\r | |
2748 | Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.\r | |
2749 | The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to\r | |
2750 | the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.\r | |
2751 | The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,\r | |
2752 | so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment\r | |
2753 | and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry\r | |
2754 | point must exit with a RETF instruction. The register state is captured into RealModeState immediately\r | |
2755 | after the RETF instruction is executed.\r | |
2756 | \r | |
2757 | If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r | |
2758 | or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure\r | |
2759 | the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.\r | |
2760 | \r | |
2761 | If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r | |
2762 | then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.\r | |
2763 | This includes the base vectors, the interrupt masks, and the edge/level trigger mode.\r | |
2764 | \r | |
2765 | If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code\r | |
2766 | is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.\r | |
2767 | \r | |
2768 | If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r | |
2769 | ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to\r | |
2770 | disable the A20 mask.\r | |
2771 | \r | |
2772 | If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in\r | |
2773 | ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,\r | |
2774 | then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r | |
2775 | \r | |
2776 | If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in\r | |
2777 | ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r | |
2778 | \r | |
2779 | If ThunkContext is NULL, then ASSERT().\r | |
2780 | If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().\r | |
2781 | If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r | |
2782 | ThunkAttributes, then ASSERT().\r | |
2783 | \r | |
2784 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
2785 | virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.\r | |
2786 | \r | |
2787 | @param ThunkContext A pointer to the context structure that describes the\r | |
2788 | 16-bit real mode code to call.\r | |
2789 | \r | |
2790 | **/\r | |
2791 | VOID\r | |
2792 | EFIAPI\r | |
2793 | AsmThunk16 (\r | |
2f88bd3a | 2794 | IN OUT THUNK_CONTEXT *ThunkContext\r |
540fd45f MK |
2795 | )\r |
2796 | {\r | |
2797 | gUnitTestHostBaseLib.X86->AsmThunk16 (ThunkContext);\r | |
2798 | }\r | |
2799 | \r | |
2800 | /**\r | |
2801 | Prepares all structures and code for a 16-bit real mode thunk, transfers\r | |
2802 | control to a 16-bit real mode entry point, and returns the results.\r | |
2803 | \r | |
2804 | Prepares all structures and code for a 16-bit real mode thunk, transfers\r | |
2805 | control to a 16-bit real mode entry point, and returns the results. If the\r | |
2806 | caller only need to perform a single 16-bit real mode thunk, then this\r | |
2807 | service should be used. If the caller intends to make more than one 16-bit\r | |
2808 | real mode thunk, then it is more efficient if AsmPrepareThunk16() is called\r | |
2809 | once and AsmThunk16() can be called for each 16-bit real mode thunk.\r | |
2810 | \r | |
2811 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
2812 | virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r | |
2813 | \r | |
2814 | See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.\r | |
2815 | \r | |
2816 | @param ThunkContext A pointer to the context structure that describes the\r | |
2817 | 16-bit real mode code to call.\r | |
2818 | \r | |
2819 | **/\r | |
2820 | VOID\r | |
2821 | EFIAPI\r | |
2822 | AsmPrepareAndThunk16 (\r | |
2f88bd3a | 2823 | IN OUT THUNK_CONTEXT *ThunkContext\r |
540fd45f MK |
2824 | )\r |
2825 | {\r | |
2826 | gUnitTestHostBaseLib.X86->AsmPrepareAndThunk16 (ThunkContext);\r | |
2827 | }\r | |
2828 | \r | |
2829 | /**\r | |
2830 | Load given selector into TR register.\r | |
2831 | \r | |
2832 | @param[in] Selector Task segment selector\r | |
2833 | **/\r | |
2834 | VOID\r | |
2835 | EFIAPI\r | |
2836 | AsmWriteTr (\r | |
2f88bd3a | 2837 | IN UINT16 Selector\r |
540fd45f MK |
2838 | )\r |
2839 | {\r | |
2840 | gUnitTestHostBaseLib.X86->AsmWriteTr (Selector);\r | |
2841 | }\r | |
2842 | \r | |
2843 | /**\r | |
2844 | Performs a serializing operation on all load-from-memory instructions that\r | |
2845 | were issued prior the AsmLfence function.\r | |
2846 | \r | |
2847 | Executes a LFENCE instruction. This function is only available on IA-32 and x64.\r | |
2848 | \r | |
2849 | **/\r | |
2850 | VOID\r | |
2851 | EFIAPI\r | |
2852 | AsmLfence (\r | |
2853 | VOID\r | |
2854 | )\r | |
2855 | {\r | |
2856 | gUnitTestHostBaseLib.X86->AsmLfence ();\r | |
2857 | }\r | |
2858 | \r | |
2859 | /**\r | |
2860 | Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r | |
2861 | word, dword or qword operand is encoded at the end of the instruction's\r | |
2862 | binary representation.\r | |
2863 | \r | |
2864 | This function should be used to update object code that was compiled with\r | |
2865 | NASM from assembly source code. Example:\r | |
2866 | \r | |
2867 | NASM source code:\r | |
2868 | \r | |
2869 | mov eax, strict dword 0 ; the imm32 zero operand will be patched\r | |
2870 | ASM_PFX(gPatchCr3):\r | |
2871 | mov cr3, eax\r | |
2872 | \r | |
2873 | C source code:\r | |
2874 | \r | |
2875 | X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r | |
2876 | PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r | |
2877 | \r | |
2878 | @param[out] InstructionEnd Pointer right past the instruction to patch. The\r | |
2879 | immediate operand to patch is expected to\r | |
2880 | comprise the trailing bytes of the instruction.\r | |
2881 | If InstructionEnd is closer to address 0 than\r | |
2882 | ValueSize permits, then ASSERT().\r | |
2883 | \r | |
2884 | @param[in] PatchValue The constant to write to the immediate operand.\r | |
2885 | The caller is responsible for ensuring that\r | |
2886 | PatchValue can be represented in the byte, word,\r | |
2887 | dword or qword operand (as indicated through\r | |
2888 | ValueSize); otherwise ASSERT().\r | |
2889 | \r | |
2890 | @param[in] ValueSize The size of the operand in bytes; must be 1, 2,\r | |
2891 | 4, or 8. ASSERT() otherwise.\r | |
2892 | **/\r | |
2893 | VOID\r | |
2894 | EFIAPI\r | |
2895 | PatchInstructionX86 (\r | |
2f88bd3a MK |
2896 | OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r |
2897 | IN UINT64 PatchValue,\r | |
2898 | IN UINTN ValueSize\r | |
540fd45f MK |
2899 | )\r |
2900 | {\r | |
2901 | gUnitTestHostBaseLib.X86->PatchInstructionX86 (InstructionEnd, PatchValue, ValueSize);\r | |
2902 | }\r | |
2903 | \r | |
2904 | ///\r | |
2905 | /// Common services\r | |
2906 | ///\r | |
2907 | STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon = {\r | |
2908 | UnitTestHostBaseLibEnableInterrupts,\r | |
2909 | UnitTestHostBaseLibDisableInterrupts,\r | |
2910 | UnitTestHostBaseLibEnableDisableInterrupts,\r | |
2911 | UnitTestHostBaseLibGetInterruptState,\r | |
2912 | };\r | |
2913 | \r | |
2914 | ///\r | |
2915 | /// IA32/X64 services\r | |
2916 | ///\r | |
2917 | STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86 = {\r | |
2918 | UnitTestHostBaseLibAsmCpuid,\r | |
2919 | UnitTestHostBaseLibAsmCpuidEx,\r | |
2920 | UnitTestHostBaseLibAsmDisableCache,\r | |
2921 | UnitTestHostBaseLibAsmEnableCache,\r | |
2922 | UnitTestHostBaseLibAsmReadMsr64,\r | |
2923 | UnitTestHostBaseLibAsmWriteMsr64,\r | |
2924 | UnitTestHostBaseLibAsmReadCr0,\r | |
2925 | UnitTestHostBaseLibAsmReadCr2,\r | |
2926 | UnitTestHostBaseLibAsmReadCr3,\r | |
2927 | UnitTestHostBaseLibAsmReadCr4,\r | |
2928 | UnitTestHostBaseLibAsmWriteCr0,\r | |
2929 | UnitTestHostBaseLibAsmWriteCr2,\r | |
2930 | UnitTestHostBaseLibAsmWriteCr3,\r | |
2931 | UnitTestHostBaseLibAsmWriteCr4,\r | |
2932 | UnitTestHostBaseLibAsmReadDr0,\r | |
2933 | UnitTestHostBaseLibAsmReadDr1,\r | |
2934 | UnitTestHostBaseLibAsmReadDr2,\r | |
2935 | UnitTestHostBaseLibAsmReadDr3,\r | |
2936 | UnitTestHostBaseLibAsmReadDr4,\r | |
2937 | UnitTestHostBaseLibAsmReadDr5,\r | |
2938 | UnitTestHostBaseLibAsmReadDr6,\r | |
2939 | UnitTestHostBaseLibAsmReadDr7,\r | |
2940 | UnitTestHostBaseLibAsmWriteDr0,\r | |
2941 | UnitTestHostBaseLibAsmWriteDr1,\r | |
2942 | UnitTestHostBaseLibAsmWriteDr2,\r | |
2943 | UnitTestHostBaseLibAsmWriteDr3,\r | |
2944 | UnitTestHostBaseLibAsmWriteDr4,\r | |
2945 | UnitTestHostBaseLibAsmWriteDr5,\r | |
2946 | UnitTestHostBaseLibAsmWriteDr6,\r | |
2947 | UnitTestHostBaseLibAsmWriteDr7,\r | |
2948 | UnitTestHostBaseLibAsmReadCs,\r | |
2949 | UnitTestHostBaseLibAsmReadDs,\r | |
2950 | UnitTestHostBaseLibAsmReadEs,\r | |
2951 | UnitTestHostBaseLibAsmReadFs,\r | |
2952 | UnitTestHostBaseLibAsmReadGs,\r | |
2953 | UnitTestHostBaseLibAsmReadSs,\r | |
2954 | UnitTestHostBaseLibAsmReadTr,\r | |
2955 | UnitTestHostBaseLibAsmReadGdtr,\r | |
2956 | UnitTestHostBaseLibAsmWriteGdtr,\r | |
2957 | UnitTestHostBaseLibAsmReadIdtr,\r | |
2958 | UnitTestHostBaseLibAsmWriteIdtr,\r | |
2959 | UnitTestHostBaseLibAsmReadLdtr,\r | |
2960 | UnitTestHostBaseLibAsmWriteLdtr,\r | |
2961 | UnitTestHostBaseLibAsmReadPmc,\r | |
2962 | UnitTestHostBaseLibAsmMonitor,\r | |
2963 | UnitTestHostBaseLibAsmMwait,\r | |
2964 | UnitTestHostBaseLibAsmWbinvd,\r | |
2965 | UnitTestHostBaseLibAsmInvd,\r | |
2966 | UnitTestHostBaseLibAsmFlushCacheLine,\r | |
2967 | UnitTestHostBaseLibAsmEnablePaging32,\r | |
2968 | UnitTestHostBaseLibAsmDisablePaging32,\r | |
2969 | UnitTestHostBaseLibAsmEnablePaging64,\r | |
2970 | UnitTestHostBaseLibAsmDisablePaging64,\r | |
2971 | UnitTestHostBaseLibAsmGetThunk16Properties,\r | |
2972 | UnitTestHostBaseLibAsmPrepareThunk16,\r | |
2973 | UnitTestHostBaseLibAsmThunk16,\r | |
2974 | UnitTestHostBaseLibAsmPrepareAndThunk16,\r | |
2975 | UnitTestHostBaseLibAsmWriteTr,\r | |
2976 | UnitTestHostBaseLibAsmLfence,\r | |
2977 | UnitTestHostBaseLibPatchInstructionX86\r | |
2978 | };\r | |
2979 | \r | |
2980 | ///\r | |
2981 | /// Structure of hook functions for BaseLib functions that can not be used from\r | |
2982 | /// a host application. A simple emulation of these function is provided by\r | |
2983 | /// default. A specific unit test can provide its own implementation for any\r | |
2984 | /// of these functions.\r | |
2985 | ///\r | |
2986 | UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib = {\r | |
2987 | &mUnitTestHostBaseLibCommon,\r | |
2988 | &mUnitTestHostBaseLibX86\r | |
2989 | };\r |