]>
Commit | Line | Data |
---|---|---|
e1f414b6 | 1 | /** @file\r |
e1f414b6 | 2 | Functions in this library instance make use of MMIO functions in IoLib to\r |
3 | access memory mapped PCI configuration space.\r | |
4 | \r | |
5 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r | |
6 | Library.\r | |
7 | \r | |
94952554 | 8 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
19388d29 | 9 | This program and the accompanying materials\r |
e1f414b6 | 10 | are licensed and made available under the terms and conditions of the BSD License\r |
11 | which accompanies this distribution. The full text of the license may be found at\r | |
2fc59a00 | 12 | http://opensource.org/licenses/bsd-license.php.\r |
e1f414b6 | 13 | \r |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | \r | |
e1f414b6 | 17 | **/\r |
18 | \r | |
c892d846 | 19 | \r |
c7d265a9 | 20 | #include <Base.h>\r |
c892d846 | 21 | \r |
0c62737d | 22 | #include <Library/BaseLib.h>\r |
c7d265a9 | 23 | #include <Library/PciExpressLib.h>\r |
24 | #include <Library/IoLib.h>\r | |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/PcdLib.h>\r | |
27 | \r | |
e1f414b6 | 28 | \r |
29 | /**\r | |
30 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
31 | only in the low 28 bits.\r | |
32 | \r | |
33 | @param A The address to validate.\r | |
34 | \r | |
35 | **/\r | |
36 | #define ASSERT_INVALID_PCI_ADDRESS(A) \\r | |
37 | ASSERT (((A) & ~0xfffffff) == 0)\r | |
38 | \r | |
3e3ae634 | 39 | /**\r |
d11195a3 | 40 | Registers a PCI device so PCI configuration registers may be accessed after \r |
3e3ae634 | 41 | SetVirtualAddressMap().\r |
42 | \r | |
d11195a3 | 43 | Registers the PCI device specified by Address so all the PCI configuration \r |
44 | registers associated with that PCI device may be accessed after SetVirtualAddressMap() \r | |
45 | is called.\r | |
46 | \r | |
3e3ae634 | 47 | If Address > 0x0FFFFFFF, then ASSERT().\r |
48 | \r | |
2fc59a00 | 49 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 50 | Register.\r |
51 | \r | |
52 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
53 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
54 | after ExitBootServices().\r | |
55 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
56 | at runtime could not be mapped.\r | |
57 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
58 | complete the registration.\r | |
59 | \r | |
60 | **/\r | |
61 | RETURN_STATUS\r | |
62 | EFIAPI\r | |
63 | PciExpressRegisterForRuntimeAccess (\r | |
64 | IN UINTN Address\r | |
65 | )\r | |
66 | {\r | |
59ceeabe | 67 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
3e3ae634 | 68 | return RETURN_UNSUPPORTED;\r |
69 | }\r | |
e1f414b6 | 70 | \r |
71 | /**\r | |
72 | Gets the base address of PCI Express.\r | |
73 | \r | |
74 | This internal functions retrieves PCI Express Base Address via a PCD entry\r | |
75 | PcdPciExpressBaseAddress.\r | |
76 | \r | |
77 | @return The base address of PCI Express.\r | |
78 | \r | |
79 | **/\r | |
94646ec0 | 80 | VOID*\r |
e1f414b6 | 81 | GetPciExpressBaseAddress (\r |
82 | VOID\r | |
83 | )\r | |
84 | {\r | |
85 | return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r | |
86 | }\r | |
87 | \r | |
88 | /**\r | |
89 | Reads an 8-bit PCI configuration register.\r | |
90 | \r | |
91 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
92 | This function must guarantee that all PCI read and write operations are\r | |
93 | serialized.\r | |
94 | \r | |
95 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
96 | \r | |
2fc59a00 | 97 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 98 | Register.\r |
99 | \r | |
100 | @return The read value from the PCI configuration register.\r | |
101 | \r | |
102 | **/\r | |
103 | UINT8\r | |
104 | EFIAPI\r | |
105 | PciExpressRead8 (\r | |
106 | IN UINTN Address\r | |
107 | )\r | |
108 | {\r | |
109 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
110 | return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
111 | }\r | |
112 | \r | |
113 | /**\r | |
114 | Writes an 8-bit PCI configuration register.\r | |
115 | \r | |
116 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
117 | value specified by Value. Value is returned. This function must guarantee\r | |
118 | that all PCI read and write operations are serialized.\r | |
119 | \r | |
120 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
121 | \r | |
2fc59a00 | 122 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 123 | Register.\r |
124 | @param Value The value to write.\r | |
125 | \r | |
126 | @return The value written to the PCI configuration register.\r | |
127 | \r | |
128 | **/\r | |
129 | UINT8\r | |
130 | EFIAPI\r | |
131 | PciExpressWrite8 (\r | |
132 | IN UINTN Address,\r | |
133 | IN UINT8 Value\r | |
134 | )\r | |
135 | {\r | |
136 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
137 | return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
138 | }\r | |
139 | \r | |
140 | /**\r | |
62991af2 | 141 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
e1f414b6 | 142 | an 8-bit value.\r |
143 | \r | |
144 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 145 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 146 | OrData, and writes the result to the 8-bit PCI configuration register\r |
147 | specified by Address. The value written to the PCI configuration register is\r | |
148 | returned. This function must guarantee that all PCI read and write operations\r | |
149 | are serialized.\r | |
150 | \r | |
151 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
152 | \r | |
2fc59a00 | 153 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 154 | Register.\r |
155 | @param OrData The value to OR with the PCI configuration register.\r | |
156 | \r | |
157 | @return The value written back to the PCI configuration register.\r | |
158 | \r | |
159 | **/\r | |
160 | UINT8\r | |
161 | EFIAPI\r | |
162 | PciExpressOr8 (\r | |
163 | IN UINTN Address,\r | |
164 | IN UINT8 OrData\r | |
165 | )\r | |
166 | {\r | |
167 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
168 | return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
169 | }\r | |
170 | \r | |
171 | /**\r | |
172 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
173 | value.\r | |
174 | \r | |
175 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
176 | bitwise AND between the read result and the value specified by AndData, and\r | |
177 | writes the result to the 8-bit PCI configuration register specified by\r | |
178 | Address. The value written to the PCI configuration register is returned.\r | |
179 | This function must guarantee that all PCI read and write operations are\r | |
180 | serialized.\r | |
181 | \r | |
182 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
183 | \r | |
2fc59a00 | 184 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 185 | Register.\r |
186 | @param AndData The value to AND with the PCI configuration register.\r | |
187 | \r | |
188 | @return The value written back to the PCI configuration register.\r | |
189 | \r | |
190 | **/\r | |
191 | UINT8\r | |
192 | EFIAPI\r | |
193 | PciExpressAnd8 (\r | |
194 | IN UINTN Address,\r | |
195 | IN UINT8 AndData\r | |
196 | )\r | |
197 | {\r | |
198 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
199 | return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
200 | }\r | |
201 | \r | |
202 | /**\r | |
203 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 204 | value, followed a bitwise OR with another 8-bit value.\r |
e1f414b6 | 205 | \r |
206 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
207 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 208 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 209 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
210 | configuration register specified by Address. The value written to the PCI\r | |
211 | configuration register is returned. This function must guarantee that all PCI\r | |
212 | read and write operations are serialized.\r | |
213 | \r | |
214 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
215 | \r | |
2fc59a00 | 216 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 217 | Register.\r |
218 | @param AndData The value to AND with the PCI configuration register.\r | |
219 | @param OrData The value to OR with the result of the AND operation.\r | |
220 | \r | |
221 | @return The value written back to the PCI configuration register.\r | |
222 | \r | |
223 | **/\r | |
224 | UINT8\r | |
225 | EFIAPI\r | |
226 | PciExpressAndThenOr8 (\r | |
227 | IN UINTN Address,\r | |
228 | IN UINT8 AndData,\r | |
229 | IN UINT8 OrData\r | |
230 | )\r | |
231 | {\r | |
232 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
233 | return MmioAndThenOr8 (\r | |
234 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
235 | AndData,\r | |
236 | OrData\r | |
237 | );\r | |
238 | }\r | |
239 | \r | |
240 | /**\r | |
241 | Reads a bit field of a PCI configuration register.\r | |
242 | \r | |
243 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
244 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
245 | returned.\r | |
246 | \r | |
247 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
248 | If StartBit is greater than 7, then ASSERT().\r | |
249 | If EndBit is greater than 7, then ASSERT().\r | |
250 | If EndBit is less than StartBit, then ASSERT().\r | |
251 | \r | |
2fc59a00 | 252 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 253 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
254 | Range 0..7.\r | |
255 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
256 | Range 0..7.\r | |
257 | \r | |
258 | @return The value of the bit field read from the PCI configuration register.\r | |
259 | \r | |
260 | **/\r | |
261 | UINT8\r | |
262 | EFIAPI\r | |
263 | PciExpressBitFieldRead8 (\r | |
264 | IN UINTN Address,\r | |
265 | IN UINTN StartBit,\r | |
266 | IN UINTN EndBit\r | |
267 | )\r | |
268 | {\r | |
269 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
270 | return MmioBitFieldRead8 (\r | |
271 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
272 | StartBit,\r | |
273 | EndBit\r | |
274 | );\r | |
275 | }\r | |
276 | \r | |
277 | /**\r | |
278 | Writes a bit field to a PCI configuration register.\r | |
279 | \r | |
280 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
281 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
282 | destination PCI configuration register are preserved. The new value of the\r | |
283 | 8-bit register is returned.\r | |
284 | \r | |
285 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
286 | If StartBit is greater than 7, then ASSERT().\r | |
287 | If EndBit is greater than 7, then ASSERT().\r | |
288 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 289 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 290 | \r |
2fc59a00 | 291 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 292 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
293 | Range 0..7.\r | |
294 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
295 | Range 0..7.\r | |
2fc59a00 | 296 | @param Value The new value of the bit field.\r |
e1f414b6 | 297 | \r |
298 | @return The value written back to the PCI configuration register.\r | |
299 | \r | |
300 | **/\r | |
301 | UINT8\r | |
302 | EFIAPI\r | |
303 | PciExpressBitFieldWrite8 (\r | |
304 | IN UINTN Address,\r | |
305 | IN UINTN StartBit,\r | |
306 | IN UINTN EndBit,\r | |
307 | IN UINT8 Value\r | |
308 | )\r | |
309 | {\r | |
310 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
311 | return MmioBitFieldWrite8 (\r | |
312 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
313 | StartBit,\r | |
314 | EndBit,\r | |
315 | Value\r | |
316 | );\r | |
317 | }\r | |
318 | \r | |
319 | /**\r | |
320 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
321 | writes the result back to the bit field in the 8-bit port.\r | |
322 | \r | |
323 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 324 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 325 | OrData, and writes the result to the 8-bit PCI configuration register\r |
326 | specified by Address. The value written to the PCI configuration register is\r | |
327 | returned. This function must guarantee that all PCI read and write operations\r | |
328 | are serialized. Extra left bits in OrData are stripped.\r | |
329 | \r | |
330 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
331 | If StartBit is greater than 7, then ASSERT().\r | |
332 | If EndBit is greater than 7, then ASSERT().\r | |
333 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 334 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 335 | \r |
2fc59a00 | 336 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 337 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
338 | Range 0..7.\r | |
339 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
340 | Range 0..7.\r | |
341 | @param OrData The value to OR with the PCI configuration register.\r | |
342 | \r | |
343 | @return The value written back to the PCI configuration register.\r | |
344 | \r | |
345 | **/\r | |
346 | UINT8\r | |
347 | EFIAPI\r | |
348 | PciExpressBitFieldOr8 (\r | |
349 | IN UINTN Address,\r | |
350 | IN UINTN StartBit,\r | |
351 | IN UINTN EndBit,\r | |
352 | IN UINT8 OrData\r | |
353 | )\r | |
354 | {\r | |
355 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
356 | return MmioBitFieldOr8 (\r | |
357 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
358 | StartBit,\r | |
359 | EndBit,\r | |
360 | OrData\r | |
361 | );\r | |
362 | }\r | |
363 | \r | |
364 | /**\r | |
365 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
366 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
367 | \r | |
368 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
369 | bitwise AND between the read result and the value specified by AndData, and\r | |
370 | writes the result to the 8-bit PCI configuration register specified by\r | |
371 | Address. The value written to the PCI configuration register is returned.\r | |
372 | This function must guarantee that all PCI read and write operations are\r | |
373 | serialized. Extra left bits in AndData are stripped.\r | |
374 | \r | |
375 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
376 | If StartBit is greater than 7, then ASSERT().\r | |
377 | If EndBit is greater than 7, then ASSERT().\r | |
378 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 379 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 380 | \r |
2fc59a00 | 381 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 382 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
383 | Range 0..7.\r | |
384 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
385 | Range 0..7.\r | |
386 | @param AndData The value to AND with the PCI configuration register.\r | |
387 | \r | |
388 | @return The value written back to the PCI configuration register.\r | |
389 | \r | |
390 | **/\r | |
391 | UINT8\r | |
392 | EFIAPI\r | |
393 | PciExpressBitFieldAnd8 (\r | |
394 | IN UINTN Address,\r | |
395 | IN UINTN StartBit,\r | |
396 | IN UINTN EndBit,\r | |
397 | IN UINT8 AndData\r | |
398 | )\r | |
399 | {\r | |
400 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
401 | return MmioBitFieldAnd8 (\r | |
402 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
403 | StartBit,\r | |
404 | EndBit,\r | |
405 | AndData\r | |
406 | );\r | |
407 | }\r | |
408 | \r | |
409 | /**\r | |
410 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 411 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 412 | 8-bit port.\r |
413 | \r | |
414 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 415 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 416 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
417 | configuration register specified by Address. The value written to the PCI\r | |
418 | configuration register is returned. This function must guarantee that all PCI\r | |
419 | read and write operations are serialized. Extra left bits in both AndData and\r | |
420 | OrData are stripped.\r | |
421 | \r | |
422 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
423 | If StartBit is greater than 7, then ASSERT().\r | |
424 | If EndBit is greater than 7, then ASSERT().\r | |
425 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
426 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
427 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 428 | \r |
2fc59a00 | 429 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 430 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
431 | Range 0..7.\r | |
432 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
433 | Range 0..7.\r | |
434 | @param AndData The value to AND with the PCI configuration register.\r | |
435 | @param OrData The value to OR with the result of the AND operation.\r | |
436 | \r | |
437 | @return The value written back to the PCI configuration register.\r | |
438 | \r | |
439 | **/\r | |
440 | UINT8\r | |
441 | EFIAPI\r | |
442 | PciExpressBitFieldAndThenOr8 (\r | |
443 | IN UINTN Address,\r | |
444 | IN UINTN StartBit,\r | |
445 | IN UINTN EndBit,\r | |
446 | IN UINT8 AndData,\r | |
447 | IN UINT8 OrData\r | |
448 | )\r | |
449 | {\r | |
450 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
451 | return MmioBitFieldAndThenOr8 (\r | |
452 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
453 | StartBit,\r | |
454 | EndBit,\r | |
455 | AndData,\r | |
456 | OrData\r | |
457 | );\r | |
458 | }\r | |
459 | \r | |
460 | /**\r | |
461 | Reads a 16-bit PCI configuration register.\r | |
462 | \r | |
463 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
464 | This function must guarantee that all PCI read and write operations are\r | |
465 | serialized.\r | |
466 | \r | |
467 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
468 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
469 | \r | |
2fc59a00 | 470 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 471 | Register.\r |
472 | \r | |
473 | @return The read value from the PCI configuration register.\r | |
474 | \r | |
475 | **/\r | |
476 | UINT16\r | |
477 | EFIAPI\r | |
478 | PciExpressRead16 (\r | |
479 | IN UINTN Address\r | |
480 | )\r | |
481 | {\r | |
482 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
483 | return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
484 | }\r | |
485 | \r | |
486 | /**\r | |
487 | Writes a 16-bit PCI configuration register.\r | |
488 | \r | |
489 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
490 | value specified by Value. Value is returned. This function must guarantee\r | |
491 | that all PCI read and write operations are serialized.\r | |
492 | \r | |
493 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
494 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
495 | \r | |
2fc59a00 | 496 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 497 | Register.\r |
498 | @param Value The value to write.\r | |
499 | \r | |
500 | @return The value written to the PCI configuration register.\r | |
501 | \r | |
502 | **/\r | |
503 | UINT16\r | |
504 | EFIAPI\r | |
505 | PciExpressWrite16 (\r | |
506 | IN UINTN Address,\r | |
507 | IN UINT16 Value\r | |
508 | )\r | |
509 | {\r | |
510 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
511 | return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
512 | }\r | |
513 | \r | |
514 | /**\r | |
62991af2 | 515 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
e1f414b6 | 516 | a 16-bit value.\r |
517 | \r | |
518 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 519 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 520 | OrData, and writes the result to the 16-bit PCI configuration register\r |
521 | specified by Address. The value written to the PCI configuration register is\r | |
522 | returned. This function must guarantee that all PCI read and write operations\r | |
523 | are serialized.\r | |
524 | \r | |
525 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
526 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
527 | \r | |
2fc59a00 | 528 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 529 | Register.\r |
530 | @param OrData The value to OR with the PCI configuration register.\r | |
531 | \r | |
532 | @return The value written back to the PCI configuration register.\r | |
533 | \r | |
534 | **/\r | |
535 | UINT16\r | |
536 | EFIAPI\r | |
537 | PciExpressOr16 (\r | |
538 | IN UINTN Address,\r | |
539 | IN UINT16 OrData\r | |
540 | )\r | |
541 | {\r | |
542 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
543 | return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
544 | }\r | |
545 | \r | |
546 | /**\r | |
547 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
548 | value.\r | |
549 | \r | |
550 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
551 | bitwise AND between the read result and the value specified by AndData, and\r | |
552 | writes the result to the 16-bit PCI configuration register specified by\r | |
553 | Address. The value written to the PCI configuration register is returned.\r | |
554 | This function must guarantee that all PCI read and write operations are\r | |
555 | serialized.\r | |
556 | \r | |
557 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
558 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
559 | \r | |
2fc59a00 | 560 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 561 | Register.\r |
562 | @param AndData The value to AND with the PCI configuration register.\r | |
563 | \r | |
564 | @return The value written back to the PCI configuration register.\r | |
565 | \r | |
566 | **/\r | |
567 | UINT16\r | |
568 | EFIAPI\r | |
569 | PciExpressAnd16 (\r | |
570 | IN UINTN Address,\r | |
571 | IN UINT16 AndData\r | |
572 | )\r | |
573 | {\r | |
574 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
575 | return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
576 | }\r | |
577 | \r | |
578 | /**\r | |
579 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 580 | value, followed a bitwise OR with another 16-bit value.\r |
e1f414b6 | 581 | \r |
582 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
583 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 584 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 585 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
586 | configuration register specified by Address. The value written to the PCI\r | |
587 | configuration register is returned. This function must guarantee that all PCI\r | |
588 | read and write operations are serialized.\r | |
589 | \r | |
590 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
591 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
592 | \r | |
2fc59a00 | 593 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 594 | Register.\r |
595 | @param AndData The value to AND with the PCI configuration register.\r | |
596 | @param OrData The value to OR with the result of the AND operation.\r | |
597 | \r | |
598 | @return The value written back to the PCI configuration register.\r | |
599 | \r | |
600 | **/\r | |
601 | UINT16\r | |
602 | EFIAPI\r | |
603 | PciExpressAndThenOr16 (\r | |
604 | IN UINTN Address,\r | |
605 | IN UINT16 AndData,\r | |
606 | IN UINT16 OrData\r | |
607 | )\r | |
608 | {\r | |
609 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
610 | return MmioAndThenOr16 (\r | |
611 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
612 | AndData,\r | |
613 | OrData\r | |
614 | );\r | |
615 | }\r | |
616 | \r | |
617 | /**\r | |
618 | Reads a bit field of a PCI configuration register.\r | |
619 | \r | |
620 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
621 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
622 | returned.\r | |
623 | \r | |
624 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
625 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
626 | If StartBit is greater than 15, then ASSERT().\r | |
627 | If EndBit is greater than 15, then ASSERT().\r | |
628 | If EndBit is less than StartBit, then ASSERT().\r | |
629 | \r | |
2fc59a00 | 630 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 631 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
632 | Range 0..15.\r | |
633 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
634 | Range 0..15.\r | |
635 | \r | |
636 | @return The value of the bit field read from the PCI configuration register.\r | |
637 | \r | |
638 | **/\r | |
639 | UINT16\r | |
640 | EFIAPI\r | |
641 | PciExpressBitFieldRead16 (\r | |
642 | IN UINTN Address,\r | |
643 | IN UINTN StartBit,\r | |
644 | IN UINTN EndBit\r | |
645 | )\r | |
646 | {\r | |
647 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
648 | return MmioBitFieldRead16 (\r | |
649 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
650 | StartBit,\r | |
651 | EndBit\r | |
652 | );\r | |
653 | }\r | |
654 | \r | |
655 | /**\r | |
656 | Writes a bit field to a PCI configuration register.\r | |
657 | \r | |
658 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
659 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
660 | destination PCI configuration register are preserved. The new value of the\r | |
661 | 16-bit register is returned.\r | |
662 | \r | |
663 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
664 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
665 | If StartBit is greater than 15, then ASSERT().\r | |
666 | If EndBit is greater than 15, then ASSERT().\r | |
667 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 668 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 669 | \r |
2fc59a00 | 670 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 671 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
672 | Range 0..15.\r | |
673 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
674 | Range 0..15.\r | |
2fc59a00 | 675 | @param Value The new value of the bit field.\r |
e1f414b6 | 676 | \r |
677 | @return The value written back to the PCI configuration register.\r | |
678 | \r | |
679 | **/\r | |
680 | UINT16\r | |
681 | EFIAPI\r | |
682 | PciExpressBitFieldWrite16 (\r | |
683 | IN UINTN Address,\r | |
684 | IN UINTN StartBit,\r | |
685 | IN UINTN EndBit,\r | |
686 | IN UINT16 Value\r | |
687 | )\r | |
688 | {\r | |
689 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
690 | return MmioBitFieldWrite16 (\r | |
691 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
692 | StartBit,\r | |
693 | EndBit,\r | |
694 | Value\r | |
695 | );\r | |
696 | }\r | |
697 | \r | |
698 | /**\r | |
699 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
700 | writes the result back to the bit field in the 16-bit port.\r | |
701 | \r | |
702 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 703 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 704 | OrData, and writes the result to the 16-bit PCI configuration register\r |
705 | specified by Address. The value written to the PCI configuration register is\r | |
706 | returned. This function must guarantee that all PCI read and write operations\r | |
707 | are serialized. Extra left bits in OrData are stripped.\r | |
708 | \r | |
709 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
710 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
711 | If StartBit is greater than 15, then ASSERT().\r | |
712 | If EndBit is greater than 15, then ASSERT().\r | |
713 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 714 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 715 | \r |
2fc59a00 | 716 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 717 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
718 | Range 0..15.\r | |
719 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
720 | Range 0..15.\r | |
721 | @param OrData The value to OR with the PCI configuration register.\r | |
722 | \r | |
723 | @return The value written back to the PCI configuration register.\r | |
724 | \r | |
725 | **/\r | |
726 | UINT16\r | |
727 | EFIAPI\r | |
728 | PciExpressBitFieldOr16 (\r | |
729 | IN UINTN Address,\r | |
730 | IN UINTN StartBit,\r | |
731 | IN UINTN EndBit,\r | |
732 | IN UINT16 OrData\r | |
733 | )\r | |
734 | {\r | |
735 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
736 | return MmioBitFieldOr16 (\r | |
737 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
738 | StartBit,\r | |
739 | EndBit,\r | |
740 | OrData\r | |
741 | );\r | |
742 | }\r | |
743 | \r | |
744 | /**\r | |
745 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
746 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
747 | \r | |
748 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
749 | bitwise AND between the read result and the value specified by AndData, and\r | |
750 | writes the result to the 16-bit PCI configuration register specified by\r | |
751 | Address. The value written to the PCI configuration register is returned.\r | |
752 | This function must guarantee that all PCI read and write operations are\r | |
753 | serialized. Extra left bits in AndData are stripped.\r | |
754 | \r | |
755 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
756 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
757 | If StartBit is greater than 15, then ASSERT().\r | |
758 | If EndBit is greater than 15, then ASSERT().\r | |
759 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 760 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 761 | \r |
2fc59a00 | 762 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 763 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
764 | Range 0..15.\r | |
765 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
766 | Range 0..15.\r | |
767 | @param AndData The value to AND with the PCI configuration register.\r | |
768 | \r | |
769 | @return The value written back to the PCI configuration register.\r | |
770 | \r | |
771 | **/\r | |
772 | UINT16\r | |
773 | EFIAPI\r | |
774 | PciExpressBitFieldAnd16 (\r | |
775 | IN UINTN Address,\r | |
776 | IN UINTN StartBit,\r | |
777 | IN UINTN EndBit,\r | |
778 | IN UINT16 AndData\r | |
779 | )\r | |
780 | {\r | |
781 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
782 | return MmioBitFieldAnd16 (\r | |
783 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
784 | StartBit,\r | |
785 | EndBit,\r | |
786 | AndData\r | |
787 | );\r | |
788 | }\r | |
789 | \r | |
790 | /**\r | |
791 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 792 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 793 | 16-bit port.\r |
794 | \r | |
795 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 796 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 797 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
798 | configuration register specified by Address. The value written to the PCI\r | |
799 | configuration register is returned. This function must guarantee that all PCI\r | |
800 | read and write operations are serialized. Extra left bits in both AndData and\r | |
801 | OrData are stripped.\r | |
802 | \r | |
803 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
804 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
805 | If StartBit is greater than 15, then ASSERT().\r | |
806 | If EndBit is greater than 15, then ASSERT().\r | |
807 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
808 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
809 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 810 | \r |
2fc59a00 | 811 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 812 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
813 | Range 0..15.\r | |
814 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
815 | Range 0..15.\r | |
816 | @param AndData The value to AND with the PCI configuration register.\r | |
817 | @param OrData The value to OR with the result of the AND operation.\r | |
818 | \r | |
819 | @return The value written back to the PCI configuration register.\r | |
820 | \r | |
821 | **/\r | |
822 | UINT16\r | |
823 | EFIAPI\r | |
824 | PciExpressBitFieldAndThenOr16 (\r | |
825 | IN UINTN Address,\r | |
826 | IN UINTN StartBit,\r | |
827 | IN UINTN EndBit,\r | |
828 | IN UINT16 AndData,\r | |
829 | IN UINT16 OrData\r | |
830 | )\r | |
831 | {\r | |
832 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
833 | return MmioBitFieldAndThenOr16 (\r | |
834 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
835 | StartBit,\r | |
836 | EndBit,\r | |
837 | AndData,\r | |
838 | OrData\r | |
839 | );\r | |
840 | }\r | |
841 | \r | |
842 | /**\r | |
843 | Reads a 32-bit PCI configuration register.\r | |
844 | \r | |
845 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
846 | This function must guarantee that all PCI read and write operations are\r | |
847 | serialized.\r | |
848 | \r | |
849 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
850 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
851 | \r | |
2fc59a00 | 852 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 853 | Register.\r |
854 | \r | |
855 | @return The read value from the PCI configuration register.\r | |
856 | \r | |
857 | **/\r | |
858 | UINT32\r | |
859 | EFIAPI\r | |
860 | PciExpressRead32 (\r | |
861 | IN UINTN Address\r | |
862 | )\r | |
863 | {\r | |
864 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
865 | return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
866 | }\r | |
867 | \r | |
868 | /**\r | |
869 | Writes a 32-bit PCI configuration register.\r | |
870 | \r | |
871 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
872 | value specified by Value. Value is returned. This function must guarantee\r | |
873 | that all PCI read and write operations are serialized.\r | |
874 | \r | |
875 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
876 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
877 | \r | |
2fc59a00 | 878 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 879 | Register.\r |
880 | @param Value The value to write.\r | |
881 | \r | |
882 | @return The value written to the PCI configuration register.\r | |
883 | \r | |
884 | **/\r | |
885 | UINT32\r | |
886 | EFIAPI\r | |
887 | PciExpressWrite32 (\r | |
888 | IN UINTN Address,\r | |
889 | IN UINT32 Value\r | |
890 | )\r | |
891 | {\r | |
892 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
893 | return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
894 | }\r | |
895 | \r | |
896 | /**\r | |
62991af2 | 897 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
e1f414b6 | 898 | a 32-bit value.\r |
899 | \r | |
900 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 901 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 902 | OrData, and writes the result to the 32-bit PCI configuration register\r |
903 | specified by Address. The value written to the PCI configuration register is\r | |
904 | returned. This function must guarantee that all PCI read and write operations\r | |
905 | are serialized.\r | |
906 | \r | |
907 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
908 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
909 | \r | |
2fc59a00 | 910 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 911 | Register.\r |
912 | @param OrData The value to OR with the PCI configuration register.\r | |
913 | \r | |
914 | @return The value written back to the PCI configuration register.\r | |
915 | \r | |
916 | **/\r | |
917 | UINT32\r | |
918 | EFIAPI\r | |
919 | PciExpressOr32 (\r | |
920 | IN UINTN Address,\r | |
921 | IN UINT32 OrData\r | |
922 | )\r | |
923 | {\r | |
924 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
925 | return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
926 | }\r | |
927 | \r | |
928 | /**\r | |
929 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
930 | value.\r | |
931 | \r | |
932 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
933 | bitwise AND between the read result and the value specified by AndData, and\r | |
934 | writes the result to the 32-bit PCI configuration register specified by\r | |
935 | Address. The value written to the PCI configuration register is returned.\r | |
936 | This function must guarantee that all PCI read and write operations are\r | |
937 | serialized.\r | |
938 | \r | |
939 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
940 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
941 | \r | |
2fc59a00 | 942 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 943 | Register.\r |
944 | @param AndData The value to AND with the PCI configuration register.\r | |
945 | \r | |
946 | @return The value written back to the PCI configuration register.\r | |
947 | \r | |
948 | **/\r | |
949 | UINT32\r | |
950 | EFIAPI\r | |
951 | PciExpressAnd32 (\r | |
952 | IN UINTN Address,\r | |
953 | IN UINT32 AndData\r | |
954 | )\r | |
955 | {\r | |
956 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
957 | return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
958 | }\r | |
959 | \r | |
960 | /**\r | |
961 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 962 | value, followed a bitwise OR with another 32-bit value.\r |
e1f414b6 | 963 | \r |
964 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
965 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 966 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 967 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
968 | configuration register specified by Address. The value written to the PCI\r | |
969 | configuration register is returned. This function must guarantee that all PCI\r | |
970 | read and write operations are serialized.\r | |
971 | \r | |
972 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
973 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
974 | \r | |
2fc59a00 | 975 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 976 | Register.\r |
977 | @param AndData The value to AND with the PCI configuration register.\r | |
978 | @param OrData The value to OR with the result of the AND operation.\r | |
979 | \r | |
980 | @return The value written back to the PCI configuration register.\r | |
981 | \r | |
982 | **/\r | |
983 | UINT32\r | |
984 | EFIAPI\r | |
985 | PciExpressAndThenOr32 (\r | |
986 | IN UINTN Address,\r | |
987 | IN UINT32 AndData,\r | |
988 | IN UINT32 OrData\r | |
989 | )\r | |
990 | {\r | |
991 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
992 | return MmioAndThenOr32 (\r | |
993 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
994 | AndData,\r | |
995 | OrData\r | |
996 | );\r | |
997 | }\r | |
998 | \r | |
999 | /**\r | |
1000 | Reads a bit field of a PCI configuration register.\r | |
1001 | \r | |
1002 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1003 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1004 | returned.\r | |
1005 | \r | |
1006 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1007 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1008 | If StartBit is greater than 31, then ASSERT().\r | |
1009 | If EndBit is greater than 31, then ASSERT().\r | |
1010 | If EndBit is less than StartBit, then ASSERT().\r | |
1011 | \r | |
2fc59a00 | 1012 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 1013 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1014 | Range 0..31.\r | |
1015 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1016 | Range 0..31.\r | |
1017 | \r | |
1018 | @return The value of the bit field read from the PCI configuration register.\r | |
1019 | \r | |
1020 | **/\r | |
1021 | UINT32\r | |
1022 | EFIAPI\r | |
1023 | PciExpressBitFieldRead32 (\r | |
1024 | IN UINTN Address,\r | |
1025 | IN UINTN StartBit,\r | |
1026 | IN UINTN EndBit\r | |
1027 | )\r | |
1028 | {\r | |
1029 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1030 | return MmioBitFieldRead32 (\r | |
1031 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1032 | StartBit,\r | |
1033 | EndBit\r | |
1034 | );\r | |
1035 | }\r | |
1036 | \r | |
1037 | /**\r | |
1038 | Writes a bit field to a PCI configuration register.\r | |
1039 | \r | |
1040 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1041 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1042 | destination PCI configuration register are preserved. The new value of the\r | |
1043 | 32-bit register is returned.\r | |
1044 | \r | |
1045 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1046 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1047 | If StartBit is greater than 31, then ASSERT().\r | |
1048 | If EndBit is greater than 31, then ASSERT().\r | |
1049 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1050 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 1051 | \r |
2fc59a00 | 1052 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1053 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1054 | Range 0..31.\r | |
1055 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1056 | Range 0..31.\r | |
2fc59a00 | 1057 | @param Value The new value of the bit field.\r |
e1f414b6 | 1058 | \r |
1059 | @return The value written back to the PCI configuration register.\r | |
1060 | \r | |
1061 | **/\r | |
1062 | UINT32\r | |
1063 | EFIAPI\r | |
1064 | PciExpressBitFieldWrite32 (\r | |
1065 | IN UINTN Address,\r | |
1066 | IN UINTN StartBit,\r | |
1067 | IN UINTN EndBit,\r | |
1068 | IN UINT32 Value\r | |
1069 | )\r | |
1070 | {\r | |
1071 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1072 | return MmioBitFieldWrite32 (\r | |
1073 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1074 | StartBit,\r | |
1075 | EndBit,\r | |
1076 | Value\r | |
1077 | );\r | |
1078 | }\r | |
1079 | \r | |
1080 | /**\r | |
1081 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1082 | writes the result back to the bit field in the 32-bit port.\r | |
1083 | \r | |
1084 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1085 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 1086 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1087 | specified by Address. The value written to the PCI configuration register is\r | |
1088 | returned. This function must guarantee that all PCI read and write operations\r | |
1089 | are serialized. Extra left bits in OrData are stripped.\r | |
1090 | \r | |
1091 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1092 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1093 | If StartBit is greater than 31, then ASSERT().\r | |
1094 | If EndBit is greater than 31, then ASSERT().\r | |
1095 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1096 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 1097 | \r |
2fc59a00 | 1098 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1099 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1100 | Range 0..31.\r | |
1101 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1102 | Range 0..31.\r | |
1103 | @param OrData The value to OR with the PCI configuration register.\r | |
1104 | \r | |
1105 | @return The value written back to the PCI configuration register.\r | |
1106 | \r | |
1107 | **/\r | |
1108 | UINT32\r | |
1109 | EFIAPI\r | |
1110 | PciExpressBitFieldOr32 (\r | |
1111 | IN UINTN Address,\r | |
1112 | IN UINTN StartBit,\r | |
1113 | IN UINTN EndBit,\r | |
1114 | IN UINT32 OrData\r | |
1115 | )\r | |
1116 | {\r | |
1117 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1118 | return MmioBitFieldOr32 (\r | |
1119 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1120 | StartBit,\r | |
1121 | EndBit,\r | |
1122 | OrData\r | |
1123 | );\r | |
1124 | }\r | |
1125 | \r | |
1126 | /**\r | |
1127 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1128 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1129 | \r | |
1130 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1131 | bitwise AND between the read result and the value specified by AndData, and\r | |
1132 | writes the result to the 32-bit PCI configuration register specified by\r | |
1133 | Address. The value written to the PCI configuration register is returned.\r | |
1134 | This function must guarantee that all PCI read and write operations are\r | |
1135 | serialized. Extra left bits in AndData are stripped.\r | |
1136 | \r | |
1137 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1138 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1139 | If StartBit is greater than 31, then ASSERT().\r | |
1140 | If EndBit is greater than 31, then ASSERT().\r | |
1141 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1142 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 1143 | \r |
2fc59a00 | 1144 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1145 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1146 | Range 0..31.\r | |
1147 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1148 | Range 0..31.\r | |
1149 | @param AndData The value to AND with the PCI configuration register.\r | |
1150 | \r | |
1151 | @return The value written back to the PCI configuration register.\r | |
1152 | \r | |
1153 | **/\r | |
1154 | UINT32\r | |
1155 | EFIAPI\r | |
1156 | PciExpressBitFieldAnd32 (\r | |
1157 | IN UINTN Address,\r | |
1158 | IN UINTN StartBit,\r | |
1159 | IN UINTN EndBit,\r | |
1160 | IN UINT32 AndData\r | |
1161 | )\r | |
1162 | {\r | |
1163 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1164 | return MmioBitFieldAnd32 (\r | |
1165 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1166 | StartBit,\r | |
1167 | EndBit,\r | |
1168 | AndData\r | |
1169 | );\r | |
1170 | }\r | |
1171 | \r | |
1172 | /**\r | |
1173 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1174 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 1175 | 32-bit port.\r |
1176 | \r | |
1177 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1178 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 1179 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1180 | configuration register specified by Address. The value written to the PCI\r | |
1181 | configuration register is returned. This function must guarantee that all PCI\r | |
1182 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1183 | OrData are stripped.\r | |
1184 | \r | |
1185 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1186 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1187 | If StartBit is greater than 31, then ASSERT().\r | |
1188 | If EndBit is greater than 31, then ASSERT().\r | |
1189 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1190 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1191 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 1192 | \r |
2fc59a00 | 1193 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1194 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1195 | Range 0..31.\r | |
1196 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1197 | Range 0..31.\r | |
1198 | @param AndData The value to AND with the PCI configuration register.\r | |
1199 | @param OrData The value to OR with the result of the AND operation.\r | |
1200 | \r | |
1201 | @return The value written back to the PCI configuration register.\r | |
1202 | \r | |
1203 | **/\r | |
1204 | UINT32\r | |
1205 | EFIAPI\r | |
1206 | PciExpressBitFieldAndThenOr32 (\r | |
1207 | IN UINTN Address,\r | |
1208 | IN UINTN StartBit,\r | |
1209 | IN UINTN EndBit,\r | |
1210 | IN UINT32 AndData,\r | |
1211 | IN UINT32 OrData\r | |
1212 | )\r | |
1213 | {\r | |
1214 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1215 | return MmioBitFieldAndThenOr32 (\r | |
1216 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1217 | StartBit,\r | |
1218 | EndBit,\r | |
1219 | AndData,\r | |
1220 | OrData\r | |
1221 | );\r | |
1222 | }\r | |
1223 | \r | |
1224 | /**\r | |
1225 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1226 | \r | |
1227 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1228 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1229 | configuration registers from a single PCI function to be read. Size is\r | |
1230 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1231 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1232 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1233 | end of the range.\r | |
1234 | \r | |
1235 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1236 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1237 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1238 | \r | |
2fc59a00 | 1239 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1240 | Function and Register.\r |
2fc59a00 | 1241 | @param Size The size in bytes of the transfer.\r |
1242 | @param Buffer The pointer to a buffer receiving the data read.\r | |
e1f414b6 | 1243 | \r |
9638ba6d | 1244 | @return Size read data from StartAddress.\r |
e1f414b6 | 1245 | \r |
1246 | **/\r | |
1247 | UINTN\r | |
1248 | EFIAPI\r | |
1249 | PciExpressReadBuffer (\r | |
1250 | IN UINTN StartAddress,\r | |
1251 | IN UINTN Size,\r | |
1252 | OUT VOID *Buffer\r | |
1253 | )\r | |
1254 | {\r | |
0c62737d | 1255 | UINTN ReturnValue;\r |
e1f414b6 | 1256 | \r |
1257 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1258 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1259 | \r | |
1260 | if (Size == 0) {\r | |
1261 | return Size;\r | |
1262 | }\r | |
1263 | \r | |
1264 | ASSERT (Buffer != NULL);\r | |
1265 | \r | |
1266 | //\r | |
1267 | // Save Size for return\r | |
1268 | //\r | |
1269 | ReturnValue = Size;\r | |
1270 | \r | |
1271 | if ((StartAddress & 1) != 0) {\r | |
1272 | //\r | |
1273 | // Read a byte if StartAddress is byte aligned\r | |
1274 | //\r | |
1275 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1276 | StartAddress += sizeof (UINT8);\r | |
1277 | Size -= sizeof (UINT8);\r | |
1278 | Buffer = (UINT8*)Buffer + 1;\r | |
1279 | }\r | |
1280 | \r | |
1281 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1282 | //\r | |
1283 | // Read a word if StartAddress is word aligned\r | |
1284 | //\r | |
af2bb549 | 1285 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r |
0c62737d | 1286 | \r |
e1f414b6 | 1287 | StartAddress += sizeof (UINT16);\r |
1288 | Size -= sizeof (UINT16);\r | |
1289 | Buffer = (UINT16*)Buffer + 1;\r | |
1290 | }\r | |
1291 | \r | |
1292 | while (Size >= sizeof (UINT32)) {\r | |
1293 | //\r | |
1294 | // Read as many double words as possible\r | |
1295 | //\r | |
af2bb549 | 1296 | WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r |
0c62737d | 1297 | \r |
e1f414b6 | 1298 | StartAddress += sizeof (UINT32);\r |
1299 | Size -= sizeof (UINT32);\r | |
1300 | Buffer = (UINT32*)Buffer + 1;\r | |
1301 | }\r | |
1302 | \r | |
1303 | if (Size >= sizeof (UINT16)) {\r | |
1304 | //\r | |
1305 | // Read the last remaining word if exist\r | |
1306 | //\r | |
af2bb549 | 1307 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r |
e1f414b6 | 1308 | StartAddress += sizeof (UINT16);\r |
1309 | Size -= sizeof (UINT16);\r | |
1310 | Buffer = (UINT16*)Buffer + 1;\r | |
1311 | }\r | |
1312 | \r | |
1313 | if (Size >= sizeof (UINT8)) {\r | |
1314 | //\r | |
1315 | // Read the last remaining byte if exist\r | |
1316 | //\r | |
1317 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1318 | }\r | |
1319 | \r | |
1320 | return ReturnValue;\r | |
1321 | }\r | |
1322 | \r | |
1323 | /**\r | |
1324 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1325 | configuration space.\r | |
1326 | \r | |
1327 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1328 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1329 | configuration registers from a single PCI function to be written. Size is\r | |
1330 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1331 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1332 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1333 | and the end of the range.\r | |
1334 | \r | |
1335 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1336 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1337 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1338 | \r | |
2fc59a00 | 1339 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1340 | Function and Register.\r |
2fc59a00 | 1341 | @param Size The size in bytes of the transfer.\r |
1342 | @param Buffer The pointer to a buffer containing the data to write.\r | |
e1f414b6 | 1343 | \r |
9638ba6d | 1344 | @return Size written to StartAddress.\r |
e1f414b6 | 1345 | \r |
1346 | **/\r | |
1347 | UINTN\r | |
1348 | EFIAPI\r | |
1349 | PciExpressWriteBuffer (\r | |
1350 | IN UINTN StartAddress,\r | |
1351 | IN UINTN Size,\r | |
1352 | IN VOID *Buffer\r | |
1353 | )\r | |
1354 | {\r | |
1355 | UINTN ReturnValue;\r | |
1356 | \r | |
1357 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1358 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1359 | \r | |
1360 | if (Size == 0) {\r | |
1361 | return 0;\r | |
1362 | }\r | |
1363 | \r | |
1364 | ASSERT (Buffer != NULL);\r | |
1365 | \r | |
1366 | //\r | |
1367 | // Save Size for return\r | |
1368 | //\r | |
1369 | ReturnValue = Size;\r | |
1370 | \r | |
1371 | if ((StartAddress & 1) != 0) {\r | |
1372 | //\r | |
1373 | // Write a byte if StartAddress is byte aligned\r | |
1374 | //\r | |
1375 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1376 | StartAddress += sizeof (UINT8);\r | |
1377 | Size -= sizeof (UINT8);\r | |
1378 | Buffer = (UINT8*)Buffer + 1;\r | |
1379 | }\r | |
1380 | \r | |
1381 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1382 | //\r | |
1383 | // Write a word if StartAddress is word aligned\r | |
1384 | //\r | |
0c62737d | 1385 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r |
e1f414b6 | 1386 | StartAddress += sizeof (UINT16);\r |
1387 | Size -= sizeof (UINT16);\r | |
1388 | Buffer = (UINT16*)Buffer + 1;\r | |
1389 | }\r | |
1390 | \r | |
1391 | while (Size >= sizeof (UINT32)) {\r | |
1392 | //\r | |
1393 | // Write as many double words as possible\r | |
1394 | //\r | |
0c62737d | 1395 | PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r |
e1f414b6 | 1396 | StartAddress += sizeof (UINT32);\r |
1397 | Size -= sizeof (UINT32);\r | |
1398 | Buffer = (UINT32*)Buffer + 1;\r | |
1399 | }\r | |
1400 | \r | |
1401 | if (Size >= sizeof (UINT16)) {\r | |
1402 | //\r | |
1403 | // Write the last remaining word if exist\r | |
1404 | //\r | |
0c62737d | 1405 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r |
e1f414b6 | 1406 | StartAddress += sizeof (UINT16);\r |
1407 | Size -= sizeof (UINT16);\r | |
1408 | Buffer = (UINT16*)Buffer + 1;\r | |
1409 | }\r | |
1410 | \r | |
1411 | if (Size >= sizeof (UINT8)) {\r | |
1412 | //\r | |
1413 | // Write the last remaining byte if exist\r | |
1414 | //\r | |
1415 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1416 | }\r | |
1417 | \r | |
1418 | return ReturnValue;\r | |
1419 | }\r |