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e1f414b6 | 1 | /** @file\r |
e1f414b6 | 2 | Functions in this library instance make use of MMIO functions in IoLib to\r |
3 | access memory mapped PCI configuration space.\r | |
4 | \r | |
5 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r | |
6 | Library.\r | |
7 | \r | |
9095d37b | 8 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
e1f414b6 | 10 | \r |
e1f414b6 | 11 | **/\r |
12 | \r | |
c892d846 | 13 | \r |
c7d265a9 | 14 | #include <Base.h>\r |
c892d846 | 15 | \r |
0c62737d | 16 | #include <Library/BaseLib.h>\r |
c7d265a9 | 17 | #include <Library/PciExpressLib.h>\r |
18 | #include <Library/IoLib.h>\r | |
19 | #include <Library/DebugLib.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | \r | |
e1f414b6 | 22 | \r |
23 | /**\r | |
24 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
25 | only in the low 28 bits.\r | |
26 | \r | |
27 | @param A The address to validate.\r | |
28 | \r | |
29 | **/\r | |
30 | #define ASSERT_INVALID_PCI_ADDRESS(A) \\r | |
31 | ASSERT (((A) & ~0xfffffff) == 0)\r | |
32 | \r | |
3e3ae634 | 33 | /**\r |
9095d37b | 34 | Registers a PCI device so PCI configuration registers may be accessed after\r |
3e3ae634 | 35 | SetVirtualAddressMap().\r |
9095d37b LG |
36 | \r |
37 | Registers the PCI device specified by Address so all the PCI configuration\r | |
38 | registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r | |
d11195a3 | 39 | is called.\r |
9095d37b | 40 | \r |
3e3ae634 | 41 | If Address > 0x0FFFFFFF, then ASSERT().\r |
42 | \r | |
2fc59a00 | 43 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 44 | Register.\r |
9095d37b | 45 | \r |
3e3ae634 | 46 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
9095d37b | 47 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
3e3ae634 | 48 | after ExitBootServices().\r |
49 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
50 | at runtime could not be mapped.\r | |
51 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
52 | complete the registration.\r | |
53 | \r | |
54 | **/\r | |
55 | RETURN_STATUS\r | |
56 | EFIAPI\r | |
57 | PciExpressRegisterForRuntimeAccess (\r | |
58 | IN UINTN Address\r | |
59 | )\r | |
60 | {\r | |
59ceeabe | 61 | ASSERT_INVALID_PCI_ADDRESS (Address);\r |
3e3ae634 | 62 | return RETURN_UNSUPPORTED;\r |
63 | }\r | |
e1f414b6 | 64 | \r |
65 | /**\r | |
66 | Gets the base address of PCI Express.\r | |
9095d37b | 67 | \r |
e1f414b6 | 68 | This internal functions retrieves PCI Express Base Address via a PCD entry\r |
69 | PcdPciExpressBaseAddress.\r | |
9095d37b | 70 | \r |
e1f414b6 | 71 | @return The base address of PCI Express.\r |
72 | \r | |
73 | **/\r | |
94646ec0 | 74 | VOID*\r |
e1f414b6 | 75 | GetPciExpressBaseAddress (\r |
76 | VOID\r | |
77 | )\r | |
78 | {\r | |
79 | return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r | |
80 | }\r | |
81 | \r | |
82 | /**\r | |
83 | Reads an 8-bit PCI configuration register.\r | |
84 | \r | |
85 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
86 | This function must guarantee that all PCI read and write operations are\r | |
87 | serialized.\r | |
88 | \r | |
89 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
90 | \r | |
2fc59a00 | 91 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 92 | Register.\r |
93 | \r | |
94 | @return The read value from the PCI configuration register.\r | |
95 | \r | |
96 | **/\r | |
97 | UINT8\r | |
98 | EFIAPI\r | |
99 | PciExpressRead8 (\r | |
100 | IN UINTN Address\r | |
101 | )\r | |
102 | {\r | |
103 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
104 | return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
105 | }\r | |
106 | \r | |
107 | /**\r | |
108 | Writes an 8-bit PCI configuration register.\r | |
109 | \r | |
110 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
111 | value specified by Value. Value is returned. This function must guarantee\r | |
112 | that all PCI read and write operations are serialized.\r | |
113 | \r | |
114 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
115 | \r | |
2fc59a00 | 116 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 117 | Register.\r |
118 | @param Value The value to write.\r | |
119 | \r | |
120 | @return The value written to the PCI configuration register.\r | |
121 | \r | |
122 | **/\r | |
123 | UINT8\r | |
124 | EFIAPI\r | |
125 | PciExpressWrite8 (\r | |
126 | IN UINTN Address,\r | |
127 | IN UINT8 Value\r | |
128 | )\r | |
129 | {\r | |
130 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
131 | return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
132 | }\r | |
133 | \r | |
134 | /**\r | |
62991af2 | 135 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
e1f414b6 | 136 | an 8-bit value.\r |
137 | \r | |
138 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 139 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 140 | OrData, and writes the result to the 8-bit PCI configuration register\r |
141 | specified by Address. The value written to the PCI configuration register is\r | |
142 | returned. This function must guarantee that all PCI read and write operations\r | |
143 | are serialized.\r | |
144 | \r | |
145 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
146 | \r | |
2fc59a00 | 147 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 148 | Register.\r |
149 | @param OrData The value to OR with the PCI configuration register.\r | |
150 | \r | |
151 | @return The value written back to the PCI configuration register.\r | |
152 | \r | |
153 | **/\r | |
154 | UINT8\r | |
155 | EFIAPI\r | |
156 | PciExpressOr8 (\r | |
157 | IN UINTN Address,\r | |
158 | IN UINT8 OrData\r | |
159 | )\r | |
160 | {\r | |
161 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
162 | return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
163 | }\r | |
164 | \r | |
165 | /**\r | |
166 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
167 | value.\r | |
168 | \r | |
169 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
170 | bitwise AND between the read result and the value specified by AndData, and\r | |
171 | writes the result to the 8-bit PCI configuration register specified by\r | |
172 | Address. The value written to the PCI configuration register is returned.\r | |
173 | This function must guarantee that all PCI read and write operations are\r | |
174 | serialized.\r | |
175 | \r | |
176 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
177 | \r | |
2fc59a00 | 178 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 179 | Register.\r |
180 | @param AndData The value to AND with the PCI configuration register.\r | |
181 | \r | |
182 | @return The value written back to the PCI configuration register.\r | |
183 | \r | |
184 | **/\r | |
185 | UINT8\r | |
186 | EFIAPI\r | |
187 | PciExpressAnd8 (\r | |
188 | IN UINTN Address,\r | |
189 | IN UINT8 AndData\r | |
190 | )\r | |
191 | {\r | |
192 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
193 | return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
194 | }\r | |
195 | \r | |
196 | /**\r | |
197 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 198 | value, followed a bitwise OR with another 8-bit value.\r |
e1f414b6 | 199 | \r |
200 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
201 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 202 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 203 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
204 | configuration register specified by Address. The value written to the PCI\r | |
205 | configuration register is returned. This function must guarantee that all PCI\r | |
206 | read and write operations are serialized.\r | |
207 | \r | |
208 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
209 | \r | |
2fc59a00 | 210 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 211 | Register.\r |
212 | @param AndData The value to AND with the PCI configuration register.\r | |
213 | @param OrData The value to OR with the result of the AND operation.\r | |
214 | \r | |
215 | @return The value written back to the PCI configuration register.\r | |
216 | \r | |
217 | **/\r | |
218 | UINT8\r | |
219 | EFIAPI\r | |
220 | PciExpressAndThenOr8 (\r | |
221 | IN UINTN Address,\r | |
222 | IN UINT8 AndData,\r | |
223 | IN UINT8 OrData\r | |
224 | )\r | |
225 | {\r | |
226 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
227 | return MmioAndThenOr8 (\r | |
228 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
229 | AndData,\r | |
230 | OrData\r | |
231 | );\r | |
232 | }\r | |
233 | \r | |
234 | /**\r | |
235 | Reads a bit field of a PCI configuration register.\r | |
236 | \r | |
237 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
238 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
239 | returned.\r | |
240 | \r | |
241 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
242 | If StartBit is greater than 7, then ASSERT().\r | |
243 | If EndBit is greater than 7, then ASSERT().\r | |
244 | If EndBit is less than StartBit, then ASSERT().\r | |
245 | \r | |
2fc59a00 | 246 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 247 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
248 | Range 0..7.\r | |
249 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
250 | Range 0..7.\r | |
251 | \r | |
252 | @return The value of the bit field read from the PCI configuration register.\r | |
253 | \r | |
254 | **/\r | |
255 | UINT8\r | |
256 | EFIAPI\r | |
257 | PciExpressBitFieldRead8 (\r | |
258 | IN UINTN Address,\r | |
259 | IN UINTN StartBit,\r | |
260 | IN UINTN EndBit\r | |
261 | )\r | |
262 | {\r | |
263 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
264 | return MmioBitFieldRead8 (\r | |
265 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
266 | StartBit,\r | |
267 | EndBit\r | |
268 | );\r | |
269 | }\r | |
270 | \r | |
271 | /**\r | |
272 | Writes a bit field to a PCI configuration register.\r | |
273 | \r | |
274 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
275 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
276 | destination PCI configuration register are preserved. The new value of the\r | |
277 | 8-bit register is returned.\r | |
278 | \r | |
279 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
280 | If StartBit is greater than 7, then ASSERT().\r | |
281 | If EndBit is greater than 7, then ASSERT().\r | |
282 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 283 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 284 | \r |
2fc59a00 | 285 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 286 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
287 | Range 0..7.\r | |
288 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
289 | Range 0..7.\r | |
2fc59a00 | 290 | @param Value The new value of the bit field.\r |
e1f414b6 | 291 | \r |
292 | @return The value written back to the PCI configuration register.\r | |
293 | \r | |
294 | **/\r | |
295 | UINT8\r | |
296 | EFIAPI\r | |
297 | PciExpressBitFieldWrite8 (\r | |
298 | IN UINTN Address,\r | |
299 | IN UINTN StartBit,\r | |
300 | IN UINTN EndBit,\r | |
301 | IN UINT8 Value\r | |
302 | )\r | |
303 | {\r | |
304 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
305 | return MmioBitFieldWrite8 (\r | |
306 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
307 | StartBit,\r | |
308 | EndBit,\r | |
309 | Value\r | |
310 | );\r | |
311 | }\r | |
312 | \r | |
313 | /**\r | |
314 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
315 | writes the result back to the bit field in the 8-bit port.\r | |
316 | \r | |
317 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 318 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 319 | OrData, and writes the result to the 8-bit PCI configuration register\r |
320 | specified by Address. The value written to the PCI configuration register is\r | |
321 | returned. This function must guarantee that all PCI read and write operations\r | |
322 | are serialized. Extra left bits in OrData are stripped.\r | |
323 | \r | |
324 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
325 | If StartBit is greater than 7, then ASSERT().\r | |
326 | If EndBit is greater than 7, then ASSERT().\r | |
327 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 328 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 329 | \r |
2fc59a00 | 330 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 331 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
332 | Range 0..7.\r | |
333 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
334 | Range 0..7.\r | |
335 | @param OrData The value to OR with the PCI configuration register.\r | |
336 | \r | |
337 | @return The value written back to the PCI configuration register.\r | |
338 | \r | |
339 | **/\r | |
340 | UINT8\r | |
341 | EFIAPI\r | |
342 | PciExpressBitFieldOr8 (\r | |
343 | IN UINTN Address,\r | |
344 | IN UINTN StartBit,\r | |
345 | IN UINTN EndBit,\r | |
346 | IN UINT8 OrData\r | |
347 | )\r | |
348 | {\r | |
349 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
350 | return MmioBitFieldOr8 (\r | |
351 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
352 | StartBit,\r | |
353 | EndBit,\r | |
354 | OrData\r | |
355 | );\r | |
356 | }\r | |
357 | \r | |
358 | /**\r | |
359 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
360 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
361 | \r | |
362 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
363 | bitwise AND between the read result and the value specified by AndData, and\r | |
364 | writes the result to the 8-bit PCI configuration register specified by\r | |
365 | Address. The value written to the PCI configuration register is returned.\r | |
366 | This function must guarantee that all PCI read and write operations are\r | |
367 | serialized. Extra left bits in AndData are stripped.\r | |
368 | \r | |
369 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
370 | If StartBit is greater than 7, then ASSERT().\r | |
371 | If EndBit is greater than 7, then ASSERT().\r | |
372 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 373 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 374 | \r |
2fc59a00 | 375 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 376 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
377 | Range 0..7.\r | |
378 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
379 | Range 0..7.\r | |
380 | @param AndData The value to AND with the PCI configuration register.\r | |
381 | \r | |
382 | @return The value written back to the PCI configuration register.\r | |
383 | \r | |
384 | **/\r | |
385 | UINT8\r | |
386 | EFIAPI\r | |
387 | PciExpressBitFieldAnd8 (\r | |
388 | IN UINTN Address,\r | |
389 | IN UINTN StartBit,\r | |
390 | IN UINTN EndBit,\r | |
391 | IN UINT8 AndData\r | |
392 | )\r | |
393 | {\r | |
394 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
395 | return MmioBitFieldAnd8 (\r | |
396 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
397 | StartBit,\r | |
398 | EndBit,\r | |
399 | AndData\r | |
400 | );\r | |
401 | }\r | |
402 | \r | |
403 | /**\r | |
404 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 405 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 406 | 8-bit port.\r |
407 | \r | |
408 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 409 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 410 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
411 | configuration register specified by Address. The value written to the PCI\r | |
412 | configuration register is returned. This function must guarantee that all PCI\r | |
413 | read and write operations are serialized. Extra left bits in both AndData and\r | |
414 | OrData are stripped.\r | |
415 | \r | |
416 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
417 | If StartBit is greater than 7, then ASSERT().\r | |
418 | If EndBit is greater than 7, then ASSERT().\r | |
419 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
420 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
421 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 422 | \r |
2fc59a00 | 423 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 424 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
425 | Range 0..7.\r | |
426 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
427 | Range 0..7.\r | |
428 | @param AndData The value to AND with the PCI configuration register.\r | |
429 | @param OrData The value to OR with the result of the AND operation.\r | |
430 | \r | |
431 | @return The value written back to the PCI configuration register.\r | |
432 | \r | |
433 | **/\r | |
434 | UINT8\r | |
435 | EFIAPI\r | |
436 | PciExpressBitFieldAndThenOr8 (\r | |
437 | IN UINTN Address,\r | |
438 | IN UINTN StartBit,\r | |
439 | IN UINTN EndBit,\r | |
440 | IN UINT8 AndData,\r | |
441 | IN UINT8 OrData\r | |
442 | )\r | |
443 | {\r | |
444 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
445 | return MmioBitFieldAndThenOr8 (\r | |
446 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
447 | StartBit,\r | |
448 | EndBit,\r | |
449 | AndData,\r | |
450 | OrData\r | |
451 | );\r | |
452 | }\r | |
453 | \r | |
454 | /**\r | |
455 | Reads a 16-bit PCI configuration register.\r | |
456 | \r | |
457 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
458 | This function must guarantee that all PCI read and write operations are\r | |
459 | serialized.\r | |
460 | \r | |
461 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
462 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
463 | \r | |
2fc59a00 | 464 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 465 | Register.\r |
466 | \r | |
467 | @return The read value from the PCI configuration register.\r | |
468 | \r | |
469 | **/\r | |
470 | UINT16\r | |
471 | EFIAPI\r | |
472 | PciExpressRead16 (\r | |
473 | IN UINTN Address\r | |
474 | )\r | |
475 | {\r | |
476 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
477 | return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
478 | }\r | |
479 | \r | |
480 | /**\r | |
481 | Writes a 16-bit PCI configuration register.\r | |
482 | \r | |
483 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
484 | value specified by Value. Value is returned. This function must guarantee\r | |
485 | that all PCI read and write operations are serialized.\r | |
486 | \r | |
487 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
488 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
489 | \r | |
2fc59a00 | 490 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 491 | Register.\r |
492 | @param Value The value to write.\r | |
493 | \r | |
494 | @return The value written to the PCI configuration register.\r | |
495 | \r | |
496 | **/\r | |
497 | UINT16\r | |
498 | EFIAPI\r | |
499 | PciExpressWrite16 (\r | |
500 | IN UINTN Address,\r | |
501 | IN UINT16 Value\r | |
502 | )\r | |
503 | {\r | |
504 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
505 | return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
506 | }\r | |
507 | \r | |
508 | /**\r | |
62991af2 | 509 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
e1f414b6 | 510 | a 16-bit value.\r |
511 | \r | |
512 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 513 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 514 | OrData, and writes the result to the 16-bit PCI configuration register\r |
515 | specified by Address. The value written to the PCI configuration register is\r | |
516 | returned. This function must guarantee that all PCI read and write operations\r | |
517 | are serialized.\r | |
518 | \r | |
519 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
520 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
521 | \r | |
2fc59a00 | 522 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 523 | Register.\r |
524 | @param OrData The value to OR with the PCI configuration register.\r | |
525 | \r | |
526 | @return The value written back to the PCI configuration register.\r | |
527 | \r | |
528 | **/\r | |
529 | UINT16\r | |
530 | EFIAPI\r | |
531 | PciExpressOr16 (\r | |
532 | IN UINTN Address,\r | |
533 | IN UINT16 OrData\r | |
534 | )\r | |
535 | {\r | |
536 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
537 | return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
538 | }\r | |
539 | \r | |
540 | /**\r | |
541 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
542 | value.\r | |
543 | \r | |
544 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
545 | bitwise AND between the read result and the value specified by AndData, and\r | |
546 | writes the result to the 16-bit PCI configuration register specified by\r | |
547 | Address. The value written to the PCI configuration register is returned.\r | |
548 | This function must guarantee that all PCI read and write operations are\r | |
549 | serialized.\r | |
550 | \r | |
551 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
552 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
553 | \r | |
2fc59a00 | 554 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 555 | Register.\r |
556 | @param AndData The value to AND with the PCI configuration register.\r | |
557 | \r | |
558 | @return The value written back to the PCI configuration register.\r | |
559 | \r | |
560 | **/\r | |
561 | UINT16\r | |
562 | EFIAPI\r | |
563 | PciExpressAnd16 (\r | |
564 | IN UINTN Address,\r | |
565 | IN UINT16 AndData\r | |
566 | )\r | |
567 | {\r | |
568 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
569 | return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
570 | }\r | |
571 | \r | |
572 | /**\r | |
573 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 574 | value, followed a bitwise OR with another 16-bit value.\r |
e1f414b6 | 575 | \r |
576 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
577 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 578 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 579 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
580 | configuration register specified by Address. The value written to the PCI\r | |
581 | configuration register is returned. This function must guarantee that all PCI\r | |
582 | read and write operations are serialized.\r | |
583 | \r | |
584 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
585 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
586 | \r | |
2fc59a00 | 587 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 588 | Register.\r |
589 | @param AndData The value to AND with the PCI configuration register.\r | |
590 | @param OrData The value to OR with the result of the AND operation.\r | |
591 | \r | |
592 | @return The value written back to the PCI configuration register.\r | |
593 | \r | |
594 | **/\r | |
595 | UINT16\r | |
596 | EFIAPI\r | |
597 | PciExpressAndThenOr16 (\r | |
598 | IN UINTN Address,\r | |
599 | IN UINT16 AndData,\r | |
600 | IN UINT16 OrData\r | |
601 | )\r | |
602 | {\r | |
603 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
604 | return MmioAndThenOr16 (\r | |
605 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
606 | AndData,\r | |
607 | OrData\r | |
608 | );\r | |
609 | }\r | |
610 | \r | |
611 | /**\r | |
612 | Reads a bit field of a PCI configuration register.\r | |
613 | \r | |
614 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
615 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
616 | returned.\r | |
617 | \r | |
618 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
619 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
620 | If StartBit is greater than 15, then ASSERT().\r | |
621 | If EndBit is greater than 15, then ASSERT().\r | |
622 | If EndBit is less than StartBit, then ASSERT().\r | |
623 | \r | |
2fc59a00 | 624 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 625 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
626 | Range 0..15.\r | |
627 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
628 | Range 0..15.\r | |
629 | \r | |
630 | @return The value of the bit field read from the PCI configuration register.\r | |
631 | \r | |
632 | **/\r | |
633 | UINT16\r | |
634 | EFIAPI\r | |
635 | PciExpressBitFieldRead16 (\r | |
636 | IN UINTN Address,\r | |
637 | IN UINTN StartBit,\r | |
638 | IN UINTN EndBit\r | |
639 | )\r | |
640 | {\r | |
641 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
642 | return MmioBitFieldRead16 (\r | |
643 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
644 | StartBit,\r | |
645 | EndBit\r | |
646 | );\r | |
647 | }\r | |
648 | \r | |
649 | /**\r | |
650 | Writes a bit field to a PCI configuration register.\r | |
651 | \r | |
652 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
653 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
654 | destination PCI configuration register are preserved. The new value of the\r | |
655 | 16-bit register is returned.\r | |
656 | \r | |
657 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
658 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
659 | If StartBit is greater than 15, then ASSERT().\r | |
660 | If EndBit is greater than 15, then ASSERT().\r | |
661 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 662 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 663 | \r |
2fc59a00 | 664 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 665 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
666 | Range 0..15.\r | |
667 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
668 | Range 0..15.\r | |
2fc59a00 | 669 | @param Value The new value of the bit field.\r |
e1f414b6 | 670 | \r |
671 | @return The value written back to the PCI configuration register.\r | |
672 | \r | |
673 | **/\r | |
674 | UINT16\r | |
675 | EFIAPI\r | |
676 | PciExpressBitFieldWrite16 (\r | |
677 | IN UINTN Address,\r | |
678 | IN UINTN StartBit,\r | |
679 | IN UINTN EndBit,\r | |
680 | IN UINT16 Value\r | |
681 | )\r | |
682 | {\r | |
683 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
684 | return MmioBitFieldWrite16 (\r | |
685 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
686 | StartBit,\r | |
687 | EndBit,\r | |
688 | Value\r | |
689 | );\r | |
690 | }\r | |
691 | \r | |
692 | /**\r | |
693 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
694 | writes the result back to the bit field in the 16-bit port.\r | |
695 | \r | |
696 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 697 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 698 | OrData, and writes the result to the 16-bit PCI configuration register\r |
699 | specified by Address. The value written to the PCI configuration register is\r | |
700 | returned. This function must guarantee that all PCI read and write operations\r | |
701 | are serialized. Extra left bits in OrData are stripped.\r | |
702 | \r | |
703 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
704 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
705 | If StartBit is greater than 15, then ASSERT().\r | |
706 | If EndBit is greater than 15, then ASSERT().\r | |
707 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 708 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 709 | \r |
2fc59a00 | 710 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 711 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
712 | Range 0..15.\r | |
713 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
714 | Range 0..15.\r | |
715 | @param OrData The value to OR with the PCI configuration register.\r | |
716 | \r | |
717 | @return The value written back to the PCI configuration register.\r | |
718 | \r | |
719 | **/\r | |
720 | UINT16\r | |
721 | EFIAPI\r | |
722 | PciExpressBitFieldOr16 (\r | |
723 | IN UINTN Address,\r | |
724 | IN UINTN StartBit,\r | |
725 | IN UINTN EndBit,\r | |
726 | IN UINT16 OrData\r | |
727 | )\r | |
728 | {\r | |
729 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
730 | return MmioBitFieldOr16 (\r | |
731 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
732 | StartBit,\r | |
733 | EndBit,\r | |
734 | OrData\r | |
735 | );\r | |
736 | }\r | |
737 | \r | |
738 | /**\r | |
739 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
740 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
741 | \r | |
742 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
743 | bitwise AND between the read result and the value specified by AndData, and\r | |
744 | writes the result to the 16-bit PCI configuration register specified by\r | |
745 | Address. The value written to the PCI configuration register is returned.\r | |
746 | This function must guarantee that all PCI read and write operations are\r | |
747 | serialized. Extra left bits in AndData are stripped.\r | |
748 | \r | |
749 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
750 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
751 | If StartBit is greater than 15, then ASSERT().\r | |
752 | If EndBit is greater than 15, then ASSERT().\r | |
753 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 754 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 755 | \r |
2fc59a00 | 756 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 757 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
758 | Range 0..15.\r | |
759 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
760 | Range 0..15.\r | |
761 | @param AndData The value to AND with the PCI configuration register.\r | |
762 | \r | |
763 | @return The value written back to the PCI configuration register.\r | |
764 | \r | |
765 | **/\r | |
766 | UINT16\r | |
767 | EFIAPI\r | |
768 | PciExpressBitFieldAnd16 (\r | |
769 | IN UINTN Address,\r | |
770 | IN UINTN StartBit,\r | |
771 | IN UINTN EndBit,\r | |
772 | IN UINT16 AndData\r | |
773 | )\r | |
774 | {\r | |
775 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
776 | return MmioBitFieldAnd16 (\r | |
777 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
778 | StartBit,\r | |
779 | EndBit,\r | |
780 | AndData\r | |
781 | );\r | |
782 | }\r | |
783 | \r | |
784 | /**\r | |
785 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 786 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 787 | 16-bit port.\r |
788 | \r | |
789 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 790 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 791 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
792 | configuration register specified by Address. The value written to the PCI\r | |
793 | configuration register is returned. This function must guarantee that all PCI\r | |
794 | read and write operations are serialized. Extra left bits in both AndData and\r | |
795 | OrData are stripped.\r | |
796 | \r | |
797 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
798 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
799 | If StartBit is greater than 15, then ASSERT().\r | |
800 | If EndBit is greater than 15, then ASSERT().\r | |
801 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
802 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
803 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 804 | \r |
2fc59a00 | 805 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 806 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
807 | Range 0..15.\r | |
808 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
809 | Range 0..15.\r | |
810 | @param AndData The value to AND with the PCI configuration register.\r | |
811 | @param OrData The value to OR with the result of the AND operation.\r | |
812 | \r | |
813 | @return The value written back to the PCI configuration register.\r | |
814 | \r | |
815 | **/\r | |
816 | UINT16\r | |
817 | EFIAPI\r | |
818 | PciExpressBitFieldAndThenOr16 (\r | |
819 | IN UINTN Address,\r | |
820 | IN UINTN StartBit,\r | |
821 | IN UINTN EndBit,\r | |
822 | IN UINT16 AndData,\r | |
823 | IN UINT16 OrData\r | |
824 | )\r | |
825 | {\r | |
826 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
827 | return MmioBitFieldAndThenOr16 (\r | |
828 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
829 | StartBit,\r | |
830 | EndBit,\r | |
831 | AndData,\r | |
832 | OrData\r | |
833 | );\r | |
834 | }\r | |
835 | \r | |
836 | /**\r | |
837 | Reads a 32-bit PCI configuration register.\r | |
838 | \r | |
839 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
840 | This function must guarantee that all PCI read and write operations are\r | |
841 | serialized.\r | |
842 | \r | |
843 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
844 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
845 | \r | |
2fc59a00 | 846 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 847 | Register.\r |
848 | \r | |
849 | @return The read value from the PCI configuration register.\r | |
850 | \r | |
851 | **/\r | |
852 | UINT32\r | |
853 | EFIAPI\r | |
854 | PciExpressRead32 (\r | |
855 | IN UINTN Address\r | |
856 | )\r | |
857 | {\r | |
858 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
859 | return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
860 | }\r | |
861 | \r | |
862 | /**\r | |
863 | Writes a 32-bit PCI configuration register.\r | |
864 | \r | |
865 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
866 | value specified by Value. Value is returned. This function must guarantee\r | |
867 | that all PCI read and write operations are serialized.\r | |
868 | \r | |
869 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
870 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
871 | \r | |
2fc59a00 | 872 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 873 | Register.\r |
874 | @param Value The value to write.\r | |
875 | \r | |
876 | @return The value written to the PCI configuration register.\r | |
877 | \r | |
878 | **/\r | |
879 | UINT32\r | |
880 | EFIAPI\r | |
881 | PciExpressWrite32 (\r | |
882 | IN UINTN Address,\r | |
883 | IN UINT32 Value\r | |
884 | )\r | |
885 | {\r | |
886 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
887 | return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
888 | }\r | |
889 | \r | |
890 | /**\r | |
62991af2 | 891 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
e1f414b6 | 892 | a 32-bit value.\r |
893 | \r | |
894 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 895 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 896 | OrData, and writes the result to the 32-bit PCI configuration register\r |
897 | specified by Address. The value written to the PCI configuration register is\r | |
898 | returned. This function must guarantee that all PCI read and write operations\r | |
899 | are serialized.\r | |
900 | \r | |
901 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
902 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
903 | \r | |
2fc59a00 | 904 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 905 | Register.\r |
906 | @param OrData The value to OR with the PCI configuration register.\r | |
907 | \r | |
908 | @return The value written back to the PCI configuration register.\r | |
909 | \r | |
910 | **/\r | |
911 | UINT32\r | |
912 | EFIAPI\r | |
913 | PciExpressOr32 (\r | |
914 | IN UINTN Address,\r | |
915 | IN UINT32 OrData\r | |
916 | )\r | |
917 | {\r | |
918 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
919 | return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
920 | }\r | |
921 | \r | |
922 | /**\r | |
923 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
924 | value.\r | |
925 | \r | |
926 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
927 | bitwise AND between the read result and the value specified by AndData, and\r | |
928 | writes the result to the 32-bit PCI configuration register specified by\r | |
929 | Address. The value written to the PCI configuration register is returned.\r | |
930 | This function must guarantee that all PCI read and write operations are\r | |
931 | serialized.\r | |
932 | \r | |
933 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
934 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
935 | \r | |
2fc59a00 | 936 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 937 | Register.\r |
938 | @param AndData The value to AND with the PCI configuration register.\r | |
939 | \r | |
940 | @return The value written back to the PCI configuration register.\r | |
941 | \r | |
942 | **/\r | |
943 | UINT32\r | |
944 | EFIAPI\r | |
945 | PciExpressAnd32 (\r | |
946 | IN UINTN Address,\r | |
947 | IN UINT32 AndData\r | |
948 | )\r | |
949 | {\r | |
950 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
951 | return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
952 | }\r | |
953 | \r | |
954 | /**\r | |
955 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 956 | value, followed a bitwise OR with another 32-bit value.\r |
e1f414b6 | 957 | \r |
958 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
959 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 960 | performs a bitwise OR between the result of the AND operation and\r |
e1f414b6 | 961 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
962 | configuration register specified by Address. The value written to the PCI\r | |
963 | configuration register is returned. This function must guarantee that all PCI\r | |
964 | read and write operations are serialized.\r | |
965 | \r | |
966 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
967 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
968 | \r | |
2fc59a00 | 969 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
e1f414b6 | 970 | Register.\r |
971 | @param AndData The value to AND with the PCI configuration register.\r | |
972 | @param OrData The value to OR with the result of the AND operation.\r | |
973 | \r | |
974 | @return The value written back to the PCI configuration register.\r | |
975 | \r | |
976 | **/\r | |
977 | UINT32\r | |
978 | EFIAPI\r | |
979 | PciExpressAndThenOr32 (\r | |
980 | IN UINTN Address,\r | |
981 | IN UINT32 AndData,\r | |
982 | IN UINT32 OrData\r | |
983 | )\r | |
984 | {\r | |
985 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
986 | return MmioAndThenOr32 (\r | |
987 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
988 | AndData,\r | |
989 | OrData\r | |
990 | );\r | |
991 | }\r | |
992 | \r | |
993 | /**\r | |
994 | Reads a bit field of a PCI configuration register.\r | |
995 | \r | |
996 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
997 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
998 | returned.\r | |
999 | \r | |
1000 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1001 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1002 | If StartBit is greater than 31, then ASSERT().\r | |
1003 | If EndBit is greater than 31, then ASSERT().\r | |
1004 | If EndBit is less than StartBit, then ASSERT().\r | |
1005 | \r | |
2fc59a00 | 1006 | @param Address The PCI configuration register to read.\r |
e1f414b6 | 1007 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1008 | Range 0..31.\r | |
1009 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1010 | Range 0..31.\r | |
1011 | \r | |
1012 | @return The value of the bit field read from the PCI configuration register.\r | |
1013 | \r | |
1014 | **/\r | |
1015 | UINT32\r | |
1016 | EFIAPI\r | |
1017 | PciExpressBitFieldRead32 (\r | |
1018 | IN UINTN Address,\r | |
1019 | IN UINTN StartBit,\r | |
1020 | IN UINTN EndBit\r | |
1021 | )\r | |
1022 | {\r | |
1023 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1024 | return MmioBitFieldRead32 (\r | |
1025 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1026 | StartBit,\r | |
1027 | EndBit\r | |
1028 | );\r | |
1029 | }\r | |
1030 | \r | |
1031 | /**\r | |
1032 | Writes a bit field to a PCI configuration register.\r | |
1033 | \r | |
1034 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1035 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1036 | destination PCI configuration register are preserved. The new value of the\r | |
1037 | 32-bit register is returned.\r | |
1038 | \r | |
1039 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1040 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1041 | If StartBit is greater than 31, then ASSERT().\r | |
1042 | If EndBit is greater than 31, then ASSERT().\r | |
1043 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1044 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 1045 | \r |
2fc59a00 | 1046 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1047 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1048 | Range 0..31.\r | |
1049 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1050 | Range 0..31.\r | |
2fc59a00 | 1051 | @param Value The new value of the bit field.\r |
e1f414b6 | 1052 | \r |
1053 | @return The value written back to the PCI configuration register.\r | |
1054 | \r | |
1055 | **/\r | |
1056 | UINT32\r | |
1057 | EFIAPI\r | |
1058 | PciExpressBitFieldWrite32 (\r | |
1059 | IN UINTN Address,\r | |
1060 | IN UINTN StartBit,\r | |
1061 | IN UINTN EndBit,\r | |
1062 | IN UINT32 Value\r | |
1063 | )\r | |
1064 | {\r | |
1065 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1066 | return MmioBitFieldWrite32 (\r | |
1067 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1068 | StartBit,\r | |
1069 | EndBit,\r | |
1070 | Value\r | |
1071 | );\r | |
1072 | }\r | |
1073 | \r | |
1074 | /**\r | |
1075 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1076 | writes the result back to the bit field in the 32-bit port.\r | |
1077 | \r | |
1078 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1079 | bitwise OR between the read result and the value specified by\r |
e1f414b6 | 1080 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1081 | specified by Address. The value written to the PCI configuration register is\r | |
1082 | returned. This function must guarantee that all PCI read and write operations\r | |
1083 | are serialized. Extra left bits in OrData are stripped.\r | |
1084 | \r | |
1085 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1086 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1087 | If StartBit is greater than 31, then ASSERT().\r | |
1088 | If EndBit is greater than 31, then ASSERT().\r | |
1089 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1090 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 1091 | \r |
2fc59a00 | 1092 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1093 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1094 | Range 0..31.\r | |
1095 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1096 | Range 0..31.\r | |
1097 | @param OrData The value to OR with the PCI configuration register.\r | |
1098 | \r | |
1099 | @return The value written back to the PCI configuration register.\r | |
1100 | \r | |
1101 | **/\r | |
1102 | UINT32\r | |
1103 | EFIAPI\r | |
1104 | PciExpressBitFieldOr32 (\r | |
1105 | IN UINTN Address,\r | |
1106 | IN UINTN StartBit,\r | |
1107 | IN UINTN EndBit,\r | |
1108 | IN UINT32 OrData\r | |
1109 | )\r | |
1110 | {\r | |
1111 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1112 | return MmioBitFieldOr32 (\r | |
1113 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1114 | StartBit,\r | |
1115 | EndBit,\r | |
1116 | OrData\r | |
1117 | );\r | |
1118 | }\r | |
1119 | \r | |
1120 | /**\r | |
1121 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1122 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1123 | \r | |
1124 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1125 | bitwise AND between the read result and the value specified by AndData, and\r | |
1126 | writes the result to the 32-bit PCI configuration register specified by\r | |
1127 | Address. The value written to the PCI configuration register is returned.\r | |
1128 | This function must guarantee that all PCI read and write operations are\r | |
1129 | serialized. Extra left bits in AndData are stripped.\r | |
1130 | \r | |
1131 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1132 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1133 | If StartBit is greater than 31, then ASSERT().\r | |
1134 | If EndBit is greater than 31, then ASSERT().\r | |
1135 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1136 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
e1f414b6 | 1137 | \r |
2fc59a00 | 1138 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1139 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1140 | Range 0..31.\r | |
1141 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1142 | Range 0..31.\r | |
1143 | @param AndData The value to AND with the PCI configuration register.\r | |
1144 | \r | |
1145 | @return The value written back to the PCI configuration register.\r | |
1146 | \r | |
1147 | **/\r | |
1148 | UINT32\r | |
1149 | EFIAPI\r | |
1150 | PciExpressBitFieldAnd32 (\r | |
1151 | IN UINTN Address,\r | |
1152 | IN UINTN StartBit,\r | |
1153 | IN UINTN EndBit,\r | |
1154 | IN UINT32 AndData\r | |
1155 | )\r | |
1156 | {\r | |
1157 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1158 | return MmioBitFieldAnd32 (\r | |
1159 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1160 | StartBit,\r | |
1161 | EndBit,\r | |
1162 | AndData\r | |
1163 | );\r | |
1164 | }\r | |
1165 | \r | |
1166 | /**\r | |
1167 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1168 | bitwise OR, and writes the result back to the bit field in the\r |
e1f414b6 | 1169 | 32-bit port.\r |
1170 | \r | |
1171 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1172 | bitwise AND followed by a bitwise OR between the read result and\r |
e1f414b6 | 1173 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1174 | configuration register specified by Address. The value written to the PCI\r | |
1175 | configuration register is returned. This function must guarantee that all PCI\r | |
1176 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1177 | OrData are stripped.\r | |
1178 | \r | |
1179 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1180 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1181 | If StartBit is greater than 31, then ASSERT().\r | |
1182 | If EndBit is greater than 31, then ASSERT().\r | |
1183 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1184 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1185 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
e1f414b6 | 1186 | \r |
2fc59a00 | 1187 | @param Address The PCI configuration register to write.\r |
e1f414b6 | 1188 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1189 | Range 0..31.\r | |
1190 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1191 | Range 0..31.\r | |
1192 | @param AndData The value to AND with the PCI configuration register.\r | |
1193 | @param OrData The value to OR with the result of the AND operation.\r | |
1194 | \r | |
1195 | @return The value written back to the PCI configuration register.\r | |
1196 | \r | |
1197 | **/\r | |
1198 | UINT32\r | |
1199 | EFIAPI\r | |
1200 | PciExpressBitFieldAndThenOr32 (\r | |
1201 | IN UINTN Address,\r | |
1202 | IN UINTN StartBit,\r | |
1203 | IN UINTN EndBit,\r | |
1204 | IN UINT32 AndData,\r | |
1205 | IN UINT32 OrData\r | |
1206 | )\r | |
1207 | {\r | |
1208 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1209 | return MmioBitFieldAndThenOr32 (\r | |
1210 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1211 | StartBit,\r | |
1212 | EndBit,\r | |
1213 | AndData,\r | |
1214 | OrData\r | |
1215 | );\r | |
1216 | }\r | |
1217 | \r | |
1218 | /**\r | |
1219 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1220 | \r | |
1221 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1222 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1223 | configuration registers from a single PCI function to be read. Size is\r | |
1224 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1225 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1226 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1227 | end of the range.\r | |
1228 | \r | |
1229 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1230 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1231 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1232 | \r | |
2fc59a00 | 1233 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1234 | Function and Register.\r |
2fc59a00 | 1235 | @param Size The size in bytes of the transfer.\r |
1236 | @param Buffer The pointer to a buffer receiving the data read.\r | |
e1f414b6 | 1237 | \r |
9638ba6d | 1238 | @return Size read data from StartAddress.\r |
e1f414b6 | 1239 | \r |
1240 | **/\r | |
1241 | UINTN\r | |
1242 | EFIAPI\r | |
1243 | PciExpressReadBuffer (\r | |
1244 | IN UINTN StartAddress,\r | |
1245 | IN UINTN Size,\r | |
1246 | OUT VOID *Buffer\r | |
1247 | )\r | |
1248 | {\r | |
0c62737d | 1249 | UINTN ReturnValue;\r |
e1f414b6 | 1250 | \r |
1251 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1252 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1253 | \r | |
1254 | if (Size == 0) {\r | |
1255 | return Size;\r | |
1256 | }\r | |
1257 | \r | |
1258 | ASSERT (Buffer != NULL);\r | |
1259 | \r | |
1260 | //\r | |
1261 | // Save Size for return\r | |
1262 | //\r | |
1263 | ReturnValue = Size;\r | |
1264 | \r | |
1265 | if ((StartAddress & 1) != 0) {\r | |
1266 | //\r | |
1267 | // Read a byte if StartAddress is byte aligned\r | |
1268 | //\r | |
1269 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1270 | StartAddress += sizeof (UINT8);\r | |
1271 | Size -= sizeof (UINT8);\r | |
1272 | Buffer = (UINT8*)Buffer + 1;\r | |
1273 | }\r | |
1274 | \r | |
1275 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1276 | //\r | |
1277 | // Read a word if StartAddress is word aligned\r | |
1278 | //\r | |
af2bb549 | 1279 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r |
0c62737d | 1280 | \r |
e1f414b6 | 1281 | StartAddress += sizeof (UINT16);\r |
1282 | Size -= sizeof (UINT16);\r | |
1283 | Buffer = (UINT16*)Buffer + 1;\r | |
1284 | }\r | |
1285 | \r | |
1286 | while (Size >= sizeof (UINT32)) {\r | |
1287 | //\r | |
1288 | // Read as many double words as possible\r | |
1289 | //\r | |
af2bb549 | 1290 | WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r |
0c62737d | 1291 | \r |
e1f414b6 | 1292 | StartAddress += sizeof (UINT32);\r |
1293 | Size -= sizeof (UINT32);\r | |
1294 | Buffer = (UINT32*)Buffer + 1;\r | |
1295 | }\r | |
1296 | \r | |
1297 | if (Size >= sizeof (UINT16)) {\r | |
1298 | //\r | |
1299 | // Read the last remaining word if exist\r | |
1300 | //\r | |
af2bb549 | 1301 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r |
e1f414b6 | 1302 | StartAddress += sizeof (UINT16);\r |
1303 | Size -= sizeof (UINT16);\r | |
1304 | Buffer = (UINT16*)Buffer + 1;\r | |
1305 | }\r | |
1306 | \r | |
1307 | if (Size >= sizeof (UINT8)) {\r | |
1308 | //\r | |
1309 | // Read the last remaining byte if exist\r | |
1310 | //\r | |
1311 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1312 | }\r | |
1313 | \r | |
1314 | return ReturnValue;\r | |
1315 | }\r | |
1316 | \r | |
1317 | /**\r | |
1318 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1319 | configuration space.\r | |
1320 | \r | |
1321 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1322 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1323 | configuration registers from a single PCI function to be written. Size is\r | |
1324 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1325 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1326 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1327 | and the end of the range.\r | |
1328 | \r | |
1329 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1330 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1331 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1332 | \r | |
2fc59a00 | 1333 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
e1f414b6 | 1334 | Function and Register.\r |
2fc59a00 | 1335 | @param Size The size in bytes of the transfer.\r |
1336 | @param Buffer The pointer to a buffer containing the data to write.\r | |
e1f414b6 | 1337 | \r |
9638ba6d | 1338 | @return Size written to StartAddress.\r |
e1f414b6 | 1339 | \r |
1340 | **/\r | |
1341 | UINTN\r | |
1342 | EFIAPI\r | |
1343 | PciExpressWriteBuffer (\r | |
1344 | IN UINTN StartAddress,\r | |
1345 | IN UINTN Size,\r | |
1346 | IN VOID *Buffer\r | |
1347 | )\r | |
1348 | {\r | |
1349 | UINTN ReturnValue;\r | |
1350 | \r | |
1351 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1352 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1353 | \r | |
1354 | if (Size == 0) {\r | |
1355 | return 0;\r | |
1356 | }\r | |
1357 | \r | |
1358 | ASSERT (Buffer != NULL);\r | |
1359 | \r | |
1360 | //\r | |
1361 | // Save Size for return\r | |
1362 | //\r | |
1363 | ReturnValue = Size;\r | |
1364 | \r | |
1365 | if ((StartAddress & 1) != 0) {\r | |
1366 | //\r | |
1367 | // Write a byte if StartAddress is byte aligned\r | |
1368 | //\r | |
1369 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1370 | StartAddress += sizeof (UINT8);\r | |
1371 | Size -= sizeof (UINT8);\r | |
1372 | Buffer = (UINT8*)Buffer + 1;\r | |
1373 | }\r | |
1374 | \r | |
1375 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1376 | //\r | |
1377 | // Write a word if StartAddress is word aligned\r | |
1378 | //\r | |
0c62737d | 1379 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r |
e1f414b6 | 1380 | StartAddress += sizeof (UINT16);\r |
1381 | Size -= sizeof (UINT16);\r | |
1382 | Buffer = (UINT16*)Buffer + 1;\r | |
1383 | }\r | |
1384 | \r | |
1385 | while (Size >= sizeof (UINT32)) {\r | |
1386 | //\r | |
1387 | // Write as many double words as possible\r | |
1388 | //\r | |
0c62737d | 1389 | PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r |
e1f414b6 | 1390 | StartAddress += sizeof (UINT32);\r |
1391 | Size -= sizeof (UINT32);\r | |
1392 | Buffer = (UINT32*)Buffer + 1;\r | |
1393 | }\r | |
1394 | \r | |
1395 | if (Size >= sizeof (UINT16)) {\r | |
1396 | //\r | |
1397 | // Write the last remaining word if exist\r | |
1398 | //\r | |
0c62737d | 1399 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r |
e1f414b6 | 1400 | StartAddress += sizeof (UINT16);\r |
1401 | Size -= sizeof (UINT16);\r | |
1402 | Buffer = (UINT16*)Buffer + 1;\r | |
1403 | }\r | |
1404 | \r | |
1405 | if (Size >= sizeof (UINT8)) {\r | |
1406 | //\r | |
1407 | // Write the last remaining byte if exist\r | |
1408 | //\r | |
1409 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1410 | }\r | |
1411 | \r | |
1412 | return ReturnValue;\r | |
1413 | }\r |