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878ddf1f | 1 | /** @file\r |
2 | PCI Library.\r | |
3 | \r | |
4 | Functions in this library instance make use of MMIO functions in IoLib to\r | |
5 | access memory mapped PCI configuration space.\r | |
6 | \r | |
7 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r | |
8 | Library.\r | |
9 | \r | |
10 | Copyright (c) 2006, Intel Corporation<BR>\r | |
11 | All rights reserved. This program and the accompanying materials\r | |
12 | are licensed and made available under the terms and conditions of the BSD License\r | |
13 | which accompanies this distribution. The full text of the license may be found at\r | |
14 | http://opensource.org/licenses/bsd-license.php\r | |
15 | \r | |
16 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
17 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
18 | \r | |
19 | Module Name: PciLib.c\r | |
20 | \r | |
21 | **/\r | |
22 | \r | |
23 | /**\r | |
24 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
25 | only in the low 28 bits.\r | |
26 | \r | |
27 | @param A The address to validate.\r | |
28 | \r | |
29 | **/\r | |
30 | #define ASSERT_INVALID_PCI_ADDRESS(A) \\r | |
31 | ASSERT (((A) & ~0xfffffff) == 0)\r | |
32 | \r | |
33 | \r | |
1f33a17f | 34 | /**\r |
35 | Gets the base address of PCI Express.\r | |
36 | \r | |
37 | This internal functions retrieves PCI Express Base Address via a PCD entry\r | |
38 | PcdPciExpressBaseAddress.\r | |
39 | \r | |
40 | @return The base address of PCI Express.\r | |
41 | \r | |
42 | **/\r | |
58251024 | 43 | STATIC\r |
aa0dc7b4 | 44 | volatile VOID*\r |
878ddf1f | 45 | GetPciExpressBaseAddress (\r |
46 | VOID\r | |
47 | )\r | |
48 | {\r | |
aa0dc7b4 | 49 | return (VOID*)(UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r |
878ddf1f | 50 | }\r |
51 | \r | |
52 | /**\r | |
53 | Reads an 8-bit PCI configuration register.\r | |
54 | \r | |
55 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
56 | This function must guarantee that all PCI read and write operations are\r | |
57 | serialized.\r | |
58 | \r | |
59 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
60 | \r | |
61 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
62 | Register.\r | |
63 | \r | |
64 | @return The read value from the PCI configuration register.\r | |
65 | \r | |
66 | **/\r | |
67 | UINT8\r | |
68 | EFIAPI\r | |
69 | PciExpressRead8 (\r | |
70 | IN UINTN Address\r | |
71 | )\r | |
72 | {\r | |
73 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 74 | return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);\r |
878ddf1f | 75 | }\r |
76 | \r | |
77 | /**\r | |
78 | Writes an 8-bit PCI configuration register.\r | |
79 | \r | |
80 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
81 | value specified by Value. Value is returned. This function must guarantee\r | |
82 | that all PCI read and write operations are serialized.\r | |
83 | \r | |
84 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
85 | \r | |
86 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
87 | Register.\r | |
88 | @param Value The value to write.\r | |
89 | \r | |
90 | @return The value written to the PCI configuration register.\r | |
91 | \r | |
92 | **/\r | |
93 | UINT8\r | |
94 | EFIAPI\r | |
95 | PciExpressWrite8 (\r | |
96 | IN UINTN Address,\r | |
97 | IN UINT8 Value\r | |
98 | )\r | |
99 | {\r | |
100 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 101 | return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r |
878ddf1f | 102 | }\r |
103 | \r | |
104 | /**\r | |
105 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
106 | an 8-bit value.\r | |
107 | \r | |
108 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
109 | bitwise inclusive OR between the read result and the value specified by\r | |
110 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
111 | specified by Address. The value written to the PCI configuration register is\r | |
112 | returned. This function must guarantee that all PCI read and write operations\r | |
113 | are serialized.\r | |
114 | \r | |
115 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
116 | \r | |
117 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
118 | Register.\r | |
119 | @param OrData The value to OR with the PCI configuration register.\r | |
120 | \r | |
121 | @return The value written back to the PCI configuration register.\r | |
122 | \r | |
123 | **/\r | |
124 | UINT8\r | |
125 | EFIAPI\r | |
126 | PciExpressOr8 (\r | |
127 | IN UINTN Address,\r | |
128 | IN UINT8 OrData\r | |
129 | )\r | |
130 | {\r | |
131 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 132 | return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r |
878ddf1f | 133 | }\r |
134 | \r | |
135 | /**\r | |
136 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
137 | value.\r | |
138 | \r | |
139 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
140 | bitwise AND between the read result and the value specified by AndData, and\r | |
141 | writes the result to the 8-bit PCI configuration register specified by\r | |
142 | Address. The value written to the PCI configuration register is returned.\r | |
143 | This function must guarantee that all PCI read and write operations are\r | |
144 | serialized.\r | |
145 | \r | |
146 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
147 | \r | |
148 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
149 | Register.\r | |
150 | @param AndData The value to AND with the PCI configuration register.\r | |
151 | \r | |
152 | @return The value written back to the PCI configuration register.\r | |
153 | \r | |
154 | **/\r | |
155 | UINT8\r | |
156 | EFIAPI\r | |
157 | PciExpressAnd8 (\r | |
158 | IN UINTN Address,\r | |
159 | IN UINT8 AndData\r | |
160 | )\r | |
161 | {\r | |
162 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 163 | return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r |
878ddf1f | 164 | }\r |
165 | \r | |
166 | /**\r | |
167 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
168 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
169 | \r | |
170 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
171 | bitwise AND between the read result and the value specified by AndData,\r | |
172 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
173 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
174 | configuration register specified by Address. The value written to the PCI\r | |
175 | configuration register is returned. This function must guarantee that all PCI\r | |
176 | read and write operations are serialized.\r | |
177 | \r | |
178 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
179 | \r | |
180 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
181 | Register.\r | |
182 | @param AndData The value to AND with the PCI configuration register.\r | |
183 | @param OrData The value to OR with the result of the AND operation.\r | |
184 | \r | |
185 | @return The value written back to the PCI configuration register.\r | |
186 | \r | |
187 | **/\r | |
188 | UINT8\r | |
189 | EFIAPI\r | |
190 | PciExpressAndThenOr8 (\r | |
191 | IN UINTN Address,\r | |
192 | IN UINT8 AndData,\r | |
193 | IN UINT8 OrData\r | |
194 | )\r | |
195 | {\r | |
196 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
197 | return MmioAndThenOr8 (\r | |
aa0dc7b4 | 198 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 199 | AndData,\r |
200 | OrData\r | |
201 | );\r | |
202 | }\r | |
203 | \r | |
204 | /**\r | |
205 | Reads a bit field of a PCI configuration register.\r | |
206 | \r | |
207 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
208 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
209 | returned.\r | |
210 | \r | |
211 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
212 | If StartBit is greater than 7, then ASSERT().\r | |
213 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 214 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 215 | \r |
216 | @param Address PCI configuration register to read.\r | |
217 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
218 | Range 0..7.\r | |
219 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
220 | Range 0..7.\r | |
221 | \r | |
222 | @return The value of the bit field read from the PCI configuration register.\r | |
223 | \r | |
224 | **/\r | |
225 | UINT8\r | |
226 | EFIAPI\r | |
227 | PciExpressBitFieldRead8 (\r | |
228 | IN UINTN Address,\r | |
229 | IN UINTN StartBit,\r | |
230 | IN UINTN EndBit\r | |
231 | )\r | |
232 | {\r | |
233 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
234 | return MmioBitFieldRead8 (\r | |
aa0dc7b4 | 235 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 236 | StartBit,\r |
237 | EndBit\r | |
238 | );\r | |
239 | }\r | |
240 | \r | |
241 | /**\r | |
242 | Writes a bit field to a PCI configuration register.\r | |
243 | \r | |
244 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
245 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
246 | destination PCI configuration register are preserved. The new value of the\r | |
247 | 8-bit register is returned.\r | |
248 | \r | |
249 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
250 | If StartBit is greater than 7, then ASSERT().\r | |
251 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 252 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 253 | \r |
254 | @param Address PCI configuration register to write.\r | |
255 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
256 | Range 0..7.\r | |
257 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
258 | Range 0..7.\r | |
259 | @param Value New value of the bit field.\r | |
260 | \r | |
261 | @return The value written back to the PCI configuration register.\r | |
262 | \r | |
263 | **/\r | |
264 | UINT8\r | |
265 | EFIAPI\r | |
266 | PciExpressBitFieldWrite8 (\r | |
267 | IN UINTN Address,\r | |
268 | IN UINTN StartBit,\r | |
269 | IN UINTN EndBit,\r | |
270 | IN UINT8 Value\r | |
271 | )\r | |
272 | {\r | |
273 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
274 | return MmioBitFieldWrite8 (\r | |
aa0dc7b4 | 275 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 276 | StartBit,\r |
277 | EndBit,\r | |
278 | Value\r | |
279 | );\r | |
280 | }\r | |
281 | \r | |
282 | /**\r | |
283 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
284 | writes the result back to the bit field in the 8-bit port.\r | |
285 | \r | |
286 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
287 | bitwise inclusive OR between the read result and the value specified by\r | |
288 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
289 | specified by Address. The value written to the PCI configuration register is\r | |
290 | returned. This function must guarantee that all PCI read and write operations\r | |
291 | are serialized. Extra left bits in OrData are stripped.\r | |
292 | \r | |
293 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
294 | If StartBit is greater than 7, then ASSERT().\r | |
295 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 296 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 297 | \r |
298 | @param Address PCI configuration register to write.\r | |
299 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
300 | Range 0..7.\r | |
301 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
302 | Range 0..7.\r | |
303 | @param OrData The value to OR with the PCI configuration register.\r | |
304 | \r | |
305 | @return The value written back to the PCI configuration register.\r | |
306 | \r | |
307 | **/\r | |
308 | UINT8\r | |
309 | EFIAPI\r | |
310 | PciExpressBitFieldOr8 (\r | |
311 | IN UINTN Address,\r | |
312 | IN UINTN StartBit,\r | |
313 | IN UINTN EndBit,\r | |
314 | IN UINT8 OrData\r | |
315 | )\r | |
316 | {\r | |
317 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
318 | return MmioBitFieldOr8 (\r | |
aa0dc7b4 | 319 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 320 | StartBit,\r |
321 | EndBit,\r | |
322 | OrData\r | |
323 | );\r | |
324 | }\r | |
325 | \r | |
326 | /**\r | |
327 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
328 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
329 | \r | |
330 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
331 | bitwise AND between the read result and the value specified by AndData, and\r | |
332 | writes the result to the 8-bit PCI configuration register specified by\r | |
333 | Address. The value written to the PCI configuration register is returned.\r | |
334 | This function must guarantee that all PCI read and write operations are\r | |
335 | serialized. Extra left bits in AndData are stripped.\r | |
336 | \r | |
337 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
338 | If StartBit is greater than 7, then ASSERT().\r | |
339 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 340 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 341 | \r |
342 | @param Address PCI configuration register to write.\r | |
343 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
344 | Range 0..7.\r | |
345 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
346 | Range 0..7.\r | |
347 | @param AndData The value to AND with the PCI configuration register.\r | |
348 | \r | |
349 | @return The value written back to the PCI configuration register.\r | |
350 | \r | |
351 | **/\r | |
352 | UINT8\r | |
353 | EFIAPI\r | |
354 | PciExpressBitFieldAnd8 (\r | |
355 | IN UINTN Address,\r | |
356 | IN UINTN StartBit,\r | |
357 | IN UINTN EndBit,\r | |
358 | IN UINT8 AndData\r | |
359 | )\r | |
360 | {\r | |
361 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
362 | return MmioBitFieldAnd8 (\r | |
aa0dc7b4 | 363 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 364 | StartBit,\r |
365 | EndBit,\r | |
366 | AndData\r | |
367 | );\r | |
368 | }\r | |
369 | \r | |
370 | /**\r | |
371 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
372 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
373 | 8-bit port.\r | |
374 | \r | |
375 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
376 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
377 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
378 | configuration register specified by Address. The value written to the PCI\r | |
379 | configuration register is returned. This function must guarantee that all PCI\r | |
380 | read and write operations are serialized. Extra left bits in both AndData and\r | |
381 | OrData are stripped.\r | |
382 | \r | |
383 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
384 | If StartBit is greater than 7, then ASSERT().\r | |
385 | If EndBit is greater than 7, then ASSERT().\r | |
0ffa1286 | 386 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 387 | \r |
388 | @param Address PCI configuration register to write.\r | |
389 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
390 | Range 0..7.\r | |
391 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
392 | Range 0..7.\r | |
393 | @param AndData The value to AND with the PCI configuration register.\r | |
394 | @param OrData The value to OR with the result of the AND operation.\r | |
395 | \r | |
396 | @return The value written back to the PCI configuration register.\r | |
397 | \r | |
398 | **/\r | |
399 | UINT8\r | |
400 | EFIAPI\r | |
401 | PciExpressBitFieldAndThenOr8 (\r | |
402 | IN UINTN Address,\r | |
403 | IN UINTN StartBit,\r | |
404 | IN UINTN EndBit,\r | |
405 | IN UINT8 AndData,\r | |
406 | IN UINT8 OrData\r | |
407 | )\r | |
408 | {\r | |
409 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
410 | return MmioBitFieldAndThenOr8 (\r | |
aa0dc7b4 | 411 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 412 | StartBit,\r |
413 | EndBit,\r | |
414 | AndData,\r | |
415 | OrData\r | |
416 | );\r | |
417 | }\r | |
418 | \r | |
419 | /**\r | |
420 | Reads a 16-bit PCI configuration register.\r | |
421 | \r | |
422 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
423 | This function must guarantee that all PCI read and write operations are\r | |
424 | serialized.\r | |
425 | \r | |
426 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
427 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
428 | \r | |
429 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
430 | Register.\r | |
431 | \r | |
432 | @return The read value from the PCI configuration register.\r | |
433 | \r | |
434 | **/\r | |
435 | UINT16\r | |
436 | EFIAPI\r | |
437 | PciExpressRead16 (\r | |
438 | IN UINTN Address\r | |
439 | )\r | |
440 | {\r | |
441 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 442 | return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);\r |
878ddf1f | 443 | }\r |
444 | \r | |
445 | /**\r | |
446 | Writes a 16-bit PCI configuration register.\r | |
447 | \r | |
448 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
449 | value specified by Value. Value is returned. This function must guarantee\r | |
450 | that all PCI read and write operations are serialized.\r | |
451 | \r | |
452 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
453 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
454 | \r | |
455 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
456 | Register.\r | |
457 | @param Value The value to write.\r | |
458 | \r | |
459 | @return The value written to the PCI configuration register.\r | |
460 | \r | |
461 | **/\r | |
462 | UINT16\r | |
463 | EFIAPI\r | |
464 | PciExpressWrite16 (\r | |
465 | IN UINTN Address,\r | |
466 | IN UINT16 Value\r | |
467 | )\r | |
468 | {\r | |
469 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 470 | return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r |
878ddf1f | 471 | }\r |
472 | \r | |
473 | /**\r | |
474 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
475 | a 16-bit value.\r | |
476 | \r | |
477 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
478 | bitwise inclusive OR between the read result and the value specified by\r | |
479 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
480 | specified by Address. The value written to the PCI configuration register is\r | |
481 | returned. This function must guarantee that all PCI read and write operations\r | |
482 | are serialized.\r | |
483 | \r | |
484 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
485 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
486 | \r | |
487 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
488 | Register.\r | |
489 | @param OrData The value to OR with the PCI configuration register.\r | |
490 | \r | |
491 | @return The value written back to the PCI configuration register.\r | |
492 | \r | |
493 | **/\r | |
494 | UINT16\r | |
495 | EFIAPI\r | |
496 | PciExpressOr16 (\r | |
497 | IN UINTN Address,\r | |
498 | IN UINT16 OrData\r | |
499 | )\r | |
500 | {\r | |
501 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 502 | return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r |
878ddf1f | 503 | }\r |
504 | \r | |
505 | /**\r | |
506 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
507 | value.\r | |
508 | \r | |
509 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
510 | bitwise AND between the read result and the value specified by AndData, and\r | |
511 | writes the result to the 16-bit PCI configuration register specified by\r | |
512 | Address. The value written to the PCI configuration register is returned.\r | |
513 | This function must guarantee that all PCI read and write operations are\r | |
514 | serialized.\r | |
515 | \r | |
516 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
517 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
518 | \r | |
519 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
520 | Register.\r | |
521 | @param AndData The value to AND with the PCI configuration register.\r | |
522 | \r | |
523 | @return The value written back to the PCI configuration register.\r | |
524 | \r | |
525 | **/\r | |
526 | UINT16\r | |
527 | EFIAPI\r | |
528 | PciExpressAnd16 (\r | |
529 | IN UINTN Address,\r | |
530 | IN UINT16 AndData\r | |
531 | )\r | |
532 | {\r | |
533 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 534 | return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r |
878ddf1f | 535 | }\r |
536 | \r | |
537 | /**\r | |
538 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
539 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
540 | \r | |
541 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
542 | bitwise AND between the read result and the value specified by AndData,\r | |
543 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
544 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
545 | configuration register specified by Address. The value written to the PCI\r | |
546 | configuration register is returned. This function must guarantee that all PCI\r | |
547 | read and write operations are serialized.\r | |
548 | \r | |
549 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
550 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
551 | \r | |
552 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
553 | Register.\r | |
554 | @param AndData The value to AND with the PCI configuration register.\r | |
555 | @param OrData The value to OR with the result of the AND operation.\r | |
556 | \r | |
557 | @return The value written back to the PCI configuration register.\r | |
558 | \r | |
559 | **/\r | |
560 | UINT16\r | |
561 | EFIAPI\r | |
562 | PciExpressAndThenOr16 (\r | |
563 | IN UINTN Address,\r | |
564 | IN UINT16 AndData,\r | |
565 | IN UINT16 OrData\r | |
566 | )\r | |
567 | {\r | |
568 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
569 | return MmioAndThenOr16 (\r | |
aa0dc7b4 | 570 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 571 | AndData,\r |
572 | OrData\r | |
573 | );\r | |
574 | }\r | |
575 | \r | |
576 | /**\r | |
577 | Reads a bit field of a PCI configuration register.\r | |
578 | \r | |
579 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
580 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
581 | returned.\r | |
582 | \r | |
583 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
584 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
585 | If StartBit is greater than 15, then ASSERT().\r | |
586 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 587 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 588 | \r |
589 | @param Address PCI configuration register to read.\r | |
590 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
591 | Range 0..15.\r | |
592 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
593 | Range 0..15.\r | |
594 | \r | |
595 | @return The value of the bit field read from the PCI configuration register.\r | |
596 | \r | |
597 | **/\r | |
598 | UINT16\r | |
599 | EFIAPI\r | |
600 | PciExpressBitFieldRead16 (\r | |
601 | IN UINTN Address,\r | |
602 | IN UINTN StartBit,\r | |
603 | IN UINTN EndBit\r | |
604 | )\r | |
605 | {\r | |
606 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
607 | return MmioBitFieldRead16 (\r | |
aa0dc7b4 | 608 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 609 | StartBit,\r |
610 | EndBit\r | |
611 | );\r | |
612 | }\r | |
613 | \r | |
614 | /**\r | |
615 | Writes a bit field to a PCI configuration register.\r | |
616 | \r | |
617 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
618 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
619 | destination PCI configuration register are preserved. The new value of the\r | |
620 | 16-bit register is returned.\r | |
621 | \r | |
622 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
623 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
624 | If StartBit is greater than 15, then ASSERT().\r | |
625 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 626 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 627 | \r |
628 | @param Address PCI configuration register to write.\r | |
629 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
630 | Range 0..15.\r | |
631 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
632 | Range 0..15.\r | |
633 | @param Value New value of the bit field.\r | |
634 | \r | |
635 | @return The value written back to the PCI configuration register.\r | |
636 | \r | |
637 | **/\r | |
638 | UINT16\r | |
639 | EFIAPI\r | |
640 | PciExpressBitFieldWrite16 (\r | |
641 | IN UINTN Address,\r | |
642 | IN UINTN StartBit,\r | |
643 | IN UINTN EndBit,\r | |
644 | IN UINT16 Value\r | |
645 | )\r | |
646 | {\r | |
647 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
648 | return MmioBitFieldWrite16 (\r | |
aa0dc7b4 | 649 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 650 | StartBit,\r |
651 | EndBit,\r | |
652 | Value\r | |
653 | );\r | |
654 | }\r | |
655 | \r | |
656 | /**\r | |
657 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
658 | writes the result back to the bit field in the 16-bit port.\r | |
659 | \r | |
660 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
661 | bitwise inclusive OR between the read result and the value specified by\r | |
662 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
663 | specified by Address. The value written to the PCI configuration register is\r | |
664 | returned. This function must guarantee that all PCI read and write operations\r | |
665 | are serialized. Extra left bits in OrData are stripped.\r | |
666 | \r | |
667 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
668 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
669 | If StartBit is greater than 15, then ASSERT().\r | |
670 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 671 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 672 | \r |
673 | @param Address PCI configuration register to write.\r | |
674 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
675 | Range 0..15.\r | |
676 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
677 | Range 0..15.\r | |
678 | @param OrData The value to OR with the PCI configuration register.\r | |
679 | \r | |
680 | @return The value written back to the PCI configuration register.\r | |
681 | \r | |
682 | **/\r | |
683 | UINT16\r | |
684 | EFIAPI\r | |
685 | PciExpressBitFieldOr16 (\r | |
686 | IN UINTN Address,\r | |
687 | IN UINTN StartBit,\r | |
688 | IN UINTN EndBit,\r | |
689 | IN UINT16 OrData\r | |
690 | )\r | |
691 | {\r | |
692 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
693 | return MmioBitFieldOr16 (\r | |
aa0dc7b4 | 694 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 695 | StartBit,\r |
696 | EndBit,\r | |
697 | OrData\r | |
698 | );\r | |
699 | }\r | |
700 | \r | |
701 | /**\r | |
702 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
703 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
704 | \r | |
705 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
706 | bitwise AND between the read result and the value specified by AndData, and\r | |
707 | writes the result to the 16-bit PCI configuration register specified by\r | |
708 | Address. The value written to the PCI configuration register is returned.\r | |
709 | This function must guarantee that all PCI read and write operations are\r | |
710 | serialized. Extra left bits in AndData are stripped.\r | |
711 | \r | |
712 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
713 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
714 | If StartBit is greater than 15, then ASSERT().\r | |
715 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 716 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 717 | \r |
718 | @param Address PCI configuration register to write.\r | |
719 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
720 | Range 0..15.\r | |
721 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
722 | Range 0..15.\r | |
723 | @param AndData The value to AND with the PCI configuration register.\r | |
724 | \r | |
725 | @return The value written back to the PCI configuration register.\r | |
726 | \r | |
727 | **/\r | |
728 | UINT16\r | |
729 | EFIAPI\r | |
730 | PciExpressBitFieldAnd16 (\r | |
731 | IN UINTN Address,\r | |
732 | IN UINTN StartBit,\r | |
733 | IN UINTN EndBit,\r | |
734 | IN UINT16 AndData\r | |
735 | )\r | |
736 | {\r | |
737 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
738 | return MmioBitFieldAnd16 (\r | |
aa0dc7b4 | 739 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 740 | StartBit,\r |
741 | EndBit,\r | |
742 | AndData\r | |
743 | );\r | |
744 | }\r | |
745 | \r | |
746 | /**\r | |
747 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
748 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
749 | 16-bit port.\r | |
750 | \r | |
751 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
752 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
753 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
754 | configuration register specified by Address. The value written to the PCI\r | |
755 | configuration register is returned. This function must guarantee that all PCI\r | |
756 | read and write operations are serialized. Extra left bits in both AndData and\r | |
757 | OrData are stripped.\r | |
758 | \r | |
759 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
760 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
761 | If StartBit is greater than 15, then ASSERT().\r | |
762 | If EndBit is greater than 15, then ASSERT().\r | |
0ffa1286 | 763 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 764 | \r |
765 | @param Address PCI configuration register to write.\r | |
766 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
767 | Range 0..15.\r | |
768 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
769 | Range 0..15.\r | |
770 | @param AndData The value to AND with the PCI configuration register.\r | |
771 | @param OrData The value to OR with the result of the AND operation.\r | |
772 | \r | |
773 | @return The value written back to the PCI configuration register.\r | |
774 | \r | |
775 | **/\r | |
776 | UINT16\r | |
777 | EFIAPI\r | |
778 | PciExpressBitFieldAndThenOr16 (\r | |
779 | IN UINTN Address,\r | |
780 | IN UINTN StartBit,\r | |
781 | IN UINTN EndBit,\r | |
782 | IN UINT16 AndData,\r | |
783 | IN UINT16 OrData\r | |
784 | )\r | |
785 | {\r | |
786 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
787 | return MmioBitFieldAndThenOr16 (\r | |
aa0dc7b4 | 788 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 789 | StartBit,\r |
790 | EndBit,\r | |
791 | AndData,\r | |
792 | OrData\r | |
793 | );\r | |
794 | }\r | |
795 | \r | |
796 | /**\r | |
797 | Reads a 32-bit PCI configuration register.\r | |
798 | \r | |
799 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
800 | This function must guarantee that all PCI read and write operations are\r | |
801 | serialized.\r | |
802 | \r | |
803 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
804 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
805 | \r | |
806 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
807 | Register.\r | |
808 | \r | |
809 | @return The read value from the PCI configuration register.\r | |
810 | \r | |
811 | **/\r | |
812 | UINT32\r | |
813 | EFIAPI\r | |
814 | PciExpressRead32 (\r | |
815 | IN UINTN Address\r | |
816 | )\r | |
817 | {\r | |
818 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 819 | return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);\r |
878ddf1f | 820 | }\r |
821 | \r | |
822 | /**\r | |
823 | Writes a 32-bit PCI configuration register.\r | |
824 | \r | |
825 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
826 | value specified by Value. Value is returned. This function must guarantee\r | |
827 | that all PCI read and write operations are serialized.\r | |
828 | \r | |
829 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
830 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
831 | \r | |
832 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
833 | Register.\r | |
834 | @param Value The value to write.\r | |
835 | \r | |
836 | @return The value written to the PCI configuration register.\r | |
837 | \r | |
838 | **/\r | |
839 | UINT32\r | |
840 | EFIAPI\r | |
841 | PciExpressWrite32 (\r | |
842 | IN UINTN Address,\r | |
843 | IN UINT32 Value\r | |
844 | )\r | |
845 | {\r | |
846 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 847 | return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r |
878ddf1f | 848 | }\r |
849 | \r | |
850 | /**\r | |
851 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
852 | a 32-bit value.\r | |
853 | \r | |
854 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
855 | bitwise inclusive OR between the read result and the value specified by\r | |
856 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
857 | specified by Address. The value written to the PCI configuration register is\r | |
858 | returned. This function must guarantee that all PCI read and write operations\r | |
859 | are serialized.\r | |
860 | \r | |
861 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
862 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
863 | \r | |
864 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
865 | Register.\r | |
866 | @param OrData The value to OR with the PCI configuration register.\r | |
867 | \r | |
868 | @return The value written back to the PCI configuration register.\r | |
869 | \r | |
870 | **/\r | |
871 | UINT32\r | |
872 | EFIAPI\r | |
873 | PciExpressOr32 (\r | |
874 | IN UINTN Address,\r | |
875 | IN UINT32 OrData\r | |
876 | )\r | |
877 | {\r | |
878 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 879 | return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r |
878ddf1f | 880 | }\r |
881 | \r | |
882 | /**\r | |
883 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
884 | value.\r | |
885 | \r | |
886 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
887 | bitwise AND between the read result and the value specified by AndData, and\r | |
888 | writes the result to the 32-bit PCI configuration register specified by\r | |
889 | Address. The value written to the PCI configuration register is returned.\r | |
890 | This function must guarantee that all PCI read and write operations are\r | |
891 | serialized.\r | |
892 | \r | |
893 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
894 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
895 | \r | |
896 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
897 | Register.\r | |
898 | @param AndData The value to AND with the PCI configuration register.\r | |
899 | \r | |
900 | @return The value written back to the PCI configuration register.\r | |
901 | \r | |
902 | **/\r | |
903 | UINT32\r | |
904 | EFIAPI\r | |
905 | PciExpressAnd32 (\r | |
906 | IN UINTN Address,\r | |
907 | IN UINT32 AndData\r | |
908 | )\r | |
909 | {\r | |
910 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
aa0dc7b4 | 911 | return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r |
878ddf1f | 912 | }\r |
913 | \r | |
914 | /**\r | |
915 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
916 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
917 | \r | |
918 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
919 | bitwise AND between the read result and the value specified by AndData,\r | |
920 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
921 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
922 | configuration register specified by Address. The value written to the PCI\r | |
923 | configuration register is returned. This function must guarantee that all PCI\r | |
924 | read and write operations are serialized.\r | |
925 | \r | |
926 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
927 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
928 | \r | |
929 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
930 | Register.\r | |
931 | @param AndData The value to AND with the PCI configuration register.\r | |
932 | @param OrData The value to OR with the result of the AND operation.\r | |
933 | \r | |
934 | @return The value written back to the PCI configuration register.\r | |
935 | \r | |
936 | **/\r | |
937 | UINT32\r | |
938 | EFIAPI\r | |
939 | PciExpressAndThenOr32 (\r | |
940 | IN UINTN Address,\r | |
941 | IN UINT32 AndData,\r | |
942 | IN UINT32 OrData\r | |
943 | )\r | |
944 | {\r | |
945 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
946 | return MmioAndThenOr32 (\r | |
aa0dc7b4 | 947 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 948 | AndData,\r |
949 | OrData\r | |
950 | );\r | |
951 | }\r | |
952 | \r | |
953 | /**\r | |
954 | Reads a bit field of a PCI configuration register.\r | |
955 | \r | |
956 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
957 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
958 | returned.\r | |
959 | \r | |
960 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
961 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
962 | If StartBit is greater than 31, then ASSERT().\r | |
963 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 964 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 965 | \r |
966 | @param Address PCI configuration register to read.\r | |
967 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
968 | Range 0..31.\r | |
969 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
970 | Range 0..31.\r | |
971 | \r | |
972 | @return The value of the bit field read from the PCI configuration register.\r | |
973 | \r | |
974 | **/\r | |
975 | UINT32\r | |
976 | EFIAPI\r | |
977 | PciExpressBitFieldRead32 (\r | |
978 | IN UINTN Address,\r | |
979 | IN UINTN StartBit,\r | |
980 | IN UINTN EndBit\r | |
981 | )\r | |
982 | {\r | |
983 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
984 | return MmioBitFieldRead32 (\r | |
aa0dc7b4 | 985 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 986 | StartBit,\r |
987 | EndBit\r | |
988 | );\r | |
989 | }\r | |
990 | \r | |
991 | /**\r | |
992 | Writes a bit field to a PCI configuration register.\r | |
993 | \r | |
994 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
995 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
996 | destination PCI configuration register are preserved. The new value of the\r | |
997 | 32-bit register is returned.\r | |
998 | \r | |
999 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1000 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1001 | If StartBit is greater than 31, then ASSERT().\r | |
1002 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 1003 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 1004 | \r |
1005 | @param Address PCI configuration register to write.\r | |
1006 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1007 | Range 0..31.\r | |
1008 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1009 | Range 0..31.\r | |
1010 | @param Value New value of the bit field.\r | |
1011 | \r | |
1012 | @return The value written back to the PCI configuration register.\r | |
1013 | \r | |
1014 | **/\r | |
1015 | UINT32\r | |
1016 | EFIAPI\r | |
1017 | PciExpressBitFieldWrite32 (\r | |
1018 | IN UINTN Address,\r | |
1019 | IN UINTN StartBit,\r | |
1020 | IN UINTN EndBit,\r | |
1021 | IN UINT32 Value\r | |
1022 | )\r | |
1023 | {\r | |
1024 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1025 | return MmioBitFieldWrite32 (\r | |
aa0dc7b4 | 1026 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 1027 | StartBit,\r |
1028 | EndBit,\r | |
1029 | Value\r | |
1030 | );\r | |
1031 | }\r | |
1032 | \r | |
1033 | /**\r | |
1034 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1035 | writes the result back to the bit field in the 32-bit port.\r | |
1036 | \r | |
1037 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1038 | bitwise inclusive OR between the read result and the value specified by\r | |
1039 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1040 | specified by Address. The value written to the PCI configuration register is\r | |
1041 | returned. This function must guarantee that all PCI read and write operations\r | |
1042 | are serialized. Extra left bits in OrData are stripped.\r | |
1043 | \r | |
1044 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1045 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1046 | If StartBit is greater than 31, then ASSERT().\r | |
1047 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 1048 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 1049 | \r |
1050 | @param Address PCI configuration register to write.\r | |
1051 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1052 | Range 0..31.\r | |
1053 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1054 | Range 0..31.\r | |
1055 | @param OrData The value to OR with the PCI configuration register.\r | |
1056 | \r | |
1057 | @return The value written back to the PCI configuration register.\r | |
1058 | \r | |
1059 | **/\r | |
1060 | UINT32\r | |
1061 | EFIAPI\r | |
1062 | PciExpressBitFieldOr32 (\r | |
1063 | IN UINTN Address,\r | |
1064 | IN UINTN StartBit,\r | |
1065 | IN UINTN EndBit,\r | |
1066 | IN UINT32 OrData\r | |
1067 | )\r | |
1068 | {\r | |
1069 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1070 | return MmioBitFieldOr32 (\r | |
aa0dc7b4 | 1071 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 1072 | StartBit,\r |
1073 | EndBit,\r | |
1074 | OrData\r | |
1075 | );\r | |
1076 | }\r | |
1077 | \r | |
1078 | /**\r | |
1079 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1080 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1081 | \r | |
1082 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1083 | bitwise AND between the read result and the value specified by AndData, and\r | |
1084 | writes the result to the 32-bit PCI configuration register specified by\r | |
1085 | Address. The value written to the PCI configuration register is returned.\r | |
1086 | This function must guarantee that all PCI read and write operations are\r | |
1087 | serialized. Extra left bits in AndData are stripped.\r | |
1088 | \r | |
1089 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1090 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1091 | If StartBit is greater than 31, then ASSERT().\r | |
1092 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 1093 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 1094 | \r |
1095 | @param Address PCI configuration register to write.\r | |
1096 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1097 | Range 0..31.\r | |
1098 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1099 | Range 0..31.\r | |
1100 | @param AndData The value to AND with the PCI configuration register.\r | |
1101 | \r | |
1102 | @return The value written back to the PCI configuration register.\r | |
1103 | \r | |
1104 | **/\r | |
1105 | UINT32\r | |
1106 | EFIAPI\r | |
1107 | PciExpressBitFieldAnd32 (\r | |
1108 | IN UINTN Address,\r | |
1109 | IN UINTN StartBit,\r | |
1110 | IN UINTN EndBit,\r | |
1111 | IN UINT32 AndData\r | |
1112 | )\r | |
1113 | {\r | |
1114 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1115 | return MmioBitFieldAnd32 (\r | |
aa0dc7b4 | 1116 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 1117 | StartBit,\r |
1118 | EndBit,\r | |
1119 | AndData\r | |
1120 | );\r | |
1121 | }\r | |
1122 | \r | |
1123 | /**\r | |
1124 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1125 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
1126 | 32-bit port.\r | |
1127 | \r | |
1128 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1129 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
1130 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1131 | configuration register specified by Address. The value written to the PCI\r | |
1132 | configuration register is returned. This function must guarantee that all PCI\r | |
1133 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1134 | OrData are stripped.\r | |
1135 | \r | |
1136 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1137 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1138 | If StartBit is greater than 31, then ASSERT().\r | |
1139 | If EndBit is greater than 31, then ASSERT().\r | |
0ffa1286 | 1140 | If EndBit is less than StartBit, then ASSERT().\r |
878ddf1f | 1141 | \r |
1142 | @param Address PCI configuration register to write.\r | |
1143 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1144 | Range 0..31.\r | |
1145 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1146 | Range 0..31.\r | |
1147 | @param AndData The value to AND with the PCI configuration register.\r | |
1148 | @param OrData The value to OR with the result of the AND operation.\r | |
1149 | \r | |
1150 | @return The value written back to the PCI configuration register.\r | |
1151 | \r | |
1152 | **/\r | |
1153 | UINT32\r | |
1154 | EFIAPI\r | |
1155 | PciExpressBitFieldAndThenOr32 (\r | |
1156 | IN UINTN Address,\r | |
1157 | IN UINTN StartBit,\r | |
1158 | IN UINTN EndBit,\r | |
1159 | IN UINT32 AndData,\r | |
1160 | IN UINT32 OrData\r | |
1161 | )\r | |
1162 | {\r | |
1163 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1164 | return MmioBitFieldAndThenOr32 (\r | |
aa0dc7b4 | 1165 | (UINTN) GetPciExpressBaseAddress () + Address,\r |
878ddf1f | 1166 | StartBit,\r |
1167 | EndBit,\r | |
1168 | AndData,\r | |
1169 | OrData\r | |
1170 | );\r | |
1171 | }\r | |
1172 | \r | |
1173 | /**\r | |
1174 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1175 | \r | |
1176 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1177 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1178 | configuration registers from a single PCI function to be read. Size is\r | |
1179 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1180 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1181 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1182 | end of the range.\r | |
1183 | \r | |
1184 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1185 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
add13dc2 | 1186 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
878ddf1f | 1187 | \r |
1188 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1189 | Function and Register.\r | |
1190 | @param Size Size in bytes of the transfer.\r | |
1191 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1192 | \r | |
1193 | @return Size\r | |
1194 | \r | |
1195 | **/\r | |
1196 | UINTN\r | |
1197 | EFIAPI\r | |
1198 | PciExpressReadBuffer (\r | |
1199 | IN UINTN StartAddress,\r | |
1200 | IN UINTN Size,\r | |
1201 | OUT VOID *Buffer\r | |
1202 | )\r | |
1203 | {\r | |
9748aecc | 1204 | UINTN ReturnValue;\r |
878ddf1f | 1205 | \r |
9a462b41 | 1206 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r |
cd14fe3d | 1207 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
28c73f6e | 1208 | \r |
1209 | if (Size == 0) {\r | |
9748aecc | 1210 | return Size;\r |
28c73f6e | 1211 | }\r |
1212 | \r | |
1213 | ASSERT (Buffer != NULL);\r | |
9a462b41 | 1214 | \r |
9748aecc | 1215 | //\r |
1216 | // Save Size for return\r | |
1217 | //\r | |
1218 | ReturnValue = Size;\r | |
878ddf1f | 1219 | \r |
28c73f6e | 1220 | if ((StartAddress & 1) != 0) {\r |
878ddf1f | 1221 | //\r |
1222 | // Read a byte if StartAddress is byte aligned\r | |
1223 | //\r | |
2ce31132 | 1224 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r |
878ddf1f | 1225 | StartAddress += sizeof (UINT8);\r |
9748aecc | 1226 | Size -= sizeof (UINT8);\r |
878ddf1f | 1227 | Buffer = (UINT8*)Buffer + 1;\r |
1228 | }\r | |
1229 | \r | |
9748aecc | 1230 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r |
878ddf1f | 1231 | //\r |
1232 | // Read a word if StartAddress is word aligned\r | |
1233 | //\r | |
2ce31132 | 1234 | *(volatile UINT16 *)Buffer = PciExpressRead16 (StartAddress);\r |
878ddf1f | 1235 | StartAddress += sizeof (UINT16);\r |
9748aecc | 1236 | Size -= sizeof (UINT16);\r |
878ddf1f | 1237 | Buffer = (UINT16*)Buffer + 1;\r |
1238 | }\r | |
1239 | \r | |
9748aecc | 1240 | while (Size >= sizeof (UINT32)) {\r |
878ddf1f | 1241 | //\r |
1242 | // Read as many double words as possible\r | |
1243 | //\r | |
2ce31132 | 1244 | *(volatile UINT32 *)Buffer = PciExpressRead32 (StartAddress);\r |
878ddf1f | 1245 | StartAddress += sizeof (UINT32);\r |
9748aecc | 1246 | Size -= sizeof (UINT32);\r |
878ddf1f | 1247 | Buffer = (UINT32*)Buffer + 1;\r |
1248 | }\r | |
1249 | \r | |
9748aecc | 1250 | if (Size >= sizeof (UINT16)) {\r |
878ddf1f | 1251 | //\r |
1252 | // Read the last remaining word if exist\r | |
1253 | //\r | |
2ce31132 | 1254 | *(volatile UINT16 *)Buffer = PciExpressRead16 (StartAddress);\r |
878ddf1f | 1255 | StartAddress += sizeof (UINT16);\r |
9748aecc | 1256 | Size -= sizeof (UINT16);\r |
878ddf1f | 1257 | Buffer = (UINT16*)Buffer + 1;\r |
1258 | }\r | |
1259 | \r | |
9748aecc | 1260 | if (Size >= sizeof (UINT8)) {\r |
878ddf1f | 1261 | //\r |
1262 | // Read the last remaining byte if exist\r | |
1263 | //\r | |
2ce31132 | 1264 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r |
878ddf1f | 1265 | }\r |
1266 | \r | |
9748aecc | 1267 | return ReturnValue;\r |
878ddf1f | 1268 | }\r |
1269 | \r | |
1270 | /**\r | |
1271 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1272 | configuration space.\r | |
1273 | \r | |
1274 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1275 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1276 | configuration registers from a single PCI function to be written. Size is\r | |
1277 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1278 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1279 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1280 | and the end of the range.\r | |
1281 | \r | |
1282 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1283 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
add13dc2 | 1284 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
878ddf1f | 1285 | \r |
1286 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1287 | Function and Register.\r | |
1288 | @param Size Size in bytes of the transfer.\r | |
1289 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1290 | \r | |
1291 | @return Size\r | |
1292 | \r | |
1293 | **/\r | |
1294 | UINTN\r | |
1295 | EFIAPI\r | |
1296 | PciExpressWriteBuffer (\r | |
1297 | IN UINTN StartAddress,\r | |
1298 | IN UINTN Size,\r | |
1299 | IN VOID *Buffer\r | |
1300 | )\r | |
1301 | {\r | |
9748aecc | 1302 | UINTN ReturnValue;\r |
878ddf1f | 1303 | \r |
9a462b41 | 1304 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r |
cd14fe3d | 1305 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
28c73f6e | 1306 | \r |
1307 | if (Size == 0) {\r | |
1308 | return 0;\r | |
1309 | }\r | |
1310 | \r | |
1311 | ASSERT (Buffer != NULL);\r | |
9a462b41 | 1312 | \r |
9748aecc | 1313 | //\r |
1314 | // Save Size for return\r | |
1315 | //\r | |
1316 | ReturnValue = Size;\r | |
878ddf1f | 1317 | \r |
28c73f6e | 1318 | if ((StartAddress & 1) != 0) {\r |
878ddf1f | 1319 | //\r |
1320 | // Write a byte if StartAddress is byte aligned\r | |
1321 | //\r | |
1322 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1323 | StartAddress += sizeof (UINT8);\r | |
9748aecc | 1324 | Size -= sizeof (UINT8);\r |
878ddf1f | 1325 | Buffer = (UINT8*)Buffer + 1;\r |
1326 | }\r | |
1327 | \r | |
9748aecc | 1328 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r |
878ddf1f | 1329 | //\r |
1330 | // Write a word if StartAddress is word aligned\r | |
1331 | //\r | |
1332 | PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1333 | StartAddress += sizeof (UINT16);\r | |
9748aecc | 1334 | Size -= sizeof (UINT16);\r |
878ddf1f | 1335 | Buffer = (UINT16*)Buffer + 1;\r |
1336 | }\r | |
1337 | \r | |
9748aecc | 1338 | while (Size >= sizeof (UINT32)) {\r |
878ddf1f | 1339 | //\r |
1340 | // Write as many double words as possible\r | |
1341 | //\r | |
1342 | PciExpressWrite32 (StartAddress, *(UINT32*)Buffer);\r | |
1343 | StartAddress += sizeof (UINT32);\r | |
9748aecc | 1344 | Size -= sizeof (UINT32);\r |
878ddf1f | 1345 | Buffer = (UINT32*)Buffer + 1;\r |
1346 | }\r | |
1347 | \r | |
9748aecc | 1348 | if (Size >= sizeof (UINT16)) {\r |
878ddf1f | 1349 | //\r |
1350 | // Write the last remaining word if exist\r | |
1351 | //\r | |
1352 | PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1353 | StartAddress += sizeof (UINT16);\r | |
9748aecc | 1354 | Size -= sizeof (UINT16);\r |
878ddf1f | 1355 | Buffer = (UINT16*)Buffer + 1;\r |
1356 | }\r | |
1357 | \r | |
9748aecc | 1358 | if (Size >= sizeof (UINT8)) {\r |
878ddf1f | 1359 | //\r |
1360 | // Write the last remaining byte if exist\r | |
1361 | //\r | |
1362 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1363 | }\r | |
1364 | \r | |
9748aecc | 1365 | return ReturnValue;\r |
878ddf1f | 1366 | }\r |