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fe69ac84 | 1 | /** @file\r |
2 | PCI configuration Library Services that do PCI configuration and also enable\r | |
3 | the PCI operations to be replayed during an S3 resume. This library class\r | |
4 | maps directly on top of the PciLib class. \r | |
5 | \r | |
6 | Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r | |
7 | \r | |
8 | This program and the accompanying materials\r | |
9 | are licensed and made available under the terms and conditions\r | |
10 | of the BSD License which accompanies this distribution. The\r | |
11 | full text of the license may be found at\r | |
12 | http://opensource.org/licenses/bsd-license.php\r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | \r | |
20 | #include <Base.h>\r | |
21 | \r | |
22 | #include <Library/DebugLib.h>\r | |
23 | #include <Library/S3BootScriptLib.h>\r | |
24 | #include <Library/PciLib.h>\r | |
25 | #include <Library/S3PciLib.h>\r | |
26 | \r | |
27 | #define PCILIB_TO_COMMON_ADDRESS(Address) \\r | |
28 | ((UINT64) ((((UINTN) ((Address>>20) & 0xff)) << 24) + (((UINTN) ((Address>>15) & 0x1f)) << 16) + (((UINTN) ((Address>>12) & 0x07)) << 8) + ((UINTN) (Address & 0xfff ))))\r | |
29 | \r | |
30 | /**\r | |
31 | Saves a PCI configuration value to the boot script.\r | |
32 | \r | |
33 | This internal worker function saves a PCI configuration value in\r | |
34 | the S3 script to be replayed on S3 resume. \r | |
35 | \r | |
36 | If the saving process fails, then ASSERT().\r | |
37 | \r | |
38 | @param Width The width of PCI configuration.\r | |
39 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
40 | Register.\r | |
41 | @param Buffer The buffer containing value.\r | |
42 | \r | |
43 | **/\r | |
44 | VOID\r | |
45 | InternalSavePciWriteValueToBootScript (\r | |
46 | IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r | |
47 | IN UINTN Address,\r | |
48 | IN VOID *Buffer\r | |
49 | )\r | |
50 | {\r | |
51 | RETURN_STATUS Status;\r | |
52 | \r | |
53 | Status = S3BootScriptSavePciCfgWrite (\r | |
54 | Width,\r | |
55 | PCILIB_TO_COMMON_ADDRESS(Address),\r | |
56 | 1,\r | |
57 | Buffer\r | |
58 | );\r | |
59 | ASSERT (Status == RETURN_SUCCESS);\r | |
60 | }\r | |
61 | \r | |
62 | /**\r | |
63 | Saves an 8-bit PCI configuration value to the boot script.\r | |
64 | \r | |
65 | This internal worker function saves an 8-bit PCI configuration value in\r | |
66 | the S3 script to be replayed on S3 resume. \r | |
67 | \r | |
68 | If the saving process fails, then ASSERT().\r | |
69 | \r | |
70 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
71 | Register.\r | |
72 | @param Value The value saved to boot script.\r | |
73 | \r | |
74 | @return Value.\r | |
75 | \r | |
76 | **/\r | |
77 | UINT8\r | |
78 | InternalSavePciWrite8ValueToBootScript (\r | |
79 | IN UINTN Address,\r | |
80 | IN UINT8 Value\r | |
81 | )\r | |
82 | {\r | |
83 | InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);\r | |
84 | \r | |
85 | return Value;\r | |
86 | }\r | |
87 | \r | |
88 | /**\r | |
89 | Reads an 8-bit PCI configuration register and saves the value in the S3\r | |
90 | script to be replayed on S3 resume.\r | |
91 | \r | |
92 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
93 | This function must guarantee that all PCI read and write operations are\r | |
94 | serialized.\r | |
95 | \r | |
96 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
97 | \r | |
98 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
99 | Register.\r | |
100 | \r | |
101 | @return The read value from the PCI configuration register.\r | |
102 | \r | |
103 | **/\r | |
104 | UINT8\r | |
105 | EFIAPI\r | |
106 | S3PciRead8 (\r | |
107 | IN UINTN Address\r | |
108 | )\r | |
109 | {\r | |
110 | return InternalSavePciWrite8ValueToBootScript (Address, PciRead8 (Address));\r | |
111 | }\r | |
112 | \r | |
113 | /**\r | |
114 | Writes an 8-bit PCI configuration register and saves the value in the S3\r | |
115 | script to be replayed on S3 resume.\r | |
116 | \r | |
117 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
118 | value specified by Value. Value is returned. This function must guarantee\r | |
119 | that all PCI read and write operations are serialized.\r | |
120 | \r | |
121 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
122 | \r | |
123 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
124 | Register.\r | |
125 | @param Value The value to write.\r | |
126 | \r | |
127 | @return The value written to the PCI configuration register.\r | |
128 | \r | |
129 | **/\r | |
130 | UINT8\r | |
131 | EFIAPI\r | |
132 | S3PciWrite8 (\r | |
133 | IN UINTN Address,\r | |
134 | IN UINT8 Value\r | |
135 | )\r | |
136 | {\r | |
137 | return InternalSavePciWrite8ValueToBootScript (Address, PciWrite8 (Address, Value));\r | |
138 | }\r | |
139 | \r | |
140 | /**\r | |
141 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
142 | an 8-bit value and saves the value in the S3 script to be replayed on S3 resume.\r | |
143 | \r | |
144 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
145 | bitwise OR between the read result and the value specified by\r | |
146 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
147 | specified by Address. The value written to the PCI configuration register is\r | |
148 | returned. This function must guarantee that all PCI read and write operations\r | |
149 | are serialized.\r | |
150 | \r | |
151 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
152 | \r | |
153 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
154 | Register.\r | |
155 | @param OrData The value to OR with the PCI configuration register.\r | |
156 | \r | |
157 | @return The value written back to the PCI configuration register.\r | |
158 | \r | |
159 | **/\r | |
160 | UINT8\r | |
161 | EFIAPI\r | |
162 | S3PciOr8 (\r | |
163 | IN UINTN Address,\r | |
164 | IN UINT8 OrData\r | |
165 | )\r | |
166 | {\r | |
167 | return InternalSavePciWrite8ValueToBootScript (Address, PciOr8 (Address, OrData));\r | |
168 | }\r | |
169 | \r | |
170 | /**\r | |
171 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
172 | value and saves the value in the S3 script to be replayed on S3 resume.\r | |
173 | \r | |
174 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
175 | bitwise AND between the read result and the value specified by AndData, and\r | |
176 | writes the result to the 8-bit PCI configuration register specified by\r | |
177 | Address. The value written to the PCI configuration register is returned.\r | |
178 | This function must guarantee that all PCI read and write operations are\r | |
179 | serialized.\r | |
180 | \r | |
181 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
182 | \r | |
183 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
184 | Register.\r | |
185 | @param AndData The value to AND with the PCI configuration register.\r | |
186 | \r | |
187 | @return The value written back to the PCI configuration register.\r | |
188 | \r | |
189 | **/\r | |
190 | UINT8\r | |
191 | EFIAPI\r | |
192 | S3PciAnd8 (\r | |
193 | IN UINTN Address,\r | |
194 | IN UINT8 AndData\r | |
195 | )\r | |
196 | {\r | |
197 | return InternalSavePciWrite8ValueToBootScript (Address, PciAnd8 (Address, AndData));\r | |
198 | }\r | |
199 | \r | |
200 | /**\r | |
201 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
202 | value, followed a bitwise OR with another 8-bit value and saves\r | |
203 | the value in the S3 script to be replayed on S3 resume.\r | |
204 | \r | |
205 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
206 | bitwise AND between the read result and the value specified by AndData,\r | |
207 | performs a bitwise OR between the result of the AND operation and\r | |
208 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
209 | configuration register specified by Address. The value written to the PCI\r | |
210 | configuration register is returned. This function must guarantee that all PCI\r | |
211 | read and write operations are serialized.\r | |
212 | \r | |
213 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
214 | \r | |
215 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
216 | Register.\r | |
217 | @param AndData The value to AND with the PCI configuration register.\r | |
218 | @param OrData The value to OR with the result of the AND operation.\r | |
219 | \r | |
220 | @return The value written back to the PCI configuration register.\r | |
221 | \r | |
222 | **/\r | |
223 | UINT8\r | |
224 | EFIAPI\r | |
225 | S3PciAndThenOr8 (\r | |
226 | IN UINTN Address,\r | |
227 | IN UINT8 AndData,\r | |
228 | IN UINT8 OrData\r | |
229 | )\r | |
230 | {\r | |
231 | return InternalSavePciWrite8ValueToBootScript (Address, PciAndThenOr8 (Address, AndData, OrData));\r | |
232 | }\r | |
233 | \r | |
234 | /**\r | |
235 | Reads a bit field of a PCI configuration register and saves the value in\r | |
236 | the S3 script to be replayed on S3 resume.\r | |
237 | \r | |
238 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
239 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
240 | returned.\r | |
241 | \r | |
242 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
243 | If StartBit is greater than 7, then ASSERT().\r | |
244 | If EndBit is greater than 7, then ASSERT().\r | |
245 | If EndBit is less than StartBit, then ASSERT().\r | |
246 | \r | |
247 | @param Address PCI configuration register to read.\r | |
248 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
249 | Range 0..7.\r | |
250 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
251 | Range 0..7.\r | |
252 | \r | |
253 | @return The value of the bit field read from the PCI configuration register.\r | |
254 | \r | |
255 | **/\r | |
256 | UINT8\r | |
257 | EFIAPI\r | |
258 | S3PciBitFieldRead8 (\r | |
259 | IN UINTN Address,\r | |
260 | IN UINTN StartBit,\r | |
261 | IN UINTN EndBit\r | |
262 | )\r | |
263 | {\r | |
264 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldRead8 (Address, StartBit, EndBit));\r | |
265 | }\r | |
266 | \r | |
267 | /**\r | |
268 | Writes a bit field to a PCI configuration register and saves the value in\r | |
269 | the S3 script to be replayed on S3 resume.\r | |
270 | \r | |
271 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
272 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
273 | destination PCI configuration register are preserved. The new value of the\r | |
274 | 8-bit register is returned.\r | |
275 | \r | |
276 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
277 | If StartBit is greater than 7, then ASSERT().\r | |
278 | If EndBit is greater than 7, then ASSERT().\r | |
279 | If EndBit is less than StartBit, then ASSERT().\r | |
280 | \r | |
281 | @param Address PCI configuration register to write.\r | |
282 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
283 | Range 0..7.\r | |
284 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
285 | Range 0..7.\r | |
286 | @param Value New value of the bit field.\r | |
287 | \r | |
288 | @return The value written back to the PCI configuration register.\r | |
289 | \r | |
290 | **/\r | |
291 | UINT8\r | |
292 | EFIAPI\r | |
293 | S3PciBitFieldWrite8 (\r | |
294 | IN UINTN Address,\r | |
295 | IN UINTN StartBit,\r | |
296 | IN UINTN EndBit,\r | |
297 | IN UINT8 Value\r | |
298 | )\r | |
299 | {\r | |
300 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldWrite8 (Address, StartBit, EndBit, Value));\r | |
301 | }\r | |
302 | \r | |
303 | /**\r | |
304 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
305 | writes the result back to the bit field in the 8-bit port and saves the value\r | |
306 | in the S3 script to be replayed on S3 resume.\r | |
307 | \r | |
308 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
309 | bitwise OR between the read result and the value specified by\r | |
310 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
311 | specified by Address. The value written to the PCI configuration register is\r | |
312 | returned. This function must guarantee that all PCI read and write operations\r | |
313 | are serialized. Extra left bits in OrData are stripped.\r | |
314 | \r | |
315 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
316 | If StartBit is greater than 7, then ASSERT().\r | |
317 | If EndBit is greater than 7, then ASSERT().\r | |
318 | If EndBit is less than StartBit, then ASSERT().\r | |
319 | \r | |
320 | @param Address PCI configuration register to write.\r | |
321 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
322 | Range 0..7.\r | |
323 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
324 | Range 0..7.\r | |
325 | @param OrData The value to OR with the PCI configuration register.\r | |
326 | \r | |
327 | @return The value written back to the PCI configuration register.\r | |
328 | \r | |
329 | **/\r | |
330 | UINT8\r | |
331 | EFIAPI\r | |
332 | S3PciBitFieldOr8 (\r | |
333 | IN UINTN Address,\r | |
334 | IN UINTN StartBit,\r | |
335 | IN UINTN EndBit,\r | |
336 | IN UINT8 OrData\r | |
337 | )\r | |
338 | {\r | |
339 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldOr8 (Address, StartBit, EndBit, OrData));\r | |
340 | }\r | |
341 | \r | |
342 | /**\r | |
343 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
344 | AND, and writes the result back to the bit field in the 8-bit register and\r | |
345 | saves the value in the S3 script to be replayed on S3 resume.\r | |
346 | \r | |
347 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
348 | bitwise AND between the read result and the value specified by AndData, and\r | |
349 | writes the result to the 8-bit PCI configuration register specified by\r | |
350 | Address. The value written to the PCI configuration register is returned.\r | |
351 | This function must guarantee that all PCI read and write operations are\r | |
352 | serialized. Extra left bits in AndData are stripped.\r | |
353 | \r | |
354 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
355 | If StartBit is greater than 7, then ASSERT().\r | |
356 | If EndBit is greater than 7, then ASSERT().\r | |
357 | If EndBit is less than StartBit, then ASSERT().\r | |
358 | \r | |
359 | @param Address PCI configuration register to write.\r | |
360 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
361 | Range 0..7.\r | |
362 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
363 | Range 0..7.\r | |
364 | @param AndData The value to AND with the PCI configuration register.\r | |
365 | \r | |
366 | @return The value written back to the PCI configuration register.\r | |
367 | \r | |
368 | **/\r | |
369 | UINT8\r | |
370 | EFIAPI\r | |
371 | S3PciBitFieldAnd8 (\r | |
372 | IN UINTN Address,\r | |
373 | IN UINTN StartBit,\r | |
374 | IN UINTN EndBit,\r | |
375 | IN UINT8 AndData\r | |
376 | )\r | |
377 | {\r | |
378 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAnd8 (Address, StartBit, EndBit, AndData));\r | |
379 | }\r | |
380 | \r | |
381 | /**\r | |
382 | Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a\r | |
383 | bitwise OR, and writes the result back to the bit field in the\r | |
384 | 8-bit port and saves the value in the S3 script to be replayed on S3 resume.\r | |
385 | \r | |
386 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
387 | bitwise AND followed by a bitwise OR between the read result and\r | |
388 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
389 | configuration register specified by Address. The value written to the PCI\r | |
390 | configuration register is returned. This function must guarantee that all PCI\r | |
391 | read and write operations are serialized. Extra left bits in both AndData and\r | |
392 | OrData are stripped.\r | |
393 | \r | |
394 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
395 | If StartBit is greater than 7, then ASSERT().\r | |
396 | If EndBit is greater than 7, then ASSERT().\r | |
397 | If EndBit is less than StartBit, then ASSERT().\r | |
398 | \r | |
399 | @param Address PCI configuration register to write.\r | |
400 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
401 | Range 0..7.\r | |
402 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
403 | Range 0..7.\r | |
404 | @param AndData The value to AND with the PCI configuration register.\r | |
405 | @param OrData The value to OR with the result of the AND operation.\r | |
406 | \r | |
407 | @return The value written back to the PCI configuration register.\r | |
408 | \r | |
409 | **/\r | |
410 | UINT8\r | |
411 | EFIAPI\r | |
412 | S3PciBitFieldAndThenOr8 (\r | |
413 | IN UINTN Address,\r | |
414 | IN UINTN StartBit,\r | |
415 | IN UINTN EndBit,\r | |
416 | IN UINT8 AndData,\r | |
417 | IN UINT8 OrData\r | |
418 | )\r | |
419 | {\r | |
420 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));\r | |
421 | }\r | |
422 | \r | |
423 | /**\r | |
424 | Saves a 16-bit PCI configuration value to the boot script.\r | |
425 | \r | |
426 | This internal worker function saves a 16-bit PCI configuration value in\r | |
427 | the S3 script to be replayed on S3 resume. \r | |
428 | \r | |
429 | If the saving process fails, then ASSERT().\r | |
430 | \r | |
431 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
432 | Register.\r | |
433 | @param Value The value to write.\r | |
434 | \r | |
435 | @return Value.\r | |
436 | \r | |
437 | **/\r | |
438 | UINT16\r | |
439 | InternalSavePciWrite16ValueToBootScript (\r | |
440 | IN UINTN Address,\r | |
441 | IN UINT16 Value\r | |
442 | )\r | |
443 | {\r | |
444 | InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);\r | |
445 | \r | |
446 | return Value;\r | |
447 | }\r | |
448 | \r | |
449 | /**\r | |
450 | Reads a 16-bit PCI configuration register and saves the value in the S3\r | |
451 | script to be replayed on S3 resume.\r | |
452 | \r | |
453 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
454 | This function must guarantee that all PCI read and write operations are\r | |
455 | serialized.\r | |
456 | \r | |
457 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
458 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
459 | \r | |
460 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
461 | Register.\r | |
462 | \r | |
463 | @return The read value from the PCI configuration register.\r | |
464 | \r | |
465 | **/\r | |
466 | UINT16\r | |
467 | EFIAPI\r | |
468 | S3PciRead16 (\r | |
469 | IN UINTN Address\r | |
470 | )\r | |
471 | {\r | |
472 | return InternalSavePciWrite16ValueToBootScript (Address, PciRead16 (Address));\r | |
473 | }\r | |
474 | \r | |
475 | /**\r | |
476 | Writes a 16-bit PCI configuration register and saves the value in the S3\r | |
477 | script to be replayed on S3 resume.\r | |
478 | \r | |
479 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
480 | value specified by Value. Value is returned. This function must guarantee\r | |
481 | that all PCI read and write operations are serialized.\r | |
482 | \r | |
483 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
484 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
485 | \r | |
486 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
487 | Register.\r | |
488 | @param Value The value to write.\r | |
489 | \r | |
490 | @return The value written to the PCI configuration register.\r | |
491 | \r | |
492 | **/\r | |
493 | UINT16\r | |
494 | EFIAPI\r | |
495 | S3PciWrite16 (\r | |
496 | IN UINTN Address,\r | |
497 | IN UINT16 Value\r | |
498 | )\r | |
499 | {\r | |
500 | return InternalSavePciWrite16ValueToBootScript (Address, PciWrite16 (Address, Value));\r | |
501 | }\r | |
502 | \r | |
503 | /**\r | |
504 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
505 | a 16-bit value and saves the value in the S3 script to be replayed on S3 resume.\r | |
506 | \r | |
507 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
508 | bitwise OR between the read result and the value specified by\r | |
509 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
510 | specified by Address. The value written to the PCI configuration register is\r | |
511 | returned. This function must guarantee that all PCI read and write operations\r | |
512 | are serialized.\r | |
513 | \r | |
514 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
515 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
516 | \r | |
517 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
518 | Register.\r | |
519 | @param OrData The value to OR with the PCI configuration register.\r | |
520 | \r | |
521 | @return The value written back to the PCI configuration register.\r | |
522 | \r | |
523 | **/\r | |
524 | UINT16\r | |
525 | EFIAPI\r | |
526 | S3PciOr16 (\r | |
527 | IN UINTN Address,\r | |
528 | IN UINT16 OrData\r | |
529 | )\r | |
530 | {\r | |
531 | return InternalSavePciWrite16ValueToBootScript (Address, PciOr16 (Address, OrData));\r | |
532 | }\r | |
533 | \r | |
534 | /**\r | |
535 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
536 | value and saves the value in the S3 script to be replayed on S3 resume.\r | |
537 | \r | |
538 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
539 | bitwise AND between the read result and the value specified by AndData, and\r | |
540 | writes the result to the 16-bit PCI configuration register specified by\r | |
541 | Address. The value written to the PCI configuration register is returned.\r | |
542 | This function must guarantee that all PCI read and write operations are\r | |
543 | serialized.\r | |
544 | \r | |
545 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
546 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
547 | \r | |
548 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
549 | Register.\r | |
550 | @param AndData The value to AND with the PCI configuration register.\r | |
551 | \r | |
552 | @return The value written back to the PCI configuration register.\r | |
553 | \r | |
554 | **/\r | |
555 | UINT16\r | |
556 | EFIAPI\r | |
557 | S3PciAnd16 (\r | |
558 | IN UINTN Address,\r | |
559 | IN UINT16 AndData\r | |
560 | )\r | |
561 | {\r | |
562 | return InternalSavePciWrite16ValueToBootScript (Address, PciAnd16 (Address, AndData));\r | |
563 | }\r | |
564 | \r | |
565 | /**\r | |
566 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
567 | value, followed a bitwise OR with another 16-bit value and saves\r | |
568 | the value in the S3 script to be replayed on S3 resume.\r | |
569 | \r | |
570 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
571 | bitwise AND between the read result and the value specified by AndData,\r | |
572 | performs a bitwise OR between the result of the AND operation and\r | |
573 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
574 | configuration register specified by Address. The value written to the PCI\r | |
575 | configuration register is returned. This function must guarantee that all PCI\r | |
576 | read and write operations are serialized.\r | |
577 | \r | |
578 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
579 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
580 | \r | |
581 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
582 | Register.\r | |
583 | @param AndData The value to AND with the PCI configuration register.\r | |
584 | @param OrData The value to OR with the result of the AND operation.\r | |
585 | \r | |
586 | @return The value written back to the PCI configuration register.\r | |
587 | \r | |
588 | **/\r | |
589 | UINT16\r | |
590 | EFIAPI\r | |
591 | S3PciAndThenOr16 (\r | |
592 | IN UINTN Address,\r | |
593 | IN UINT16 AndData,\r | |
594 | IN UINT16 OrData\r | |
595 | )\r | |
596 | {\r | |
597 | return InternalSavePciWrite16ValueToBootScript (Address, PciAndThenOr16 (Address, AndData, OrData));\r | |
598 | }\r | |
599 | \r | |
600 | /**\r | |
601 | Reads a bit field of a PCI configuration register and saves the value in\r | |
602 | the S3 script to be replayed on S3 resume.\r | |
603 | \r | |
604 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
605 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
606 | returned.\r | |
607 | \r | |
608 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
609 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
610 | If StartBit is greater than 15, then ASSERT().\r | |
611 | If EndBit is greater than 15, then ASSERT().\r | |
612 | If EndBit is less than StartBit, then ASSERT().\r | |
613 | \r | |
614 | @param Address PCI configuration register to read.\r | |
615 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
616 | Range 0..15.\r | |
617 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
618 | Range 0..15.\r | |
619 | \r | |
620 | @return The value of the bit field read from the PCI configuration register.\r | |
621 | \r | |
622 | **/\r | |
623 | UINT16\r | |
624 | EFIAPI\r | |
625 | S3PciBitFieldRead16 (\r | |
626 | IN UINTN Address,\r | |
627 | IN UINTN StartBit,\r | |
628 | IN UINTN EndBit\r | |
629 | )\r | |
630 | {\r | |
631 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldRead16 (Address, StartBit, EndBit));\r | |
632 | }\r | |
633 | \r | |
634 | /**\r | |
635 | Writes a bit field to a PCI configuration register and saves the value in\r | |
636 | the S3 script to be replayed on S3 resume.\r | |
637 | \r | |
638 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
639 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
640 | destination PCI configuration register are preserved. The new value of the\r | |
641 | 16-bit register is returned.\r | |
642 | \r | |
643 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
644 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
645 | If StartBit is greater than 15, then ASSERT().\r | |
646 | If EndBit is greater than 15, then ASSERT().\r | |
647 | If EndBit is less than StartBit, then ASSERT().\r | |
648 | \r | |
649 | @param Address PCI configuration register to write.\r | |
650 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
651 | Range 0..15.\r | |
652 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
653 | Range 0..15.\r | |
654 | @param Value New value of the bit field.\r | |
655 | \r | |
656 | @return The value written back to the PCI configuration register.\r | |
657 | \r | |
658 | **/\r | |
659 | UINT16\r | |
660 | EFIAPI\r | |
661 | S3PciBitFieldWrite16 (\r | |
662 | IN UINTN Address,\r | |
663 | IN UINTN StartBit,\r | |
664 | IN UINTN EndBit,\r | |
665 | IN UINT16 Value\r | |
666 | )\r | |
667 | {\r | |
668 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldWrite16 (Address, StartBit, EndBit, Value));\r | |
669 | }\r | |
670 | \r | |
671 | /**\r | |
672 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
673 | writes the result back to the bit field in the 16-bit port and saves the value\r | |
674 | in the S3 script to be replayed on S3 resume.\r | |
675 | \r | |
676 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
677 | bitwise OR between the read result and the value specified by\r | |
678 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
679 | specified by Address. The value written to the PCI configuration register is\r | |
680 | returned. This function must guarantee that all PCI read and write operations\r | |
681 | are serialized. Extra left bits in OrData are stripped.\r | |
682 | \r | |
683 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
684 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
685 | If StartBit is greater than 15, then ASSERT().\r | |
686 | If EndBit is greater than 15, then ASSERT().\r | |
687 | If EndBit is less than StartBit, then ASSERT().\r | |
688 | \r | |
689 | @param Address PCI configuration register to write.\r | |
690 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
691 | Range 0..15.\r | |
692 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
693 | Range 0..15.\r | |
694 | @param OrData The value to OR with the PCI configuration register.\r | |
695 | \r | |
696 | @return The value written back to the PCI configuration register.\r | |
697 | \r | |
698 | **/\r | |
699 | UINT16\r | |
700 | EFIAPI\r | |
701 | S3PciBitFieldOr16 (\r | |
702 | IN UINTN Address,\r | |
703 | IN UINTN StartBit,\r | |
704 | IN UINTN EndBit,\r | |
705 | IN UINT16 OrData\r | |
706 | )\r | |
707 | {\r | |
708 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldOr16 (Address, StartBit, EndBit, OrData));\r | |
709 | }\r | |
710 | \r | |
711 | /**\r | |
712 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
713 | AND, and writes the result back to the bit field in the 16-bit register and\r | |
714 | saves the value in the S3 script to be replayed on S3 resume.\r | |
715 | \r | |
716 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
717 | bitwise AND between the read result and the value specified by AndData, and\r | |
718 | writes the result to the 16-bit PCI configuration register specified by\r | |
719 | Address. The value written to the PCI configuration register is returned.\r | |
720 | This function must guarantee that all PCI read and write operations are\r | |
721 | serialized. Extra left bits in AndData are stripped.\r | |
722 | \r | |
723 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
724 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
725 | If StartBit is greater than 15, then ASSERT().\r | |
726 | If EndBit is greater than 15, then ASSERT().\r | |
727 | If EndBit is less than StartBit, then ASSERT().\r | |
728 | \r | |
729 | @param Address PCI configuration register to write.\r | |
730 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
731 | Range 0..15.\r | |
732 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
733 | Range 0..15.\r | |
734 | @param AndData The value to AND with the PCI configuration register.\r | |
735 | \r | |
736 | @return The value written back to the PCI configuration register.\r | |
737 | \r | |
738 | **/\r | |
739 | UINT16\r | |
740 | EFIAPI\r | |
741 | S3PciBitFieldAnd16 (\r | |
742 | IN UINTN Address,\r | |
743 | IN UINTN StartBit,\r | |
744 | IN UINTN EndBit,\r | |
745 | IN UINT16 AndData\r | |
746 | )\r | |
747 | {\r | |
748 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAnd16 (Address, StartBit, EndBit, AndData));\r | |
749 | }\r | |
750 | \r | |
751 | /**\r | |
752 | Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a\r | |
753 | bitwise OR, and writes the result back to the bit field in the\r | |
754 | 16-bit port and saves the value in the S3 script to be replayed on S3 resume.\r | |
755 | \r | |
756 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
757 | bitwise AND followed by a bitwise OR between the read result and\r | |
758 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
759 | configuration register specified by Address. The value written to the PCI\r | |
760 | configuration register is returned. This function must guarantee that all PCI\r | |
761 | read and write operations are serialized. Extra left bits in both AndData and\r | |
762 | OrData are stripped.\r | |
763 | \r | |
764 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
765 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
766 | If StartBit is greater than 15, then ASSERT().\r | |
767 | If EndBit is greater than 15, then ASSERT().\r | |
768 | If EndBit is less than StartBit, then ASSERT().\r | |
769 | \r | |
770 | @param Address PCI configuration register to write.\r | |
771 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
772 | Range 0..15.\r | |
773 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
774 | Range 0..15.\r | |
775 | @param AndData The value to AND with the PCI configuration register.\r | |
776 | @param OrData The value to OR with the result of the AND operation.\r | |
777 | \r | |
778 | @return The value written back to the PCI configuration register.\r | |
779 | \r | |
780 | **/\r | |
781 | UINT16\r | |
782 | EFIAPI\r | |
783 | S3PciBitFieldAndThenOr16 (\r | |
784 | IN UINTN Address,\r | |
785 | IN UINTN StartBit,\r | |
786 | IN UINTN EndBit,\r | |
787 | IN UINT16 AndData,\r | |
788 | IN UINT16 OrData\r | |
789 | )\r | |
790 | {\r | |
791 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));\r | |
792 | }\r | |
793 | \r | |
794 | /**\r | |
795 | Saves a 32-bit PCI configuration value to the boot script.\r | |
796 | \r | |
797 | This internal worker function saves a 32-bit PCI configuration value in the S3 script\r | |
798 | to be replayed on S3 resume. \r | |
799 | \r | |
800 | If the saving process fails, then ASSERT().\r | |
801 | \r | |
802 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
803 | Register.\r | |
804 | @param Value The value to write.\r | |
805 | \r | |
806 | @return Value.\r | |
807 | \r | |
808 | **/\r | |
809 | UINT32\r | |
810 | InternalSavePciWrite32ValueToBootScript (\r | |
811 | IN UINTN Address,\r | |
812 | IN UINT32 Value\r | |
813 | )\r | |
814 | {\r | |
815 | InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);\r | |
816 | \r | |
817 | return Value;\r | |
818 | }\r | |
819 | \r | |
820 | /**\r | |
821 | Reads a 32-bit PCI configuration register and saves the value in the S3\r | |
822 | script to be replayed on S3 resume.\r | |
823 | \r | |
824 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
825 | This function must guarantee that all PCI read and write operations are\r | |
826 | serialized.\r | |
827 | \r | |
828 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
829 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
830 | \r | |
831 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
832 | Register.\r | |
833 | \r | |
834 | @return The read value from the PCI configuration register.\r | |
835 | \r | |
836 | **/\r | |
837 | UINT32\r | |
838 | EFIAPI\r | |
839 | S3PciRead32 (\r | |
840 | IN UINTN Address\r | |
841 | )\r | |
842 | {\r | |
843 | return InternalSavePciWrite32ValueToBootScript (Address, PciRead32 (Address));\r | |
844 | }\r | |
845 | \r | |
846 | /**\r | |
847 | Writes a 32-bit PCI configuration register and saves the value in the S3\r | |
848 | script to be replayed on S3 resume.\r | |
849 | \r | |
850 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
851 | value specified by Value. Value is returned. This function must guarantee\r | |
852 | that all PCI read and write operations are serialized.\r | |
853 | \r | |
854 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
855 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
856 | \r | |
857 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
858 | Register.\r | |
859 | @param Value The value to write.\r | |
860 | \r | |
861 | @return The value written to the PCI configuration register.\r | |
862 | \r | |
863 | **/\r | |
864 | UINT32\r | |
865 | EFIAPI\r | |
866 | S3PciWrite32 (\r | |
867 | IN UINTN Address,\r | |
868 | IN UINT32 Value\r | |
869 | )\r | |
870 | {\r | |
871 | return InternalSavePciWrite32ValueToBootScript (Address, PciWrite32 (Address, Value));\r | |
872 | }\r | |
873 | \r | |
874 | /**\r | |
875 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
876 | a 32-bit value and saves the value in the S3 script to be replayed on S3 resume.\r | |
877 | \r | |
878 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
879 | bitwise OR between the read result and the value specified by\r | |
880 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
881 | specified by Address. The value written to the PCI configuration register is\r | |
882 | returned. This function must guarantee that all PCI read and write operations\r | |
883 | are serialized.\r | |
884 | \r | |
885 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
886 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
887 | \r | |
888 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
889 | Register.\r | |
890 | @param OrData The value to OR with the PCI configuration register.\r | |
891 | \r | |
892 | @return The value written back to the PCI configuration register.\r | |
893 | \r | |
894 | **/\r | |
895 | UINT32\r | |
896 | EFIAPI\r | |
897 | S3PciOr32 (\r | |
898 | IN UINTN Address,\r | |
899 | IN UINT32 OrData\r | |
900 | )\r | |
901 | {\r | |
902 | return InternalSavePciWrite32ValueToBootScript (Address, PciOr32 (Address, OrData));\r | |
903 | }\r | |
904 | \r | |
905 | /**\r | |
906 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
907 | value and saves the value in the S3 script to be replayed on S3 resume.\r | |
908 | \r | |
909 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
910 | bitwise AND between the read result and the value specified by AndData, and\r | |
911 | writes the result to the 32-bit PCI configuration register specified by\r | |
912 | Address. The value written to the PCI configuration register is returned.\r | |
913 | This function must guarantee that all PCI read and write operations are\r | |
914 | serialized.\r | |
915 | \r | |
916 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
917 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
918 | \r | |
919 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
920 | Register.\r | |
921 | @param AndData The value to AND with the PCI configuration register.\r | |
922 | \r | |
923 | @return The value written back to the PCI configuration register.\r | |
924 | \r | |
925 | **/\r | |
926 | UINT32\r | |
927 | EFIAPI\r | |
928 | S3PciAnd32 (\r | |
929 | IN UINTN Address,\r | |
930 | IN UINT32 AndData\r | |
931 | )\r | |
932 | {\r | |
933 | return InternalSavePciWrite32ValueToBootScript (Address, PciAnd32 (Address, AndData));\r | |
934 | }\r | |
935 | \r | |
936 | /**\r | |
937 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
938 | value, followed a bitwise OR with another 32-bit value and saves\r | |
939 | the value in the S3 script to be replayed on S3 resume.\r | |
940 | \r | |
941 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
942 | bitwise AND between the read result and the value specified by AndData,\r | |
943 | performs a bitwise OR between the result of the AND operation and\r | |
944 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
945 | configuration register specified by Address. The value written to the PCI\r | |
946 | configuration register is returned. This function must guarantee that all PCI\r | |
947 | read and write operations are serialized.\r | |
948 | \r | |
949 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
950 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
951 | \r | |
952 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
953 | Register.\r | |
954 | @param AndData The value to AND with the PCI configuration register.\r | |
955 | @param OrData The value to OR with the result of the AND operation.\r | |
956 | \r | |
957 | @return The value written back to the PCI configuration register.\r | |
958 | \r | |
959 | **/\r | |
960 | UINT32\r | |
961 | EFIAPI\r | |
962 | S3PciAndThenOr32 (\r | |
963 | IN UINTN Address,\r | |
964 | IN UINT32 AndData,\r | |
965 | IN UINT32 OrData\r | |
966 | )\r | |
967 | {\r | |
968 | return InternalSavePciWrite32ValueToBootScript (Address, PciAndThenOr32 (Address, AndData, OrData));\r | |
969 | }\r | |
970 | \r | |
971 | /**\r | |
972 | Reads a bit field of a PCI configuration register and saves the value in\r | |
973 | the S3 script to be replayed on S3 resume.\r | |
974 | \r | |
975 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
976 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
977 | returned.\r | |
978 | \r | |
979 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
980 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
981 | If StartBit is greater than 31, then ASSERT().\r | |
982 | If EndBit is greater than 31, then ASSERT().\r | |
983 | If EndBit is less than StartBit, then ASSERT().\r | |
984 | \r | |
985 | @param Address PCI configuration register to read.\r | |
986 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
987 | Range 0..31.\r | |
988 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
989 | Range 0..31.\r | |
990 | \r | |
991 | @return The value of the bit field read from the PCI configuration register.\r | |
992 | \r | |
993 | **/\r | |
994 | UINT32\r | |
995 | EFIAPI\r | |
996 | S3PciBitFieldRead32 (\r | |
997 | IN UINTN Address,\r | |
998 | IN UINTN StartBit,\r | |
999 | IN UINTN EndBit\r | |
1000 | )\r | |
1001 | {\r | |
1002 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldRead32 (Address, StartBit, EndBit));\r | |
1003 | }\r | |
1004 | \r | |
1005 | /**\r | |
1006 | Writes a bit field to a PCI configuration register and saves the value in\r | |
1007 | the S3 script to be replayed on S3 resume.\r | |
1008 | \r | |
1009 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1010 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1011 | destination PCI configuration register are preserved. The new value of the\r | |
1012 | 32-bit register is returned.\r | |
1013 | \r | |
1014 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1015 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1016 | If StartBit is greater than 31, then ASSERT().\r | |
1017 | If EndBit is greater than 31, then ASSERT().\r | |
1018 | If EndBit is less than StartBit, then ASSERT().\r | |
1019 | \r | |
1020 | @param Address PCI configuration register to write.\r | |
1021 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1022 | Range 0..31.\r | |
1023 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1024 | Range 0..31.\r | |
1025 | @param Value New value of the bit field.\r | |
1026 | \r | |
1027 | @return The value written back to the PCI configuration register.\r | |
1028 | \r | |
1029 | **/\r | |
1030 | UINT32\r | |
1031 | EFIAPI\r | |
1032 | S3PciBitFieldWrite32 (\r | |
1033 | IN UINTN Address,\r | |
1034 | IN UINTN StartBit,\r | |
1035 | IN UINTN EndBit,\r | |
1036 | IN UINT32 Value\r | |
1037 | )\r | |
1038 | {\r | |
1039 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldWrite32 (Address, StartBit, EndBit, Value));\r | |
1040 | }\r | |
1041 | \r | |
1042 | /**\r | |
1043 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1044 | writes the result back to the bit field in the 32-bit port and saves the value\r | |
1045 | in the S3 script to be replayed on S3 resume.\r | |
1046 | \r | |
1047 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1048 | bitwise OR between the read result and the value specified by\r | |
1049 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1050 | specified by Address. The value written to the PCI configuration register is\r | |
1051 | returned. This function must guarantee that all PCI read and write operations\r | |
1052 | are serialized. Extra left bits in OrData are stripped.\r | |
1053 | \r | |
1054 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1055 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1056 | If StartBit is greater than 31, then ASSERT().\r | |
1057 | If EndBit is greater than 31, then ASSERT().\r | |
1058 | If EndBit is less than StartBit, then ASSERT().\r | |
1059 | \r | |
1060 | @param Address PCI configuration register to write.\r | |
1061 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1062 | Range 0..31.\r | |
1063 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1064 | Range 0..31.\r | |
1065 | @param OrData The value to OR with the PCI configuration register.\r | |
1066 | \r | |
1067 | @return The value written back to the PCI configuration register.\r | |
1068 | \r | |
1069 | **/\r | |
1070 | UINT32\r | |
1071 | EFIAPI\r | |
1072 | S3PciBitFieldOr32 (\r | |
1073 | IN UINTN Address,\r | |
1074 | IN UINTN StartBit,\r | |
1075 | IN UINTN EndBit,\r | |
1076 | IN UINT32 OrData\r | |
1077 | )\r | |
1078 | {\r | |
1079 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldOr32 (Address, StartBit, EndBit, OrData));\r | |
1080 | }\r | |
1081 | \r | |
1082 | /**\r | |
1083 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1084 | AND, and writes the result back to the bit field in the 32-bit register and\r | |
1085 | saves the value in the S3 script to be replayed on S3 resume.\r | |
1086 | \r | |
1087 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1088 | bitwise AND between the read result and the value specified by AndData, and\r | |
1089 | writes the result to the 32-bit PCI configuration register specified by\r | |
1090 | Address. The value written to the PCI configuration register is returned.\r | |
1091 | This function must guarantee that all PCI read and write operations are\r | |
1092 | serialized. Extra left bits in AndData are stripped.\r | |
1093 | \r | |
1094 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1095 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1096 | If StartBit is greater than 31, then ASSERT().\r | |
1097 | If EndBit is greater than 31, then ASSERT().\r | |
1098 | If EndBit is less than StartBit, then ASSERT().\r | |
1099 | \r | |
1100 | @param Address PCI configuration register to write.\r | |
1101 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1102 | Range 0..31.\r | |
1103 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1104 | Range 0..31.\r | |
1105 | @param AndData The value to AND with the PCI configuration register.\r | |
1106 | \r | |
1107 | @return The value written back to the PCI configuration register.\r | |
1108 | \r | |
1109 | **/\r | |
1110 | UINT32\r | |
1111 | EFIAPI\r | |
1112 | S3PciBitFieldAnd32 (\r | |
1113 | IN UINTN Address,\r | |
1114 | IN UINTN StartBit,\r | |
1115 | IN UINTN EndBit,\r | |
1116 | IN UINT32 AndData\r | |
1117 | )\r | |
1118 | {\r | |
1119 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAnd32 (Address, StartBit, EndBit, AndData));\r | |
1120 | }\r | |
1121 | \r | |
1122 | /**\r | |
1123 | Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a\r | |
1124 | bitwise OR, and writes the result back to the bit field in the\r | |
1125 | 32-bit port and saves the value in the S3 script to be replayed on S3 resume.\r | |
1126 | \r | |
1127 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1128 | bitwise AND followed by a bitwise OR between the read result and\r | |
1129 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1130 | configuration register specified by Address. The value written to the PCI\r | |
1131 | configuration register is returned. This function must guarantee that all PCI\r | |
1132 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1133 | OrData are stripped.\r | |
1134 | \r | |
1135 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1136 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1137 | If StartBit is greater than 31, then ASSERT().\r | |
1138 | If EndBit is greater than 31, then ASSERT().\r | |
1139 | If EndBit is less than StartBit, then ASSERT().\r | |
1140 | \r | |
1141 | @param Address PCI configuration register to write.\r | |
1142 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1143 | Range 0..31.\r | |
1144 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1145 | Range 0..31.\r | |
1146 | @param AndData The value to AND with the PCI configuration register.\r | |
1147 | @param OrData The value to OR with the result of the AND operation.\r | |
1148 | \r | |
1149 | @return The value written back to the PCI configuration register.\r | |
1150 | \r | |
1151 | **/\r | |
1152 | UINT32\r | |
1153 | EFIAPI\r | |
1154 | S3PciBitFieldAndThenOr32 (\r | |
1155 | IN UINTN Address,\r | |
1156 | IN UINTN StartBit,\r | |
1157 | IN UINTN EndBit,\r | |
1158 | IN UINT32 AndData,\r | |
1159 | IN UINT32 OrData\r | |
1160 | )\r | |
1161 | {\r | |
1162 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));\r | |
1163 | }\r | |
1164 | \r | |
1165 | /**\r | |
1166 | Reads a range of PCI configuration registers into a caller supplied buffer\r | |
1167 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
1168 | \r | |
1169 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1170 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1171 | configuration registers from a single PCI function to be read. Size is\r | |
1172 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1173 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1174 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1175 | end of the range.\r | |
1176 | \r | |
1177 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1178 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1179 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1180 | \r | |
1181 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1182 | Function and Register.\r | |
1183 | @param Size Size in bytes of the transfer.\r | |
1184 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1185 | \r | |
1186 | @return Size\r | |
1187 | \r | |
1188 | **/\r | |
1189 | UINTN\r | |
1190 | EFIAPI\r | |
1191 | S3PciReadBuffer (\r | |
1192 | IN UINTN StartAddress,\r | |
1193 | IN UINTN Size,\r | |
1194 | OUT VOID *Buffer\r | |
1195 | )\r | |
1196 | {\r | |
1197 | RETURN_STATUS Status;\r | |
1198 | \r | |
1199 | Status = S3BootScriptSavePciCfgWrite (\r | |
1200 | S3BootScriptWidthUint8,\r | |
1201 | PCILIB_TO_COMMON_ADDRESS (StartAddress),\r | |
1202 | PciReadBuffer (StartAddress, Size, Buffer),\r | |
1203 | Buffer\r | |
1204 | );\r | |
1205 | ASSERT (Status == RETURN_SUCCESS);\r | |
1206 | \r | |
1207 | return Size;\r | |
1208 | }\r | |
1209 | \r | |
1210 | /**\r | |
1211 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1212 | configuration space and saves the value in the S3 script to be replayed on S3\r | |
1213 | resume.\r | |
1214 | \r | |
1215 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1216 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1217 | configuration registers from a single PCI function to be written. Size is\r | |
1218 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1219 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1220 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1221 | and the end of the range.\r | |
1222 | \r | |
1223 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1224 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1225 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1226 | \r | |
1227 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1228 | Function and Register.\r | |
1229 | @param Size Size in bytes of the transfer.\r | |
1230 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1231 | \r | |
1232 | @return Size\r | |
1233 | \r | |
1234 | **/\r | |
1235 | UINTN\r | |
1236 | EFIAPI\r | |
1237 | S3PciWriteBuffer (\r | |
1238 | IN UINTN StartAddress,\r | |
1239 | IN UINTN Size,\r | |
1240 | IN VOID *Buffer\r | |
1241 | )\r | |
1242 | {\r | |
1243 | RETURN_STATUS Status;\r | |
1244 | \r | |
1245 | Status = S3BootScriptSavePciCfgWrite (\r | |
1246 | S3BootScriptWidthUint8,\r | |
1247 | PCILIB_TO_COMMON_ADDRESS (StartAddress),\r | |
1248 | PciWriteBuffer (StartAddress, Size, Buffer),\r | |
1249 | Buffer\r | |
1250 | );\r | |
1251 | ASSERT (Status == RETURN_SUCCESS);\r | |
1252 | \r | |
1253 | return Size;\r | |
1254 | }\r |