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fe69ac84 | 1 | /** @file\r |
2 | PCI configuration Library Services that do PCI configuration and also enable\r | |
3 | the PCI operations to be replayed during an S3 resume. This library class\r | |
4 | maps directly on top of the PciLib class. \r | |
5 | \r | |
94952554 | 6 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
fe69ac84 | 7 | \r |
8 | This program and the accompanying materials\r | |
9 | are licensed and made available under the terms and conditions\r | |
10 | of the BSD License which accompanies this distribution. The\r | |
11 | full text of the license may be found at\r | |
12 | http://opensource.org/licenses/bsd-license.php\r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | \r | |
20 | #include <Base.h>\r | |
21 | \r | |
22 | #include <Library/DebugLib.h>\r | |
23 | #include <Library/S3BootScriptLib.h>\r | |
24 | #include <Library/PciLib.h>\r | |
25 | #include <Library/S3PciLib.h>\r | |
26 | \r | |
27 | #define PCILIB_TO_COMMON_ADDRESS(Address) \\r | |
28 | ((UINT64) ((((UINTN) ((Address>>20) & 0xff)) << 24) + (((UINTN) ((Address>>15) & 0x1f)) << 16) + (((UINTN) ((Address>>12) & 0x07)) << 8) + ((UINTN) (Address & 0xfff ))))\r | |
29 | \r | |
30 | /**\r | |
31 | Saves a PCI configuration value to the boot script.\r | |
32 | \r | |
33 | This internal worker function saves a PCI configuration value in\r | |
34 | the S3 script to be replayed on S3 resume. \r | |
35 | \r | |
36 | If the saving process fails, then ASSERT().\r | |
37 | \r | |
38 | @param Width The width of PCI configuration.\r | |
39 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
40 | Register.\r | |
41 | @param Buffer The buffer containing value.\r | |
42 | \r | |
43 | **/\r | |
44 | VOID\r | |
45 | InternalSavePciWriteValueToBootScript (\r | |
46 | IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r | |
47 | IN UINTN Address,\r | |
48 | IN VOID *Buffer\r | |
49 | )\r | |
50 | {\r | |
51 | RETURN_STATUS Status;\r | |
52 | \r | |
53 | Status = S3BootScriptSavePciCfgWrite (\r | |
54 | Width,\r | |
55 | PCILIB_TO_COMMON_ADDRESS(Address),\r | |
56 | 1,\r | |
57 | Buffer\r | |
58 | );\r | |
59 | ASSERT (Status == RETURN_SUCCESS);\r | |
60 | }\r | |
61 | \r | |
62 | /**\r | |
63 | Saves an 8-bit PCI configuration value to the boot script.\r | |
64 | \r | |
65 | This internal worker function saves an 8-bit PCI configuration value in\r | |
66 | the S3 script to be replayed on S3 resume. \r | |
67 | \r | |
68 | If the saving process fails, then ASSERT().\r | |
69 | \r | |
70 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
71 | Register.\r | |
72 | @param Value The value saved to boot script.\r | |
73 | \r | |
74 | @return Value.\r | |
75 | \r | |
76 | **/\r | |
77 | UINT8\r | |
78 | InternalSavePciWrite8ValueToBootScript (\r | |
79 | IN UINTN Address,\r | |
80 | IN UINT8 Value\r | |
81 | )\r | |
82 | {\r | |
83 | InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);\r | |
84 | \r | |
85 | return Value;\r | |
86 | }\r | |
87 | \r | |
88 | /**\r | |
89 | Reads an 8-bit PCI configuration register and saves the value in the S3\r | |
90 | script to be replayed on S3 resume.\r | |
91 | \r | |
92 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
93 | This function must guarantee that all PCI read and write operations are\r | |
94 | serialized.\r | |
95 | \r | |
96 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
97 | \r | |
98 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
99 | Register.\r | |
100 | \r | |
101 | @return The read value from the PCI configuration register.\r | |
102 | \r | |
103 | **/\r | |
104 | UINT8\r | |
105 | EFIAPI\r | |
106 | S3PciRead8 (\r | |
107 | IN UINTN Address\r | |
108 | )\r | |
109 | {\r | |
110 | return InternalSavePciWrite8ValueToBootScript (Address, PciRead8 (Address));\r | |
111 | }\r | |
112 | \r | |
113 | /**\r | |
114 | Writes an 8-bit PCI configuration register and saves the value in the S3\r | |
115 | script to be replayed on S3 resume.\r | |
116 | \r | |
117 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
118 | value specified by Value. Value is returned. This function must guarantee\r | |
119 | that all PCI read and write operations are serialized.\r | |
120 | \r | |
121 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
122 | \r | |
123 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
124 | Register.\r | |
125 | @param Value The value to write.\r | |
126 | \r | |
127 | @return The value written to the PCI configuration register.\r | |
128 | \r | |
129 | **/\r | |
130 | UINT8\r | |
131 | EFIAPI\r | |
132 | S3PciWrite8 (\r | |
133 | IN UINTN Address,\r | |
134 | IN UINT8 Value\r | |
135 | )\r | |
136 | {\r | |
137 | return InternalSavePciWrite8ValueToBootScript (Address, PciWrite8 (Address, Value));\r | |
138 | }\r | |
139 | \r | |
140 | /**\r | |
141 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
142 | an 8-bit value and saves the value in the S3 script to be replayed on S3 resume.\r | |
143 | \r | |
144 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
145 | bitwise OR between the read result and the value specified by\r | |
146 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
147 | specified by Address. The value written to the PCI configuration register is\r | |
148 | returned. This function must guarantee that all PCI read and write operations\r | |
149 | are serialized.\r | |
150 | \r | |
151 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
152 | \r | |
153 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
154 | Register.\r | |
155 | @param OrData The value to OR with the PCI configuration register.\r | |
156 | \r | |
157 | @return The value written back to the PCI configuration register.\r | |
158 | \r | |
159 | **/\r | |
160 | UINT8\r | |
161 | EFIAPI\r | |
162 | S3PciOr8 (\r | |
163 | IN UINTN Address,\r | |
164 | IN UINT8 OrData\r | |
165 | )\r | |
166 | {\r | |
167 | return InternalSavePciWrite8ValueToBootScript (Address, PciOr8 (Address, OrData));\r | |
168 | }\r | |
169 | \r | |
170 | /**\r | |
171 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
172 | value and saves the value in the S3 script to be replayed on S3 resume.\r | |
173 | \r | |
174 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
175 | bitwise AND between the read result and the value specified by AndData, and\r | |
176 | writes the result to the 8-bit PCI configuration register specified by\r | |
177 | Address. The value written to the PCI configuration register is returned.\r | |
178 | This function must guarantee that all PCI read and write operations are\r | |
179 | serialized.\r | |
180 | \r | |
181 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
182 | \r | |
183 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
184 | Register.\r | |
185 | @param AndData The value to AND with the PCI configuration register.\r | |
186 | \r | |
187 | @return The value written back to the PCI configuration register.\r | |
188 | \r | |
189 | **/\r | |
190 | UINT8\r | |
191 | EFIAPI\r | |
192 | S3PciAnd8 (\r | |
193 | IN UINTN Address,\r | |
194 | IN UINT8 AndData\r | |
195 | )\r | |
196 | {\r | |
197 | return InternalSavePciWrite8ValueToBootScript (Address, PciAnd8 (Address, AndData));\r | |
198 | }\r | |
199 | \r | |
200 | /**\r | |
201 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
202 | value, followed a bitwise OR with another 8-bit value and saves\r | |
203 | the value in the S3 script to be replayed on S3 resume.\r | |
204 | \r | |
205 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
206 | bitwise AND between the read result and the value specified by AndData,\r | |
207 | performs a bitwise OR between the result of the AND operation and\r | |
208 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
209 | configuration register specified by Address. The value written to the PCI\r | |
210 | configuration register is returned. This function must guarantee that all PCI\r | |
211 | read and write operations are serialized.\r | |
212 | \r | |
213 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
214 | \r | |
215 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
216 | Register.\r | |
217 | @param AndData The value to AND with the PCI configuration register.\r | |
218 | @param OrData The value to OR with the result of the AND operation.\r | |
219 | \r | |
220 | @return The value written back to the PCI configuration register.\r | |
221 | \r | |
222 | **/\r | |
223 | UINT8\r | |
224 | EFIAPI\r | |
225 | S3PciAndThenOr8 (\r | |
226 | IN UINTN Address,\r | |
227 | IN UINT8 AndData,\r | |
228 | IN UINT8 OrData\r | |
229 | )\r | |
230 | {\r | |
231 | return InternalSavePciWrite8ValueToBootScript (Address, PciAndThenOr8 (Address, AndData, OrData));\r | |
232 | }\r | |
233 | \r | |
234 | /**\r | |
235 | Reads a bit field of a PCI configuration register and saves the value in\r | |
236 | the S3 script to be replayed on S3 resume.\r | |
237 | \r | |
238 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
239 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
240 | returned.\r | |
241 | \r | |
242 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
243 | If StartBit is greater than 7, then ASSERT().\r | |
244 | If EndBit is greater than 7, then ASSERT().\r | |
245 | If EndBit is less than StartBit, then ASSERT().\r | |
246 | \r | |
247 | @param Address PCI configuration register to read.\r | |
248 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
249 | Range 0..7.\r | |
250 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
251 | Range 0..7.\r | |
252 | \r | |
253 | @return The value of the bit field read from the PCI configuration register.\r | |
254 | \r | |
255 | **/\r | |
256 | UINT8\r | |
257 | EFIAPI\r | |
258 | S3PciBitFieldRead8 (\r | |
259 | IN UINTN Address,\r | |
260 | IN UINTN StartBit,\r | |
261 | IN UINTN EndBit\r | |
262 | )\r | |
263 | {\r | |
264 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldRead8 (Address, StartBit, EndBit));\r | |
265 | }\r | |
266 | \r | |
267 | /**\r | |
268 | Writes a bit field to a PCI configuration register and saves the value in\r | |
269 | the S3 script to be replayed on S3 resume.\r | |
270 | \r | |
271 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
272 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
273 | destination PCI configuration register are preserved. The new value of the\r | |
274 | 8-bit register is returned.\r | |
275 | \r | |
276 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
277 | If StartBit is greater than 7, then ASSERT().\r | |
278 | If EndBit is greater than 7, then ASSERT().\r | |
279 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 280 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 281 | \r |
282 | @param Address PCI configuration register to write.\r | |
283 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
284 | Range 0..7.\r | |
285 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
286 | Range 0..7.\r | |
287 | @param Value New value of the bit field.\r | |
288 | \r | |
289 | @return The value written back to the PCI configuration register.\r | |
290 | \r | |
291 | **/\r | |
292 | UINT8\r | |
293 | EFIAPI\r | |
294 | S3PciBitFieldWrite8 (\r | |
295 | IN UINTN Address,\r | |
296 | IN UINTN StartBit,\r | |
297 | IN UINTN EndBit,\r | |
298 | IN UINT8 Value\r | |
299 | )\r | |
300 | {\r | |
301 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldWrite8 (Address, StartBit, EndBit, Value));\r | |
302 | }\r | |
303 | \r | |
304 | /**\r | |
305 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
306 | writes the result back to the bit field in the 8-bit port and saves the value\r | |
307 | in the S3 script to be replayed on S3 resume.\r | |
308 | \r | |
309 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
310 | bitwise OR between the read result and the value specified by\r | |
311 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
312 | specified by Address. The value written to the PCI configuration register is\r | |
313 | returned. This function must guarantee that all PCI read and write operations\r | |
314 | are serialized. Extra left bits in OrData are stripped.\r | |
315 | \r | |
316 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
317 | If StartBit is greater than 7, then ASSERT().\r | |
318 | If EndBit is greater than 7, then ASSERT().\r | |
319 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 320 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 321 | \r |
322 | @param Address PCI configuration register to write.\r | |
323 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
324 | Range 0..7.\r | |
325 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
326 | Range 0..7.\r | |
327 | @param OrData The value to OR with the PCI configuration register.\r | |
328 | \r | |
329 | @return The value written back to the PCI configuration register.\r | |
330 | \r | |
331 | **/\r | |
332 | UINT8\r | |
333 | EFIAPI\r | |
334 | S3PciBitFieldOr8 (\r | |
335 | IN UINTN Address,\r | |
336 | IN UINTN StartBit,\r | |
337 | IN UINTN EndBit,\r | |
338 | IN UINT8 OrData\r | |
339 | )\r | |
340 | {\r | |
341 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldOr8 (Address, StartBit, EndBit, OrData));\r | |
342 | }\r | |
343 | \r | |
344 | /**\r | |
345 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
346 | AND, and writes the result back to the bit field in the 8-bit register and\r | |
347 | saves the value in the S3 script to be replayed on S3 resume.\r | |
348 | \r | |
349 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
350 | bitwise AND between the read result and the value specified by AndData, and\r | |
351 | writes the result to the 8-bit PCI configuration register specified by\r | |
352 | Address. The value written to the PCI configuration register is returned.\r | |
353 | This function must guarantee that all PCI read and write operations are\r | |
354 | serialized. Extra left bits in AndData are stripped.\r | |
355 | \r | |
356 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
357 | If StartBit is greater than 7, then ASSERT().\r | |
358 | If EndBit is greater than 7, then ASSERT().\r | |
359 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 360 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 361 | \r |
362 | @param Address PCI configuration register to write.\r | |
363 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
364 | Range 0..7.\r | |
365 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
366 | Range 0..7.\r | |
367 | @param AndData The value to AND with the PCI configuration register.\r | |
368 | \r | |
369 | @return The value written back to the PCI configuration register.\r | |
370 | \r | |
371 | **/\r | |
372 | UINT8\r | |
373 | EFIAPI\r | |
374 | S3PciBitFieldAnd8 (\r | |
375 | IN UINTN Address,\r | |
376 | IN UINTN StartBit,\r | |
377 | IN UINTN EndBit,\r | |
378 | IN UINT8 AndData\r | |
379 | )\r | |
380 | {\r | |
381 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAnd8 (Address, StartBit, EndBit, AndData));\r | |
382 | }\r | |
383 | \r | |
384 | /**\r | |
385 | Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a\r | |
386 | bitwise OR, and writes the result back to the bit field in the\r | |
387 | 8-bit port and saves the value in the S3 script to be replayed on S3 resume.\r | |
388 | \r | |
389 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
390 | bitwise AND followed by a bitwise OR between the read result and\r | |
391 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
392 | configuration register specified by Address. The value written to the PCI\r | |
393 | configuration register is returned. This function must guarantee that all PCI\r | |
394 | read and write operations are serialized. Extra left bits in both AndData and\r | |
395 | OrData are stripped.\r | |
396 | \r | |
397 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
398 | If StartBit is greater than 7, then ASSERT().\r | |
399 | If EndBit is greater than 7, then ASSERT().\r | |
400 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
401 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
402 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fe69ac84 | 403 | \r |
404 | @param Address PCI configuration register to write.\r | |
405 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
406 | Range 0..7.\r | |
407 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
408 | Range 0..7.\r | |
409 | @param AndData The value to AND with the PCI configuration register.\r | |
410 | @param OrData The value to OR with the result of the AND operation.\r | |
411 | \r | |
412 | @return The value written back to the PCI configuration register.\r | |
413 | \r | |
414 | **/\r | |
415 | UINT8\r | |
416 | EFIAPI\r | |
417 | S3PciBitFieldAndThenOr8 (\r | |
418 | IN UINTN Address,\r | |
419 | IN UINTN StartBit,\r | |
420 | IN UINTN EndBit,\r | |
421 | IN UINT8 AndData,\r | |
422 | IN UINT8 OrData\r | |
423 | )\r | |
424 | {\r | |
425 | return InternalSavePciWrite8ValueToBootScript (Address, PciBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));\r | |
426 | }\r | |
427 | \r | |
428 | /**\r | |
429 | Saves a 16-bit PCI configuration value to the boot script.\r | |
430 | \r | |
431 | This internal worker function saves a 16-bit PCI configuration value in\r | |
432 | the S3 script to be replayed on S3 resume. \r | |
433 | \r | |
434 | If the saving process fails, then ASSERT().\r | |
435 | \r | |
436 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
437 | Register.\r | |
438 | @param Value The value to write.\r | |
439 | \r | |
440 | @return Value.\r | |
441 | \r | |
442 | **/\r | |
443 | UINT16\r | |
444 | InternalSavePciWrite16ValueToBootScript (\r | |
445 | IN UINTN Address,\r | |
446 | IN UINT16 Value\r | |
447 | )\r | |
448 | {\r | |
449 | InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);\r | |
450 | \r | |
451 | return Value;\r | |
452 | }\r | |
453 | \r | |
454 | /**\r | |
455 | Reads a 16-bit PCI configuration register and saves the value in the S3\r | |
456 | script to be replayed on S3 resume.\r | |
457 | \r | |
458 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
459 | This function must guarantee that all PCI read and write operations are\r | |
460 | serialized.\r | |
461 | \r | |
462 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
463 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
464 | \r | |
465 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
466 | Register.\r | |
467 | \r | |
468 | @return The read value from the PCI configuration register.\r | |
469 | \r | |
470 | **/\r | |
471 | UINT16\r | |
472 | EFIAPI\r | |
473 | S3PciRead16 (\r | |
474 | IN UINTN Address\r | |
475 | )\r | |
476 | {\r | |
477 | return InternalSavePciWrite16ValueToBootScript (Address, PciRead16 (Address));\r | |
478 | }\r | |
479 | \r | |
480 | /**\r | |
481 | Writes a 16-bit PCI configuration register and saves the value in the S3\r | |
482 | script to be replayed on S3 resume.\r | |
483 | \r | |
484 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
485 | value specified by Value. Value is returned. This function must guarantee\r | |
486 | that all PCI read and write operations are serialized.\r | |
487 | \r | |
488 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
489 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
490 | \r | |
491 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
492 | Register.\r | |
493 | @param Value The value to write.\r | |
494 | \r | |
495 | @return The value written to the PCI configuration register.\r | |
496 | \r | |
497 | **/\r | |
498 | UINT16\r | |
499 | EFIAPI\r | |
500 | S3PciWrite16 (\r | |
501 | IN UINTN Address,\r | |
502 | IN UINT16 Value\r | |
503 | )\r | |
504 | {\r | |
505 | return InternalSavePciWrite16ValueToBootScript (Address, PciWrite16 (Address, Value));\r | |
506 | }\r | |
507 | \r | |
508 | /**\r | |
509 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
510 | a 16-bit value and saves the value in the S3 script to be replayed on S3 resume.\r | |
511 | \r | |
512 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
513 | bitwise OR between the read result and the value specified by\r | |
514 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
515 | specified by Address. The value written to the PCI configuration register is\r | |
516 | returned. This function must guarantee that all PCI read and write operations\r | |
517 | are serialized.\r | |
518 | \r | |
519 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
520 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
521 | \r | |
522 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
523 | Register.\r | |
524 | @param OrData The value to OR with the PCI configuration register.\r | |
525 | \r | |
526 | @return The value written back to the PCI configuration register.\r | |
527 | \r | |
528 | **/\r | |
529 | UINT16\r | |
530 | EFIAPI\r | |
531 | S3PciOr16 (\r | |
532 | IN UINTN Address,\r | |
533 | IN UINT16 OrData\r | |
534 | )\r | |
535 | {\r | |
536 | return InternalSavePciWrite16ValueToBootScript (Address, PciOr16 (Address, OrData));\r | |
537 | }\r | |
538 | \r | |
539 | /**\r | |
540 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
541 | value and saves the value in the S3 script to be replayed on S3 resume.\r | |
542 | \r | |
543 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
544 | bitwise AND between the read result and the value specified by AndData, and\r | |
545 | writes the result to the 16-bit PCI configuration register specified by\r | |
546 | Address. The value written to the PCI configuration register is returned.\r | |
547 | This function must guarantee that all PCI read and write operations are\r | |
548 | serialized.\r | |
549 | \r | |
550 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
551 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
552 | \r | |
553 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
554 | Register.\r | |
555 | @param AndData The value to AND with the PCI configuration register.\r | |
556 | \r | |
557 | @return The value written back to the PCI configuration register.\r | |
558 | \r | |
559 | **/\r | |
560 | UINT16\r | |
561 | EFIAPI\r | |
562 | S3PciAnd16 (\r | |
563 | IN UINTN Address,\r | |
564 | IN UINT16 AndData\r | |
565 | )\r | |
566 | {\r | |
567 | return InternalSavePciWrite16ValueToBootScript (Address, PciAnd16 (Address, AndData));\r | |
568 | }\r | |
569 | \r | |
570 | /**\r | |
571 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
572 | value, followed a bitwise OR with another 16-bit value and saves\r | |
573 | the value in the S3 script to be replayed on S3 resume.\r | |
574 | \r | |
575 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
576 | bitwise AND between the read result and the value specified by AndData,\r | |
577 | performs a bitwise OR between the result of the AND operation and\r | |
578 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
579 | configuration register specified by Address. The value written to the PCI\r | |
580 | configuration register is returned. This function must guarantee that all PCI\r | |
581 | read and write operations are serialized.\r | |
582 | \r | |
583 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
584 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
585 | \r | |
586 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
587 | Register.\r | |
588 | @param AndData The value to AND with the PCI configuration register.\r | |
589 | @param OrData The value to OR with the result of the AND operation.\r | |
590 | \r | |
591 | @return The value written back to the PCI configuration register.\r | |
592 | \r | |
593 | **/\r | |
594 | UINT16\r | |
595 | EFIAPI\r | |
596 | S3PciAndThenOr16 (\r | |
597 | IN UINTN Address,\r | |
598 | IN UINT16 AndData,\r | |
599 | IN UINT16 OrData\r | |
600 | )\r | |
601 | {\r | |
602 | return InternalSavePciWrite16ValueToBootScript (Address, PciAndThenOr16 (Address, AndData, OrData));\r | |
603 | }\r | |
604 | \r | |
605 | /**\r | |
606 | Reads a bit field of a PCI configuration register and saves the value in\r | |
607 | the S3 script to be replayed on S3 resume.\r | |
608 | \r | |
609 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
610 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
611 | returned.\r | |
612 | \r | |
613 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
614 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
615 | If StartBit is greater than 15, then ASSERT().\r | |
616 | If EndBit is greater than 15, then ASSERT().\r | |
617 | If EndBit is less than StartBit, then ASSERT().\r | |
618 | \r | |
619 | @param Address PCI configuration register to read.\r | |
620 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
621 | Range 0..15.\r | |
622 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
623 | Range 0..15.\r | |
624 | \r | |
625 | @return The value of the bit field read from the PCI configuration register.\r | |
626 | \r | |
627 | **/\r | |
628 | UINT16\r | |
629 | EFIAPI\r | |
630 | S3PciBitFieldRead16 (\r | |
631 | IN UINTN Address,\r | |
632 | IN UINTN StartBit,\r | |
633 | IN UINTN EndBit\r | |
634 | )\r | |
635 | {\r | |
636 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldRead16 (Address, StartBit, EndBit));\r | |
637 | }\r | |
638 | \r | |
639 | /**\r | |
640 | Writes a bit field to a PCI configuration register and saves the value in\r | |
641 | the S3 script to be replayed on S3 resume.\r | |
642 | \r | |
643 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
644 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
645 | destination PCI configuration register are preserved. The new value of the\r | |
646 | 16-bit register is returned.\r | |
647 | \r | |
648 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
649 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
650 | If StartBit is greater than 15, then ASSERT().\r | |
651 | If EndBit is greater than 15, then ASSERT().\r | |
652 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 653 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 654 | \r |
655 | @param Address PCI configuration register to write.\r | |
656 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
657 | Range 0..15.\r | |
658 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
659 | Range 0..15.\r | |
660 | @param Value New value of the bit field.\r | |
661 | \r | |
662 | @return The value written back to the PCI configuration register.\r | |
663 | \r | |
664 | **/\r | |
665 | UINT16\r | |
666 | EFIAPI\r | |
667 | S3PciBitFieldWrite16 (\r | |
668 | IN UINTN Address,\r | |
669 | IN UINTN StartBit,\r | |
670 | IN UINTN EndBit,\r | |
671 | IN UINT16 Value\r | |
672 | )\r | |
673 | {\r | |
674 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldWrite16 (Address, StartBit, EndBit, Value));\r | |
675 | }\r | |
676 | \r | |
677 | /**\r | |
678 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
679 | writes the result back to the bit field in the 16-bit port and saves the value\r | |
680 | in the S3 script to be replayed on S3 resume.\r | |
681 | \r | |
682 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
683 | bitwise OR between the read result and the value specified by\r | |
684 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
685 | specified by Address. The value written to the PCI configuration register is\r | |
686 | returned. This function must guarantee that all PCI read and write operations\r | |
687 | are serialized. Extra left bits in OrData are stripped.\r | |
688 | \r | |
689 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
690 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
691 | If StartBit is greater than 15, then ASSERT().\r | |
692 | If EndBit is greater than 15, then ASSERT().\r | |
693 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 694 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 695 | \r |
696 | @param Address PCI configuration register to write.\r | |
697 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
698 | Range 0..15.\r | |
699 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
700 | Range 0..15.\r | |
701 | @param OrData The value to OR with the PCI configuration register.\r | |
702 | \r | |
703 | @return The value written back to the PCI configuration register.\r | |
704 | \r | |
705 | **/\r | |
706 | UINT16\r | |
707 | EFIAPI\r | |
708 | S3PciBitFieldOr16 (\r | |
709 | IN UINTN Address,\r | |
710 | IN UINTN StartBit,\r | |
711 | IN UINTN EndBit,\r | |
712 | IN UINT16 OrData\r | |
713 | )\r | |
714 | {\r | |
715 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldOr16 (Address, StartBit, EndBit, OrData));\r | |
716 | }\r | |
717 | \r | |
718 | /**\r | |
719 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
720 | AND, and writes the result back to the bit field in the 16-bit register and\r | |
721 | saves the value in the S3 script to be replayed on S3 resume.\r | |
722 | \r | |
723 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
724 | bitwise AND between the read result and the value specified by AndData, and\r | |
725 | writes the result to the 16-bit PCI configuration register specified by\r | |
726 | Address. The value written to the PCI configuration register is returned.\r | |
727 | This function must guarantee that all PCI read and write operations are\r | |
728 | serialized. Extra left bits in AndData are stripped.\r | |
729 | \r | |
730 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
731 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
732 | If StartBit is greater than 15, then ASSERT().\r | |
733 | If EndBit is greater than 15, then ASSERT().\r | |
734 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 735 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 736 | \r |
737 | @param Address PCI configuration register to write.\r | |
738 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
739 | Range 0..15.\r | |
740 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
741 | Range 0..15.\r | |
742 | @param AndData The value to AND with the PCI configuration register.\r | |
743 | \r | |
744 | @return The value written back to the PCI configuration register.\r | |
745 | \r | |
746 | **/\r | |
747 | UINT16\r | |
748 | EFIAPI\r | |
749 | S3PciBitFieldAnd16 (\r | |
750 | IN UINTN Address,\r | |
751 | IN UINTN StartBit,\r | |
752 | IN UINTN EndBit,\r | |
753 | IN UINT16 AndData\r | |
754 | )\r | |
755 | {\r | |
756 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAnd16 (Address, StartBit, EndBit, AndData));\r | |
757 | }\r | |
758 | \r | |
759 | /**\r | |
760 | Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a\r | |
761 | bitwise OR, and writes the result back to the bit field in the\r | |
762 | 16-bit port and saves the value in the S3 script to be replayed on S3 resume.\r | |
763 | \r | |
764 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
765 | bitwise AND followed by a bitwise OR between the read result and\r | |
766 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
767 | configuration register specified by Address. The value written to the PCI\r | |
768 | configuration register is returned. This function must guarantee that all PCI\r | |
769 | read and write operations are serialized. Extra left bits in both AndData and\r | |
770 | OrData are stripped.\r | |
771 | \r | |
772 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
773 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
774 | If StartBit is greater than 15, then ASSERT().\r | |
775 | If EndBit is greater than 15, then ASSERT().\r | |
776 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
777 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
778 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fe69ac84 | 779 | \r |
780 | @param Address PCI configuration register to write.\r | |
781 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
782 | Range 0..15.\r | |
783 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
784 | Range 0..15.\r | |
785 | @param AndData The value to AND with the PCI configuration register.\r | |
786 | @param OrData The value to OR with the result of the AND operation.\r | |
787 | \r | |
788 | @return The value written back to the PCI configuration register.\r | |
789 | \r | |
790 | **/\r | |
791 | UINT16\r | |
792 | EFIAPI\r | |
793 | S3PciBitFieldAndThenOr16 (\r | |
794 | IN UINTN Address,\r | |
795 | IN UINTN StartBit,\r | |
796 | IN UINTN EndBit,\r | |
797 | IN UINT16 AndData,\r | |
798 | IN UINT16 OrData\r | |
799 | )\r | |
800 | {\r | |
801 | return InternalSavePciWrite16ValueToBootScript (Address, PciBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));\r | |
802 | }\r | |
803 | \r | |
804 | /**\r | |
805 | Saves a 32-bit PCI configuration value to the boot script.\r | |
806 | \r | |
807 | This internal worker function saves a 32-bit PCI configuration value in the S3 script\r | |
808 | to be replayed on S3 resume. \r | |
809 | \r | |
810 | If the saving process fails, then ASSERT().\r | |
811 | \r | |
812 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
813 | Register.\r | |
814 | @param Value The value to write.\r | |
815 | \r | |
816 | @return Value.\r | |
817 | \r | |
818 | **/\r | |
819 | UINT32\r | |
820 | InternalSavePciWrite32ValueToBootScript (\r | |
821 | IN UINTN Address,\r | |
822 | IN UINT32 Value\r | |
823 | )\r | |
824 | {\r | |
825 | InternalSavePciWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);\r | |
826 | \r | |
827 | return Value;\r | |
828 | }\r | |
829 | \r | |
830 | /**\r | |
831 | Reads a 32-bit PCI configuration register and saves the value in the S3\r | |
832 | script to be replayed on S3 resume.\r | |
833 | \r | |
834 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
835 | This function must guarantee that all PCI read and write operations are\r | |
836 | serialized.\r | |
837 | \r | |
838 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
839 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
840 | \r | |
841 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
842 | Register.\r | |
843 | \r | |
844 | @return The read value from the PCI configuration register.\r | |
845 | \r | |
846 | **/\r | |
847 | UINT32\r | |
848 | EFIAPI\r | |
849 | S3PciRead32 (\r | |
850 | IN UINTN Address\r | |
851 | )\r | |
852 | {\r | |
853 | return InternalSavePciWrite32ValueToBootScript (Address, PciRead32 (Address));\r | |
854 | }\r | |
855 | \r | |
856 | /**\r | |
857 | Writes a 32-bit PCI configuration register and saves the value in the S3\r | |
858 | script to be replayed on S3 resume.\r | |
859 | \r | |
860 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
861 | value specified by Value. Value is returned. This function must guarantee\r | |
862 | that all PCI read and write operations are serialized.\r | |
863 | \r | |
864 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
865 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
866 | \r | |
867 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
868 | Register.\r | |
869 | @param Value The value to write.\r | |
870 | \r | |
871 | @return The value written to the PCI configuration register.\r | |
872 | \r | |
873 | **/\r | |
874 | UINT32\r | |
875 | EFIAPI\r | |
876 | S3PciWrite32 (\r | |
877 | IN UINTN Address,\r | |
878 | IN UINT32 Value\r | |
879 | )\r | |
880 | {\r | |
881 | return InternalSavePciWrite32ValueToBootScript (Address, PciWrite32 (Address, Value));\r | |
882 | }\r | |
883 | \r | |
884 | /**\r | |
885 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
886 | a 32-bit value and saves the value in the S3 script to be replayed on S3 resume.\r | |
887 | \r | |
888 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
889 | bitwise OR between the read result and the value specified by\r | |
890 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
891 | specified by Address. The value written to the PCI configuration register is\r | |
892 | returned. This function must guarantee that all PCI read and write operations\r | |
893 | are serialized.\r | |
894 | \r | |
895 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
896 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
897 | \r | |
898 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
899 | Register.\r | |
900 | @param OrData The value to OR with the PCI configuration register.\r | |
901 | \r | |
902 | @return The value written back to the PCI configuration register.\r | |
903 | \r | |
904 | **/\r | |
905 | UINT32\r | |
906 | EFIAPI\r | |
907 | S3PciOr32 (\r | |
908 | IN UINTN Address,\r | |
909 | IN UINT32 OrData\r | |
910 | )\r | |
911 | {\r | |
912 | return InternalSavePciWrite32ValueToBootScript (Address, PciOr32 (Address, OrData));\r | |
913 | }\r | |
914 | \r | |
915 | /**\r | |
916 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
917 | value and saves the value in the S3 script to be replayed on S3 resume.\r | |
918 | \r | |
919 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
920 | bitwise AND between the read result and the value specified by AndData, and\r | |
921 | writes the result to the 32-bit PCI configuration register specified by\r | |
922 | Address. The value written to the PCI configuration register is returned.\r | |
923 | This function must guarantee that all PCI read and write operations are\r | |
924 | serialized.\r | |
925 | \r | |
926 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
927 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
928 | \r | |
929 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
930 | Register.\r | |
931 | @param AndData The value to AND with the PCI configuration register.\r | |
932 | \r | |
933 | @return The value written back to the PCI configuration register.\r | |
934 | \r | |
935 | **/\r | |
936 | UINT32\r | |
937 | EFIAPI\r | |
938 | S3PciAnd32 (\r | |
939 | IN UINTN Address,\r | |
940 | IN UINT32 AndData\r | |
941 | )\r | |
942 | {\r | |
943 | return InternalSavePciWrite32ValueToBootScript (Address, PciAnd32 (Address, AndData));\r | |
944 | }\r | |
945 | \r | |
946 | /**\r | |
947 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
948 | value, followed a bitwise OR with another 32-bit value and saves\r | |
949 | the value in the S3 script to be replayed on S3 resume.\r | |
950 | \r | |
951 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
952 | bitwise AND between the read result and the value specified by AndData,\r | |
953 | performs a bitwise OR between the result of the AND operation and\r | |
954 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
955 | configuration register specified by Address. The value written to the PCI\r | |
956 | configuration register is returned. This function must guarantee that all PCI\r | |
957 | read and write operations are serialized.\r | |
958 | \r | |
959 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
960 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
961 | \r | |
962 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
963 | Register.\r | |
964 | @param AndData The value to AND with the PCI configuration register.\r | |
965 | @param OrData The value to OR with the result of the AND operation.\r | |
966 | \r | |
967 | @return The value written back to the PCI configuration register.\r | |
968 | \r | |
969 | **/\r | |
970 | UINT32\r | |
971 | EFIAPI\r | |
972 | S3PciAndThenOr32 (\r | |
973 | IN UINTN Address,\r | |
974 | IN UINT32 AndData,\r | |
975 | IN UINT32 OrData\r | |
976 | )\r | |
977 | {\r | |
978 | return InternalSavePciWrite32ValueToBootScript (Address, PciAndThenOr32 (Address, AndData, OrData));\r | |
979 | }\r | |
980 | \r | |
981 | /**\r | |
982 | Reads a bit field of a PCI configuration register and saves the value in\r | |
983 | the S3 script to be replayed on S3 resume.\r | |
984 | \r | |
985 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
986 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
987 | returned.\r | |
988 | \r | |
989 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
990 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
991 | If StartBit is greater than 31, then ASSERT().\r | |
992 | If EndBit is greater than 31, then ASSERT().\r | |
993 | If EndBit is less than StartBit, then ASSERT().\r | |
994 | \r | |
995 | @param Address PCI configuration register to read.\r | |
996 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
997 | Range 0..31.\r | |
998 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
999 | Range 0..31.\r | |
1000 | \r | |
1001 | @return The value of the bit field read from the PCI configuration register.\r | |
1002 | \r | |
1003 | **/\r | |
1004 | UINT32\r | |
1005 | EFIAPI\r | |
1006 | S3PciBitFieldRead32 (\r | |
1007 | IN UINTN Address,\r | |
1008 | IN UINTN StartBit,\r | |
1009 | IN UINTN EndBit\r | |
1010 | )\r | |
1011 | {\r | |
1012 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldRead32 (Address, StartBit, EndBit));\r | |
1013 | }\r | |
1014 | \r | |
1015 | /**\r | |
1016 | Writes a bit field to a PCI configuration register and saves the value in\r | |
1017 | the S3 script to be replayed on S3 resume.\r | |
1018 | \r | |
1019 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1020 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1021 | destination PCI configuration register are preserved. The new value of the\r | |
1022 | 32-bit register is returned.\r | |
1023 | \r | |
1024 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1025 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1026 | If StartBit is greater than 31, then ASSERT().\r | |
1027 | If EndBit is greater than 31, then ASSERT().\r | |
1028 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1029 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 1030 | \r |
1031 | @param Address PCI configuration register to write.\r | |
1032 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1033 | Range 0..31.\r | |
1034 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1035 | Range 0..31.\r | |
1036 | @param Value New value of the bit field.\r | |
1037 | \r | |
1038 | @return The value written back to the PCI configuration register.\r | |
1039 | \r | |
1040 | **/\r | |
1041 | UINT32\r | |
1042 | EFIAPI\r | |
1043 | S3PciBitFieldWrite32 (\r | |
1044 | IN UINTN Address,\r | |
1045 | IN UINTN StartBit,\r | |
1046 | IN UINTN EndBit,\r | |
1047 | IN UINT32 Value\r | |
1048 | )\r | |
1049 | {\r | |
1050 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldWrite32 (Address, StartBit, EndBit, Value));\r | |
1051 | }\r | |
1052 | \r | |
1053 | /**\r | |
1054 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1055 | writes the result back to the bit field in the 32-bit port and saves the value\r | |
1056 | in the S3 script to be replayed on S3 resume.\r | |
1057 | \r | |
1058 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1059 | bitwise OR between the read result and the value specified by\r | |
1060 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1061 | specified by Address. The value written to the PCI configuration register is\r | |
1062 | returned. This function must guarantee that all PCI read and write operations\r | |
1063 | are serialized. Extra left bits in OrData are stripped.\r | |
1064 | \r | |
1065 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1066 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1067 | If StartBit is greater than 31, then ASSERT().\r | |
1068 | If EndBit is greater than 31, then ASSERT().\r | |
1069 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1070 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 1071 | \r |
1072 | @param Address PCI configuration register to write.\r | |
1073 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1074 | Range 0..31.\r | |
1075 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1076 | Range 0..31.\r | |
1077 | @param OrData The value to OR with the PCI configuration register.\r | |
1078 | \r | |
1079 | @return The value written back to the PCI configuration register.\r | |
1080 | \r | |
1081 | **/\r | |
1082 | UINT32\r | |
1083 | EFIAPI\r | |
1084 | S3PciBitFieldOr32 (\r | |
1085 | IN UINTN Address,\r | |
1086 | IN UINTN StartBit,\r | |
1087 | IN UINTN EndBit,\r | |
1088 | IN UINT32 OrData\r | |
1089 | )\r | |
1090 | {\r | |
1091 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldOr32 (Address, StartBit, EndBit, OrData));\r | |
1092 | }\r | |
1093 | \r | |
1094 | /**\r | |
1095 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1096 | AND, and writes the result back to the bit field in the 32-bit register and\r | |
1097 | saves the value in the S3 script to be replayed on S3 resume.\r | |
1098 | \r | |
1099 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1100 | bitwise AND between the read result and the value specified by AndData, and\r | |
1101 | writes the result to the 32-bit PCI configuration register specified by\r | |
1102 | Address. The value written to the PCI configuration register is returned.\r | |
1103 | This function must guarantee that all PCI read and write operations are\r | |
1104 | serialized. Extra left bits in AndData are stripped.\r | |
1105 | \r | |
1106 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1107 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1108 | If StartBit is greater than 31, then ASSERT().\r | |
1109 | If EndBit is greater than 31, then ASSERT().\r | |
1110 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1111 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fe69ac84 | 1112 | \r |
1113 | @param Address PCI configuration register to write.\r | |
1114 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1115 | Range 0..31.\r | |
1116 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1117 | Range 0..31.\r | |
1118 | @param AndData The value to AND with the PCI configuration register.\r | |
1119 | \r | |
1120 | @return The value written back to the PCI configuration register.\r | |
1121 | \r | |
1122 | **/\r | |
1123 | UINT32\r | |
1124 | EFIAPI\r | |
1125 | S3PciBitFieldAnd32 (\r | |
1126 | IN UINTN Address,\r | |
1127 | IN UINTN StartBit,\r | |
1128 | IN UINTN EndBit,\r | |
1129 | IN UINT32 AndData\r | |
1130 | )\r | |
1131 | {\r | |
1132 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAnd32 (Address, StartBit, EndBit, AndData));\r | |
1133 | }\r | |
1134 | \r | |
1135 | /**\r | |
1136 | Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a\r | |
1137 | bitwise OR, and writes the result back to the bit field in the\r | |
1138 | 32-bit port and saves the value in the S3 script to be replayed on S3 resume.\r | |
1139 | \r | |
1140 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1141 | bitwise AND followed by a bitwise OR between the read result and\r | |
1142 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1143 | configuration register specified by Address. The value written to the PCI\r | |
1144 | configuration register is returned. This function must guarantee that all PCI\r | |
1145 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1146 | OrData are stripped.\r | |
1147 | \r | |
1148 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1149 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1150 | If StartBit is greater than 31, then ASSERT().\r | |
1151 | If EndBit is greater than 31, then ASSERT().\r | |
1152 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1153 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1154 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fe69ac84 | 1155 | \r |
1156 | @param Address PCI configuration register to write.\r | |
1157 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1158 | Range 0..31.\r | |
1159 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1160 | Range 0..31.\r | |
1161 | @param AndData The value to AND with the PCI configuration register.\r | |
1162 | @param OrData The value to OR with the result of the AND operation.\r | |
1163 | \r | |
1164 | @return The value written back to the PCI configuration register.\r | |
1165 | \r | |
1166 | **/\r | |
1167 | UINT32\r | |
1168 | EFIAPI\r | |
1169 | S3PciBitFieldAndThenOr32 (\r | |
1170 | IN UINTN Address,\r | |
1171 | IN UINTN StartBit,\r | |
1172 | IN UINTN EndBit,\r | |
1173 | IN UINT32 AndData,\r | |
1174 | IN UINT32 OrData\r | |
1175 | )\r | |
1176 | {\r | |
1177 | return InternalSavePciWrite32ValueToBootScript (Address, PciBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));\r | |
1178 | }\r | |
1179 | \r | |
1180 | /**\r | |
1181 | Reads a range of PCI configuration registers into a caller supplied buffer\r | |
1182 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
1183 | \r | |
1184 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1185 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1186 | configuration registers from a single PCI function to be read. Size is\r | |
1187 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1188 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1189 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1190 | end of the range.\r | |
1191 | \r | |
1192 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1193 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1194 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1195 | \r | |
1196 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1197 | Function and Register.\r | |
1198 | @param Size Size in bytes of the transfer.\r | |
1199 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1200 | \r | |
1201 | @return Size\r | |
1202 | \r | |
1203 | **/\r | |
1204 | UINTN\r | |
1205 | EFIAPI\r | |
1206 | S3PciReadBuffer (\r | |
1207 | IN UINTN StartAddress,\r | |
1208 | IN UINTN Size,\r | |
1209 | OUT VOID *Buffer\r | |
1210 | )\r | |
1211 | {\r | |
1212 | RETURN_STATUS Status;\r | |
1213 | \r | |
1214 | Status = S3BootScriptSavePciCfgWrite (\r | |
1215 | S3BootScriptWidthUint8,\r | |
1216 | PCILIB_TO_COMMON_ADDRESS (StartAddress),\r | |
1217 | PciReadBuffer (StartAddress, Size, Buffer),\r | |
1218 | Buffer\r | |
1219 | );\r | |
1220 | ASSERT (Status == RETURN_SUCCESS);\r | |
1221 | \r | |
1222 | return Size;\r | |
1223 | }\r | |
1224 | \r | |
1225 | /**\r | |
1226 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1227 | configuration space and saves the value in the S3 script to be replayed on S3\r | |
1228 | resume.\r | |
1229 | \r | |
1230 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1231 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1232 | configuration registers from a single PCI function to be written. Size is\r | |
1233 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1234 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1235 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1236 | and the end of the range.\r | |
1237 | \r | |
1238 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1239 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1240 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1241 | \r | |
1242 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1243 | Function and Register.\r | |
1244 | @param Size Size in bytes of the transfer.\r | |
1245 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1246 | \r | |
1247 | @return Size\r | |
1248 | \r | |
1249 | **/\r | |
1250 | UINTN\r | |
1251 | EFIAPI\r | |
1252 | S3PciWriteBuffer (\r | |
1253 | IN UINTN StartAddress,\r | |
1254 | IN UINTN Size,\r | |
1255 | IN VOID *Buffer\r | |
1256 | )\r | |
1257 | {\r | |
1258 | RETURN_STATUS Status;\r | |
1259 | \r | |
1260 | Status = S3BootScriptSavePciCfgWrite (\r | |
1261 | S3BootScriptWidthUint8,\r | |
1262 | PCILIB_TO_COMMON_ADDRESS (StartAddress),\r | |
1263 | PciWriteBuffer (StartAddress, Size, Buffer),\r | |
1264 | Buffer\r | |
1265 | );\r | |
1266 | ASSERT (Status == RETURN_SUCCESS);\r | |
1267 | \r | |
1268 | return Size;\r | |
1269 | }\r |