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863be5d0 | 1 | /** @file\r |
2 | DXE PCI Library instance layered on top of ESAL services.\r | |
3 | \r | |
94952554 | 4 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
863be5d0 | 5 | This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php.\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #include <PiDxe.h>\r | |
16 | \r | |
17 | #include <Protocol/ExtendedSalServiceClasses.h>\r | |
18 | \r | |
19 | #include <Library/PciLib.h>\r | |
20 | #include <Library/BaseLib.h>\r | |
21 | #include <Library/DebugLib.h>\r | |
22 | #include <Library/ExtendedSalLib.h>\r | |
23 | \r | |
24 | /**\r | |
25 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
26 | only in the low 28 bits.\r | |
27 | \r | |
28 | @param A The address to validate.\r | |
29 | @param M Additional bits to assert to be zero.\r | |
30 | \r | |
31 | **/\r | |
32 | #define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r | |
33 | ASSERT (((A) & (~0xfffffff | (M))) == 0)\r | |
34 | \r | |
35 | /**\r | |
36 | Converts a PCI Library Address to a ESAL PCI Service Address.\r | |
37 | Based on SAL Spec 3.2, there are two SAL PCI Address:\r | |
38 | \r | |
39 | If address type = 0\r | |
40 | Bits 0..7 - Register address\r | |
41 | Bits 8..10 - Function number\r | |
42 | Bits 11..15 - Device number\r | |
43 | Bits 16..23 - Bus number\r | |
44 | Bits 24..31 - PCI segment group\r | |
45 | Bits 32..63 - Reserved (0)\r | |
46 | \r | |
47 | If address type = 1\r | |
48 | Bits 0..7 - Register address\r | |
49 | Bits 8..11 - Extended Register address\r | |
50 | Bits 12..14 - Function number\r | |
51 | Bits 15..19 - Device number\r | |
52 | Bits 20..27 - Bus number\r | |
53 | Bits 28..43 - PCI segment group\r | |
54 | Bits 44..63 - Reserved (0)\r | |
55 | \r | |
56 | @param A The PCI Library Address to convert.\r | |
57 | \r | |
58 | **/\r | |
59 | #define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address) ((((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff))\r | |
60 | #define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address) (Address)\r | |
61 | \r | |
62 | /**\r | |
63 | Check a PCI Library Address is a PCI Compatible Address or not.\r | |
64 | **/\r | |
65 | #define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)\r | |
66 | \r | |
67 | /**\r | |
68 | Internal worker function to read a PCI configuration register.\r | |
69 | \r | |
70 | This function wraps EsalPciConfigRead function of Extended SAL PCI\r | |
71 | Services Class.\r | |
72 | It reads and returns the PCI configuration register specified by Address,\r | |
73 | the width of data is specified by Width.\r | |
74 | \r | |
75 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
76 | Register.\r | |
77 | @param Width Width of data to read\r | |
78 | \r | |
79 | @return The value read from the PCI configuration register.\r | |
80 | \r | |
81 | **/\r | |
82 | UINT32\r | |
83 | DxePciLibEsalReadWorker (\r | |
84 | IN UINTN Address,\r | |
85 | IN UINTN Width\r | |
86 | )\r | |
87 | {\r | |
88 | SAL_RETURN_REGS Return;\r | |
89 | \r | |
90 | if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {\r | |
91 | Return = EsalCall (\r | |
92 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r | |
93 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r | |
94 | SalPciConfigReadFunctionId,\r | |
95 | CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),\r | |
96 | Width,\r | |
97 | EFI_SAL_PCI_COMPATIBLE_ADDRESS,\r | |
98 | 0,\r | |
99 | 0,\r | |
100 | 0,\r | |
101 | 0\r | |
102 | );\r | |
103 | } else {\r | |
104 | Return = EsalCall (\r | |
105 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r | |
106 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r | |
107 | SalPciConfigReadFunctionId,\r | |
108 | CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),\r | |
109 | Width,\r | |
110 | EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,\r | |
111 | 0,\r | |
112 | 0,\r | |
113 | 0,\r | |
114 | 0\r | |
115 | );\r | |
116 | }\r | |
117 | \r | |
118 | return (UINT32) Return.r9;\r | |
119 | }\r | |
120 | \r | |
121 | /**\r | |
122 | Internal worker function to writes a PCI configuration register.\r | |
123 | \r | |
124 | This function wraps EsalPciConfigWrite function of Extended SAL PCI\r | |
125 | Services Class.\r | |
126 | It writes the PCI configuration register specified by Address with the\r | |
a750b4ae | 127 | value specified by Data. The width of data is specified by Width.\r |
863be5d0 | 128 | Data is returned.\r |
129 | \r | |
130 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
131 | Register.\r | |
132 | @param Width Width of data to write\r | |
133 | @param Data The value to write.\r | |
134 | \r | |
135 | @return The value written to the PCI configuration register.\r | |
136 | \r | |
137 | **/\r | |
138 | UINT32\r | |
139 | DxePciLibEsalWriteWorker (\r | |
140 | IN UINTN Address,\r | |
141 | IN UINTN Width,\r | |
142 | IN UINT32 Data\r | |
143 | )\r | |
144 | {\r | |
145 | if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {\r | |
146 | EsalCall (\r | |
147 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r | |
148 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r | |
149 | SalPciConfigWriteFunctionId,\r | |
150 | CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),\r | |
151 | Width,\r | |
152 | Data,\r | |
153 | EFI_SAL_PCI_COMPATIBLE_ADDRESS,\r | |
154 | 0,\r | |
155 | 0,\r | |
156 | 0\r | |
157 | );\r | |
158 | } else {\r | |
159 | EsalCall (\r | |
160 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,\r | |
161 | EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,\r | |
162 | SalPciConfigWriteFunctionId,\r | |
163 | CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),\r | |
164 | Width,\r | |
165 | Data,\r | |
166 | EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,\r | |
167 | 0,\r | |
168 | 0,\r | |
169 | 0\r | |
170 | );\r | |
171 | }\r | |
172 | \r | |
173 | return Data;\r | |
174 | }\r | |
175 | \r | |
176 | /**\r | |
177 | Register a PCI device so PCI configuration registers may be accessed after\r | |
178 | SetVirtualAddressMap().\r | |
179 | \r | |
180 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
181 | \r | |
182 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
183 | Register.\r | |
184 | \r | |
185 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
186 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r | |
187 | after ExitBootServices().\r | |
188 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
189 | at runtime could not be mapped.\r | |
190 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
191 | complete the registration.\r | |
192 | \r | |
193 | **/\r | |
194 | RETURN_STATUS\r | |
195 | EFIAPI\r | |
196 | PciRegisterForRuntimeAccess (\r | |
197 | IN UINTN Address\r | |
198 | )\r | |
199 | {\r | |
200 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
201 | return RETURN_SUCCESS;\r | |
202 | }\r | |
203 | \r | |
204 | /**\r | |
205 | Reads an 8-bit PCI configuration register.\r | |
206 | \r | |
207 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
208 | This function must guarantee that all PCI read and write operations are\r | |
209 | serialized.\r | |
210 | \r | |
211 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
212 | \r | |
213 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
214 | Register.\r | |
215 | \r | |
216 | @return The value read from the PCI configuration register.\r | |
217 | \r | |
218 | **/\r | |
219 | UINT8\r | |
220 | EFIAPI\r | |
221 | PciRead8 (\r | |
222 | IN UINTN Address\r | |
223 | )\r | |
224 | {\r | |
225 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
226 | \r | |
227 | return (UINT8) DxePciLibEsalReadWorker (Address, 1);\r | |
228 | }\r | |
229 | \r | |
230 | /**\r | |
231 | Writes an 8-bit PCI configuration register.\r | |
232 | \r | |
233 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
234 | value specified by Value. Value is returned. This function must guarantee\r | |
235 | that all PCI read and write operations are serialized.\r | |
236 | \r | |
237 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
238 | \r | |
239 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
240 | Register.\r | |
241 | @param Data The value to write.\r | |
242 | \r | |
243 | @return The value written to the PCI configuration register.\r | |
244 | \r | |
245 | **/\r | |
246 | UINT8\r | |
247 | EFIAPI\r | |
248 | PciWrite8 (\r | |
249 | IN UINTN Address,\r | |
250 | IN UINT8 Data\r | |
251 | )\r | |
252 | {\r | |
253 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
254 | \r | |
255 | return (UINT8) DxePciLibEsalWriteWorker (Address, 1, Data);\r | |
256 | }\r | |
257 | \r | |
258 | /**\r | |
259 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
260 | an 8-bit value.\r | |
261 | \r | |
262 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
263 | bitwise OR between the read result and the value specified by\r | |
264 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
265 | specified by Address. The value written to the PCI configuration register is\r | |
266 | returned. This function must guarantee that all PCI read and write operations\r | |
267 | are serialized.\r | |
268 | \r | |
269 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
270 | \r | |
271 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
272 | Register.\r | |
273 | @param OrData The value to OR with the PCI configuration register.\r | |
274 | \r | |
275 | @return The value written back to the PCI configuration register.\r | |
276 | \r | |
277 | **/\r | |
278 | UINT8\r | |
279 | EFIAPI\r | |
280 | PciOr8 (\r | |
281 | IN UINTN Address,\r | |
282 | IN UINT8 OrData\r | |
283 | )\r | |
284 | {\r | |
285 | return PciWrite8 (Address, (UINT8)(PciRead8 (Address) | OrData));\r | |
286 | }\r | |
287 | \r | |
288 | /**\r | |
289 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
290 | value.\r | |
291 | \r | |
292 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
293 | bitwise AND between the read result and the value specified by AndData, and\r | |
294 | writes the result to the 8-bit PCI configuration register specified by\r | |
295 | Address. The value written to the PCI configuration register is returned.\r | |
296 | This function must guarantee that all PCI read and write operations are\r | |
297 | serialized.\r | |
298 | \r | |
299 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
300 | \r | |
301 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
302 | Register.\r | |
303 | @param AndData The value to AND with the PCI configuration register.\r | |
304 | \r | |
305 | @return The value written back to the PCI configuration register.\r | |
306 | \r | |
307 | **/\r | |
308 | UINT8\r | |
309 | EFIAPI\r | |
310 | PciAnd8 (\r | |
311 | IN UINTN Address,\r | |
312 | IN UINT8 AndData\r | |
313 | )\r | |
314 | {\r | |
315 | return PciWrite8 (Address, (UINT8)(PciRead8 (Address) & AndData));\r | |
316 | }\r | |
317 | \r | |
318 | /**\r | |
319 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
320 | value, followed a bitwise OR with another 8-bit value.\r | |
321 | \r | |
322 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
323 | bitwise AND between the read result and the value specified by AndData,\r | |
324 | performs a bitwise OR between the result of the AND operation and\r | |
325 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
326 | configuration register specified by Address. The value written to the PCI\r | |
327 | configuration register is returned. This function must guarantee that all PCI\r | |
328 | read and write operations are serialized.\r | |
329 | \r | |
330 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
331 | \r | |
332 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
333 | Register.\r | |
334 | @param AndData The value to AND with the PCI configuration register.\r | |
335 | @param OrData The value to OR with the result of the AND operation.\r | |
336 | \r | |
337 | @return The value written back to the PCI configuration register.\r | |
338 | \r | |
339 | **/\r | |
340 | UINT8\r | |
341 | EFIAPI\r | |
342 | PciAndThenOr8 (\r | |
343 | IN UINTN Address,\r | |
344 | IN UINT8 AndData,\r | |
345 | IN UINT8 OrData\r | |
346 | )\r | |
347 | {\r | |
348 | return PciWrite8 (Address, (UINT8)((PciRead8 (Address) & AndData) | OrData));\r | |
349 | }\r | |
350 | \r | |
351 | /**\r | |
352 | Reads a bit field of a PCI configuration register.\r | |
353 | \r | |
354 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
355 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
356 | returned.\r | |
357 | \r | |
358 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
359 | If StartBit is greater than 7, then ASSERT().\r | |
360 | If EndBit is greater than 7, then ASSERT().\r | |
361 | If EndBit is less than StartBit, then ASSERT().\r | |
362 | \r | |
363 | @param Address PCI configuration register to read.\r | |
364 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
365 | Range 0..7.\r | |
366 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
367 | Range 0..7.\r | |
368 | \r | |
369 | @return The value of the bit field read from the PCI configuration register.\r | |
370 | \r | |
371 | **/\r | |
372 | UINT8\r | |
373 | EFIAPI\r | |
374 | PciBitFieldRead8 (\r | |
375 | IN UINTN Address,\r | |
376 | IN UINTN StartBit,\r | |
377 | IN UINTN EndBit\r | |
378 | )\r | |
379 | {\r | |
380 | return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r | |
381 | }\r | |
382 | \r | |
383 | /**\r | |
384 | Writes a bit field to a PCI configuration register.\r | |
385 | \r | |
386 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
387 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
388 | destination PCI configuration register are preserved. The new value of the\r | |
389 | 8-bit register is returned.\r | |
390 | \r | |
391 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
392 | If StartBit is greater than 7, then ASSERT().\r | |
393 | If EndBit is greater than 7, then ASSERT().\r | |
394 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 395 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 396 | \r |
397 | @param Address PCI configuration register to write.\r | |
398 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
399 | Range 0..7.\r | |
400 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
401 | Range 0..7.\r | |
402 | @param Value New value of the bit field.\r | |
403 | \r | |
404 | @return The value written back to the PCI configuration register.\r | |
405 | \r | |
406 | **/\r | |
407 | UINT8\r | |
408 | EFIAPI\r | |
409 | PciBitFieldWrite8 (\r | |
410 | IN UINTN Address,\r | |
411 | IN UINTN StartBit,\r | |
412 | IN UINTN EndBit,\r | |
413 | IN UINT8 Value\r | |
414 | )\r | |
415 | {\r | |
416 | return PciWrite8 (\r | |
417 | Address,\r | |
418 | BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)\r | |
419 | );\r | |
420 | }\r | |
421 | \r | |
422 | /**\r | |
423 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
424 | writes the result back to the bit field in the 8-bit port.\r | |
425 | \r | |
426 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
427 | bitwise OR between the read result and the value specified by\r | |
428 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
429 | specified by Address. The value written to the PCI configuration register is\r | |
430 | returned. This function must guarantee that all PCI read and write operations\r | |
431 | are serialized. Extra left bits in OrData are stripped.\r | |
432 | \r | |
433 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
434 | If StartBit is greater than 7, then ASSERT().\r | |
435 | If EndBit is greater than 7, then ASSERT().\r | |
436 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 437 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 438 | \r |
439 | @param Address PCI configuration register to write.\r | |
440 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
441 | Range 0..7.\r | |
442 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
443 | Range 0..7.\r | |
444 | @param OrData The value to OR with the PCI configuration register.\r | |
445 | \r | |
446 | @return The value written back to the PCI configuration register.\r | |
447 | \r | |
448 | **/\r | |
449 | UINT8\r | |
450 | EFIAPI\r | |
451 | PciBitFieldOr8 (\r | |
452 | IN UINTN Address,\r | |
453 | IN UINTN StartBit,\r | |
454 | IN UINTN EndBit,\r | |
455 | IN UINT8 OrData\r | |
456 | )\r | |
457 | {\r | |
458 | return PciWrite8 (\r | |
459 | Address,\r | |
460 | BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)\r | |
461 | );\r | |
462 | }\r | |
463 | \r | |
464 | /**\r | |
465 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
466 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
467 | \r | |
468 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
469 | bitwise AND between the read result and the value specified by AndData, and\r | |
470 | writes the result to the 8-bit PCI configuration register specified by\r | |
471 | Address. The value written to the PCI configuration register is returned.\r | |
472 | This function must guarantee that all PCI read and write operations are\r | |
473 | serialized. Extra left bits in AndData are stripped.\r | |
474 | \r | |
475 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
476 | If StartBit is greater than 7, then ASSERT().\r | |
477 | If EndBit is greater than 7, then ASSERT().\r | |
478 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 479 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 480 | \r |
481 | @param Address PCI configuration register to write.\r | |
482 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
483 | Range 0..7.\r | |
484 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
485 | Range 0..7.\r | |
486 | @param AndData The value to AND with the PCI configuration register.\r | |
487 | \r | |
488 | @return The value written back to the PCI configuration register.\r | |
489 | \r | |
490 | **/\r | |
491 | UINT8\r | |
492 | EFIAPI\r | |
493 | PciBitFieldAnd8 (\r | |
494 | IN UINTN Address,\r | |
495 | IN UINTN StartBit,\r | |
496 | IN UINTN EndBit,\r | |
497 | IN UINT8 AndData\r | |
498 | )\r | |
499 | {\r | |
500 | return PciWrite8 (\r | |
501 | Address,\r | |
502 | BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)\r | |
503 | );\r | |
504 | }\r | |
505 | \r | |
506 | /**\r | |
507 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
508 | bitwise OR, and writes the result back to the bit field in the\r | |
509 | 8-bit port.\r | |
510 | \r | |
511 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
512 | bitwise AND followed by a bitwise OR between the read result and\r | |
513 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
514 | configuration register specified by Address. The value written to the PCI\r | |
515 | configuration register is returned. This function must guarantee that all PCI\r | |
516 | read and write operations are serialized. Extra left bits in both AndData and\r | |
517 | OrData are stripped.\r | |
518 | \r | |
519 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
520 | If StartBit is greater than 7, then ASSERT().\r | |
521 | If EndBit is greater than 7, then ASSERT().\r | |
522 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
523 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
524 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
863be5d0 | 525 | \r |
526 | @param Address PCI configuration register to write.\r | |
527 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
528 | Range 0..7.\r | |
529 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
530 | Range 0..7.\r | |
531 | @param AndData The value to AND with the PCI configuration register.\r | |
532 | @param OrData The value to OR with the result of the AND operation.\r | |
533 | \r | |
534 | @return The value written back to the PCI configuration register.\r | |
535 | \r | |
536 | **/\r | |
537 | UINT8\r | |
538 | EFIAPI\r | |
539 | PciBitFieldAndThenOr8 (\r | |
540 | IN UINTN Address,\r | |
541 | IN UINTN StartBit,\r | |
542 | IN UINTN EndBit,\r | |
543 | IN UINT8 AndData,\r | |
544 | IN UINT8 OrData\r | |
545 | )\r | |
546 | {\r | |
547 | return PciWrite8 (\r | |
548 | Address,\r | |
549 | BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
550 | );\r | |
551 | }\r | |
552 | \r | |
553 | /**\r | |
554 | Reads a 16-bit PCI configuration register.\r | |
555 | \r | |
556 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
557 | This function must guarantee that all PCI read and write operations are\r | |
558 | serialized.\r | |
559 | \r | |
560 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
561 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
562 | \r | |
563 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
564 | Register.\r | |
565 | \r | |
566 | @return The value read from the PCI configuration register.\r | |
567 | \r | |
568 | **/\r | |
569 | UINT16\r | |
570 | EFIAPI\r | |
571 | PciRead16 (\r | |
572 | IN UINTN Address\r | |
573 | )\r | |
574 | {\r | |
575 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
576 | \r | |
577 | return (UINT16) DxePciLibEsalReadWorker (Address, 2);\r | |
578 | }\r | |
579 | \r | |
580 | /**\r | |
581 | Writes a 16-bit PCI configuration register.\r | |
582 | \r | |
583 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
584 | value specified by Value. Value is returned. This function must guarantee\r | |
585 | that all PCI read and write operations are serialized.\r | |
586 | \r | |
587 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
588 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
589 | \r | |
590 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
591 | Register.\r | |
592 | @param Data The value to write.\r | |
593 | \r | |
594 | @return The value written to the PCI configuration register.\r | |
595 | \r | |
596 | **/\r | |
597 | UINT16\r | |
598 | EFIAPI\r | |
599 | PciWrite16 (\r | |
600 | IN UINTN Address,\r | |
601 | IN UINT16 Data\r | |
602 | )\r | |
603 | {\r | |
604 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
605 | \r | |
606 | return (UINT16) DxePciLibEsalWriteWorker (Address, 2, Data);\r | |
607 | }\r | |
608 | \r | |
609 | /**\r | |
610 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
611 | a 16-bit value.\r | |
612 | \r | |
613 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
614 | bitwise OR between the read result and the value specified by\r | |
615 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
616 | specified by Address. The value written to the PCI configuration register is\r | |
617 | returned. This function must guarantee that all PCI read and write operations\r | |
618 | are serialized.\r | |
619 | \r | |
620 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
621 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
622 | \r | |
623 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
624 | Register.\r | |
625 | @param OrData The value to OR with the PCI configuration register.\r | |
626 | \r | |
627 | @return The value written back to the PCI configuration register.\r | |
628 | \r | |
629 | **/\r | |
630 | UINT16\r | |
631 | EFIAPI\r | |
632 | PciOr16 (\r | |
633 | IN UINTN Address,\r | |
634 | IN UINT16 OrData\r | |
635 | )\r | |
636 | {\r | |
637 | return PciWrite16 (Address, (UINT16)(PciRead16 (Address) | OrData));\r | |
638 | }\r | |
639 | \r | |
640 | /**\r | |
641 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
642 | value.\r | |
643 | \r | |
644 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
645 | bitwise AND between the read result and the value specified by AndData, and\r | |
646 | writes the result to the 16-bit PCI configuration register specified by\r | |
647 | Address. The value written to the PCI configuration register is returned.\r | |
648 | This function must guarantee that all PCI read and write operations are\r | |
649 | serialized.\r | |
650 | \r | |
651 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
652 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
653 | \r | |
654 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
655 | Register.\r | |
656 | @param AndData The value to AND with the PCI configuration register.\r | |
657 | \r | |
658 | @return The value written back to the PCI configuration register.\r | |
659 | \r | |
660 | **/\r | |
661 | UINT16\r | |
662 | EFIAPI\r | |
663 | PciAnd16 (\r | |
664 | IN UINTN Address,\r | |
665 | IN UINT16 AndData\r | |
666 | )\r | |
667 | {\r | |
668 | return PciWrite16 (Address, (UINT16)(PciRead16 (Address) & AndData));\r | |
669 | }\r | |
670 | \r | |
671 | /**\r | |
672 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
673 | value, followed a bitwise OR with another 16-bit value.\r | |
674 | \r | |
675 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
676 | bitwise AND between the read result and the value specified by AndData,\r | |
677 | performs a bitwise OR between the result of the AND operation and\r | |
678 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
679 | configuration register specified by Address. The value written to the PCI\r | |
680 | configuration register is returned. This function must guarantee that all PCI\r | |
681 | read and write operations are serialized.\r | |
682 | \r | |
683 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
684 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
685 | \r | |
686 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
687 | Register.\r | |
688 | @param AndData The value to AND with the PCI configuration register.\r | |
689 | @param OrData The value to OR with the result of the AND operation.\r | |
690 | \r | |
691 | @return The value written back to the PCI configuration register.\r | |
692 | \r | |
693 | **/\r | |
694 | UINT16\r | |
695 | EFIAPI\r | |
696 | PciAndThenOr16 (\r | |
697 | IN UINTN Address,\r | |
698 | IN UINT16 AndData,\r | |
699 | IN UINT16 OrData\r | |
700 | )\r | |
701 | {\r | |
702 | return PciWrite16 (Address, (UINT16)((PciRead16 (Address) & AndData) | OrData));\r | |
703 | }\r | |
704 | \r | |
705 | /**\r | |
706 | Reads a bit field of a PCI configuration register.\r | |
707 | \r | |
708 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
709 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
710 | returned.\r | |
711 | \r | |
712 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
713 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
714 | If StartBit is greater than 15, then ASSERT().\r | |
715 | If EndBit is greater than 15, then ASSERT().\r | |
716 | If EndBit is less than StartBit, then ASSERT().\r | |
717 | \r | |
718 | @param Address PCI configuration register to read.\r | |
719 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
720 | Range 0..15.\r | |
721 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
722 | Range 0..15.\r | |
723 | \r | |
724 | @return The value of the bit field read from the PCI configuration register.\r | |
725 | \r | |
726 | **/\r | |
727 | UINT16\r | |
728 | EFIAPI\r | |
729 | PciBitFieldRead16 (\r | |
730 | IN UINTN Address,\r | |
731 | IN UINTN StartBit,\r | |
732 | IN UINTN EndBit\r | |
733 | )\r | |
734 | {\r | |
735 | return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r | |
736 | }\r | |
737 | \r | |
738 | /**\r | |
739 | Writes a bit field to a PCI configuration register.\r | |
740 | \r | |
741 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
742 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
743 | destination PCI configuration register are preserved. The new value of the\r | |
744 | 16-bit register is returned.\r | |
745 | \r | |
746 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
747 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
748 | If StartBit is greater than 15, then ASSERT().\r | |
749 | If EndBit is greater than 15, then ASSERT().\r | |
750 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 751 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 752 | \r |
753 | @param Address PCI configuration register to write.\r | |
754 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
755 | Range 0..15.\r | |
756 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
757 | Range 0..15.\r | |
758 | @param Value New value of the bit field.\r | |
759 | \r | |
760 | @return The value written back to the PCI configuration register.\r | |
761 | \r | |
762 | **/\r | |
763 | UINT16\r | |
764 | EFIAPI\r | |
765 | PciBitFieldWrite16 (\r | |
766 | IN UINTN Address,\r | |
767 | IN UINTN StartBit,\r | |
768 | IN UINTN EndBit,\r | |
769 | IN UINT16 Value\r | |
770 | )\r | |
771 | {\r | |
772 | return PciWrite16 (\r | |
773 | Address,\r | |
774 | BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)\r | |
775 | );\r | |
776 | }\r | |
777 | \r | |
778 | /**\r | |
779 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
780 | writes the result back to the bit field in the 16-bit port.\r | |
781 | \r | |
782 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
783 | bitwise OR between the read result and the value specified by\r | |
784 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
785 | specified by Address. The value written to the PCI configuration register is\r | |
786 | returned. This function must guarantee that all PCI read and write operations\r | |
787 | are serialized. Extra left bits in OrData are stripped.\r | |
788 | \r | |
789 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
790 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
791 | If StartBit is greater than 15, then ASSERT().\r | |
792 | If EndBit is greater than 15, then ASSERT().\r | |
793 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 794 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 795 | \r |
796 | @param Address PCI configuration register to write.\r | |
797 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
798 | Range 0..15.\r | |
799 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
800 | Range 0..15.\r | |
801 | @param OrData The value to OR with the PCI configuration register.\r | |
802 | \r | |
803 | @return The value written back to the PCI configuration register.\r | |
804 | \r | |
805 | **/\r | |
806 | UINT16\r | |
807 | EFIAPI\r | |
808 | PciBitFieldOr16 (\r | |
809 | IN UINTN Address,\r | |
810 | IN UINTN StartBit,\r | |
811 | IN UINTN EndBit,\r | |
812 | IN UINT16 OrData\r | |
813 | )\r | |
814 | {\r | |
815 | return PciWrite16 (\r | |
816 | Address,\r | |
817 | BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)\r | |
818 | );\r | |
819 | }\r | |
820 | \r | |
821 | /**\r | |
822 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
823 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
824 | \r | |
825 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
826 | bitwise AND between the read result and the value specified by AndData, and\r | |
827 | writes the result to the 16-bit PCI configuration register specified by\r | |
828 | Address. The value written to the PCI configuration register is returned.\r | |
829 | This function must guarantee that all PCI read and write operations are\r | |
830 | serialized. Extra left bits in AndData are stripped.\r | |
831 | \r | |
832 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
833 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
834 | If StartBit is greater than 15, then ASSERT().\r | |
835 | If EndBit is greater than 15, then ASSERT().\r | |
836 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 837 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 838 | \r |
839 | @param Address PCI configuration register to write.\r | |
840 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
841 | Range 0..15.\r | |
842 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
843 | Range 0..15.\r | |
844 | @param AndData The value to AND with the PCI configuration register.\r | |
845 | \r | |
846 | @return The value written back to the PCI configuration register.\r | |
847 | \r | |
848 | **/\r | |
849 | UINT16\r | |
850 | EFIAPI\r | |
851 | PciBitFieldAnd16 (\r | |
852 | IN UINTN Address,\r | |
853 | IN UINTN StartBit,\r | |
854 | IN UINTN EndBit,\r | |
855 | IN UINT16 AndData\r | |
856 | )\r | |
857 | {\r | |
858 | return PciWrite16 (\r | |
859 | Address,\r | |
860 | BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)\r | |
861 | );\r | |
862 | }\r | |
863 | \r | |
864 | /**\r | |
865 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
866 | bitwise OR, and writes the result back to the bit field in the\r | |
867 | 16-bit port.\r | |
868 | \r | |
869 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
870 | bitwise AND followed by a bitwise OR between the read result and\r | |
871 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
872 | configuration register specified by Address. The value written to the PCI\r | |
873 | configuration register is returned. This function must guarantee that all PCI\r | |
874 | read and write operations are serialized. Extra left bits in both AndData and\r | |
875 | OrData are stripped.\r | |
876 | \r | |
877 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
878 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
879 | If StartBit is greater than 15, then ASSERT().\r | |
880 | If EndBit is greater than 15, then ASSERT().\r | |
881 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
882 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
883 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
863be5d0 | 884 | \r |
885 | @param Address PCI configuration register to write.\r | |
886 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
887 | Range 0..15.\r | |
888 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
889 | Range 0..15.\r | |
890 | @param AndData The value to AND with the PCI configuration register.\r | |
891 | @param OrData The value to OR with the result of the AND operation.\r | |
892 | \r | |
893 | @return The value written back to the PCI configuration register.\r | |
894 | \r | |
895 | **/\r | |
896 | UINT16\r | |
897 | EFIAPI\r | |
898 | PciBitFieldAndThenOr16 (\r | |
899 | IN UINTN Address,\r | |
900 | IN UINTN StartBit,\r | |
901 | IN UINTN EndBit,\r | |
902 | IN UINT16 AndData,\r | |
903 | IN UINT16 OrData\r | |
904 | )\r | |
905 | {\r | |
906 | return PciWrite16 (\r | |
907 | Address,\r | |
908 | BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
909 | );\r | |
910 | }\r | |
911 | \r | |
912 | /**\r | |
913 | Reads a 32-bit PCI configuration register.\r | |
914 | \r | |
915 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
916 | This function must guarantee that all PCI read and write operations are\r | |
917 | serialized.\r | |
918 | \r | |
919 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
920 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
921 | \r | |
922 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
923 | Register.\r | |
924 | \r | |
925 | @return The value read from the PCI configuration register.\r | |
926 | \r | |
927 | **/\r | |
928 | UINT32\r | |
929 | EFIAPI\r | |
930 | PciRead32 (\r | |
931 | IN UINTN Address\r | |
932 | )\r | |
933 | {\r | |
934 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
935 | \r | |
936 | return DxePciLibEsalReadWorker (Address, 4);\r | |
937 | }\r | |
938 | \r | |
939 | /**\r | |
940 | Writes a 32-bit PCI configuration register.\r | |
941 | \r | |
942 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
943 | value specified by Value. Value is returned. This function must guarantee\r | |
944 | that all PCI read and write operations are serialized.\r | |
945 | \r | |
946 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
947 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
948 | \r | |
949 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
950 | Register.\r | |
951 | @param Data The value to write.\r | |
952 | \r | |
953 | @return The value written to the PCI configuration register.\r | |
954 | \r | |
955 | **/\r | |
956 | UINT32\r | |
957 | EFIAPI\r | |
958 | PciWrite32 (\r | |
959 | IN UINTN Address,\r | |
960 | IN UINT32 Data\r | |
961 | )\r | |
962 | {\r | |
963 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
964 | \r | |
965 | return DxePciLibEsalWriteWorker (Address, 4, Data);\r | |
966 | }\r | |
967 | \r | |
968 | /**\r | |
969 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
970 | a 32-bit value.\r | |
971 | \r | |
972 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
973 | bitwise OR between the read result and the value specified by\r | |
974 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
975 | specified by Address. The value written to the PCI configuration register is\r | |
976 | returned. This function must guarantee that all PCI read and write operations\r | |
977 | are serialized.\r | |
978 | \r | |
979 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
980 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
981 | \r | |
982 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
983 | Register.\r | |
984 | @param OrData The value to OR with the PCI configuration register.\r | |
985 | \r | |
986 | @return The value written back to the PCI configuration register.\r | |
987 | \r | |
988 | **/\r | |
989 | UINT32\r | |
990 | EFIAPI\r | |
991 | PciOr32 (\r | |
992 | IN UINTN Address,\r | |
993 | IN UINT32 OrData\r | |
994 | )\r | |
995 | {\r | |
996 | return PciWrite32 (Address, PciRead32 (Address) | OrData);\r | |
997 | }\r | |
998 | \r | |
999 | /**\r | |
1000 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
1001 | value.\r | |
1002 | \r | |
1003 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1004 | bitwise AND between the read result and the value specified by AndData, and\r | |
1005 | writes the result to the 32-bit PCI configuration register specified by\r | |
1006 | Address. The value written to the PCI configuration register is returned.\r | |
1007 | This function must guarantee that all PCI read and write operations are\r | |
1008 | serialized.\r | |
1009 | \r | |
1010 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1011 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1012 | \r | |
1013 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
1014 | Register.\r | |
1015 | @param AndData The value to AND with the PCI configuration register.\r | |
1016 | \r | |
1017 | @return The value written back to the PCI configuration register.\r | |
1018 | \r | |
1019 | **/\r | |
1020 | UINT32\r | |
1021 | EFIAPI\r | |
1022 | PciAnd32 (\r | |
1023 | IN UINTN Address,\r | |
1024 | IN UINT32 AndData\r | |
1025 | )\r | |
1026 | {\r | |
1027 | return PciWrite32 (Address, PciRead32 (Address) & AndData);\r | |
1028 | }\r | |
1029 | \r | |
1030 | /**\r | |
1031 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
1032 | value, followed a bitwise OR with another 32-bit value.\r | |
1033 | \r | |
1034 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1035 | bitwise AND between the read result and the value specified by AndData,\r | |
1036 | performs a bitwise OR between the result of the AND operation and\r | |
1037 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
1038 | configuration register specified by Address. The value written to the PCI\r | |
1039 | configuration register is returned. This function must guarantee that all PCI\r | |
1040 | read and write operations are serialized.\r | |
1041 | \r | |
1042 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1043 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1044 | \r | |
1045 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
1046 | Register.\r | |
1047 | @param AndData The value to AND with the PCI configuration register.\r | |
1048 | @param OrData The value to OR with the result of the AND operation.\r | |
1049 | \r | |
1050 | @return The value written back to the PCI configuration register.\r | |
1051 | \r | |
1052 | **/\r | |
1053 | UINT32\r | |
1054 | EFIAPI\r | |
1055 | PciAndThenOr32 (\r | |
1056 | IN UINTN Address,\r | |
1057 | IN UINT32 AndData,\r | |
1058 | IN UINT32 OrData\r | |
1059 | )\r | |
1060 | {\r | |
1061 | return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r | |
1062 | }\r | |
1063 | \r | |
1064 | /**\r | |
1065 | Reads a bit field of a PCI configuration register.\r | |
1066 | \r | |
1067 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1068 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1069 | returned.\r | |
1070 | \r | |
1071 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1072 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1073 | If StartBit is greater than 31, then ASSERT().\r | |
1074 | If EndBit is greater than 31, then ASSERT().\r | |
1075 | If EndBit is less than StartBit, then ASSERT().\r | |
1076 | \r | |
1077 | @param Address PCI configuration register to read.\r | |
1078 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1079 | Range 0..31.\r | |
1080 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1081 | Range 0..31.\r | |
1082 | \r | |
1083 | @return The value of the bit field read from the PCI configuration register.\r | |
1084 | \r | |
1085 | **/\r | |
1086 | UINT32\r | |
1087 | EFIAPI\r | |
1088 | PciBitFieldRead32 (\r | |
1089 | IN UINTN Address,\r | |
1090 | IN UINTN StartBit,\r | |
1091 | IN UINTN EndBit\r | |
1092 | )\r | |
1093 | {\r | |
1094 | return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r | |
1095 | }\r | |
1096 | \r | |
1097 | /**\r | |
1098 | Writes a bit field to a PCI configuration register.\r | |
1099 | \r | |
1100 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1101 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1102 | destination PCI configuration register are preserved. The new value of the\r | |
1103 | 32-bit register is returned.\r | |
1104 | \r | |
1105 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1106 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1107 | If StartBit is greater than 31, then ASSERT().\r | |
1108 | If EndBit is greater than 31, then ASSERT().\r | |
1109 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1110 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 1111 | \r |
1112 | @param Address PCI configuration register to write.\r | |
1113 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1114 | Range 0..31.\r | |
1115 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1116 | Range 0..31.\r | |
1117 | @param Value New value of the bit field.\r | |
1118 | \r | |
1119 | @return The value written back to the PCI configuration register.\r | |
1120 | \r | |
1121 | **/\r | |
1122 | UINT32\r | |
1123 | EFIAPI\r | |
1124 | PciBitFieldWrite32 (\r | |
1125 | IN UINTN Address,\r | |
1126 | IN UINTN StartBit,\r | |
1127 | IN UINTN EndBit,\r | |
1128 | IN UINT32 Value\r | |
1129 | )\r | |
1130 | {\r | |
1131 | return PciWrite32 (\r | |
1132 | Address,\r | |
1133 | BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)\r | |
1134 | );\r | |
1135 | }\r | |
1136 | \r | |
1137 | /**\r | |
1138 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1139 | writes the result back to the bit field in the 32-bit port.\r | |
1140 | \r | |
1141 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1142 | bitwise OR between the read result and the value specified by\r | |
1143 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1144 | specified by Address. The value written to the PCI configuration register is\r | |
1145 | returned. This function must guarantee that all PCI read and write operations\r | |
1146 | are serialized. Extra left bits in OrData are stripped.\r | |
1147 | \r | |
1148 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1149 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1150 | If StartBit is greater than 31, then ASSERT().\r | |
1151 | If EndBit is greater than 31, then ASSERT().\r | |
1152 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1153 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 1154 | \r |
1155 | @param Address PCI configuration register to write.\r | |
1156 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1157 | Range 0..31.\r | |
1158 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1159 | Range 0..31.\r | |
1160 | @param OrData The value to OR with the PCI configuration register.\r | |
1161 | \r | |
1162 | @return The value written back to the PCI configuration register.\r | |
1163 | \r | |
1164 | **/\r | |
1165 | UINT32\r | |
1166 | EFIAPI\r | |
1167 | PciBitFieldOr32 (\r | |
1168 | IN UINTN Address,\r | |
1169 | IN UINTN StartBit,\r | |
1170 | IN UINTN EndBit,\r | |
1171 | IN UINT32 OrData\r | |
1172 | )\r | |
1173 | {\r | |
1174 | return PciWrite32 (\r | |
1175 | Address,\r | |
1176 | BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)\r | |
1177 | );\r | |
1178 | }\r | |
1179 | \r | |
1180 | /**\r | |
1181 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1182 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1183 | \r | |
1184 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1185 | bitwise AND between the read result and the value specified by AndData, and\r | |
1186 | writes the result to the 32-bit PCI configuration register specified by\r | |
1187 | Address. The value written to the PCI configuration register is returned.\r | |
1188 | This function must guarantee that all PCI read and write operations are\r | |
1189 | serialized. Extra left bits in AndData are stripped.\r | |
1190 | \r | |
1191 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1192 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1193 | If StartBit is greater than 31, then ASSERT().\r | |
1194 | If EndBit is greater than 31, then ASSERT().\r | |
1195 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1196 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
863be5d0 | 1197 | \r |
1198 | @param Address PCI configuration register to write.\r | |
1199 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1200 | Range 0..31.\r | |
1201 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1202 | Range 0..31.\r | |
1203 | @param AndData The value to AND with the PCI configuration register.\r | |
1204 | \r | |
1205 | @return The value written back to the PCI configuration register.\r | |
1206 | \r | |
1207 | **/\r | |
1208 | UINT32\r | |
1209 | EFIAPI\r | |
1210 | PciBitFieldAnd32 (\r | |
1211 | IN UINTN Address,\r | |
1212 | IN UINTN StartBit,\r | |
1213 | IN UINTN EndBit,\r | |
1214 | IN UINT32 AndData\r | |
1215 | )\r | |
1216 | {\r | |
1217 | return PciWrite32 (\r | |
1218 | Address,\r | |
1219 | BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)\r | |
1220 | );\r | |
1221 | }\r | |
1222 | \r | |
1223 | /**\r | |
1224 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1225 | bitwise OR, and writes the result back to the bit field in the\r | |
1226 | 32-bit port.\r | |
1227 | \r | |
1228 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1229 | bitwise AND followed by a bitwise OR between the read result and\r | |
1230 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1231 | configuration register specified by Address. The value written to the PCI\r | |
1232 | configuration register is returned. This function must guarantee that all PCI\r | |
1233 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1234 | OrData are stripped.\r | |
1235 | \r | |
1236 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1237 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1238 | If StartBit is greater than 31, then ASSERT().\r | |
1239 | If EndBit is greater than 31, then ASSERT().\r | |
1240 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1241 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1242 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
863be5d0 | 1243 | \r |
1244 | @param Address PCI configuration register to write.\r | |
1245 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1246 | Range 0..31.\r | |
1247 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1248 | Range 0..31.\r | |
1249 | @param AndData The value to AND with the PCI configuration register.\r | |
1250 | @param OrData The value to OR with the result of the AND operation.\r | |
1251 | \r | |
1252 | @return The value written back to the PCI configuration register.\r | |
1253 | \r | |
1254 | **/\r | |
1255 | UINT32\r | |
1256 | EFIAPI\r | |
1257 | PciBitFieldAndThenOr32 (\r | |
1258 | IN UINTN Address,\r | |
1259 | IN UINTN StartBit,\r | |
1260 | IN UINTN EndBit,\r | |
1261 | IN UINT32 AndData,\r | |
1262 | IN UINT32 OrData\r | |
1263 | )\r | |
1264 | {\r | |
1265 | return PciWrite32 (\r | |
1266 | Address,\r | |
1267 | BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1268 | );\r | |
1269 | }\r | |
1270 | \r | |
1271 | /**\r | |
1272 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1273 | \r | |
1274 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1275 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1276 | configuration registers from a single PCI function to be read. Size is\r | |
1277 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1278 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1279 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1280 | end of the range.\r | |
1281 | \r | |
1282 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1283 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1284 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1285 | \r | |
1286 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1287 | Function and Register.\r | |
1288 | @param Size Size in bytes of the transfer.\r | |
1289 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1290 | \r | |
1291 | @return Size\r | |
1292 | \r | |
1293 | **/\r | |
1294 | UINTN\r | |
1295 | EFIAPI\r | |
1296 | PciReadBuffer (\r | |
1297 | IN UINTN StartAddress,\r | |
1298 | IN UINTN Size,\r | |
1299 | OUT VOID *Buffer\r | |
1300 | )\r | |
1301 | {\r | |
1302 | UINTN ReturnValue;\r | |
1303 | \r | |
1304 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
1305 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r | |
1306 | \r | |
1307 | if (Size == 0) {\r | |
1308 | return Size;\r | |
1309 | }\r | |
1310 | \r | |
1311 | ASSERT (Buffer != NULL);\r | |
1312 | \r | |
1313 | //\r | |
1314 | // Save Size for return\r | |
1315 | //\r | |
1316 | ReturnValue = Size;\r | |
1317 | \r | |
1318 | if ((StartAddress & 1) != 0) {\r | |
1319 | //\r | |
1320 | // Read a byte if StartAddress is byte aligned\r | |
1321 | //\r | |
1322 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1323 | StartAddress += sizeof (UINT8);\r | |
1324 | Size -= sizeof (UINT8);\r | |
1325 | Buffer = (UINT8*)Buffer + 1;\r | |
1326 | }\r | |
1327 | \r | |
1328 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1329 | //\r | |
1330 | // Read a word if StartAddress is word aligned\r | |
1331 | //\r | |
1332 | *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);\r | |
1333 | StartAddress += sizeof (UINT16);\r | |
1334 | Size -= sizeof (UINT16);\r | |
1335 | Buffer = (UINT16*)Buffer + 1;\r | |
1336 | }\r | |
1337 | \r | |
1338 | while (Size >= sizeof (UINT32)) {\r | |
1339 | //\r | |
1340 | // Read as many double words as possible\r | |
1341 | //\r | |
1342 | *(volatile UINT32 *)Buffer = PciRead32 (StartAddress);\r | |
1343 | StartAddress += sizeof (UINT32);\r | |
1344 | Size -= sizeof (UINT32);\r | |
1345 | Buffer = (UINT32*)Buffer + 1;\r | |
1346 | }\r | |
1347 | \r | |
1348 | if (Size >= sizeof (UINT16)) {\r | |
1349 | //\r | |
1350 | // Read the last remaining word if exist\r | |
1351 | //\r | |
1352 | *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);\r | |
1353 | StartAddress += sizeof (UINT16);\r | |
1354 | Size -= sizeof (UINT16);\r | |
1355 | Buffer = (UINT16*)Buffer + 1;\r | |
1356 | }\r | |
1357 | \r | |
1358 | if (Size >= sizeof (UINT8)) {\r | |
1359 | //\r | |
1360 | // Read the last remaining byte if exist\r | |
1361 | //\r | |
1362 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1363 | }\r | |
1364 | \r | |
1365 | return ReturnValue;\r | |
1366 | }\r | |
1367 | \r | |
1368 | /**\r | |
1369 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1370 | configuration space.\r | |
1371 | \r | |
1372 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1373 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1374 | configuration registers from a single PCI function to be written. Size is\r | |
1375 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1376 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1377 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1378 | and the end of the range.\r | |
1379 | \r | |
1380 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1381 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1382 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1383 | \r | |
1384 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1385 | Function and Register.\r | |
1386 | @param Size Size in bytes of the transfer.\r | |
1387 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1388 | \r | |
1389 | @return Size\r | |
1390 | \r | |
1391 | **/\r | |
1392 | UINTN\r | |
1393 | EFIAPI\r | |
1394 | PciWriteBuffer (\r | |
1395 | IN UINTN StartAddress,\r | |
1396 | IN UINTN Size,\r | |
1397 | IN VOID *Buffer\r | |
1398 | )\r | |
1399 | {\r | |
1400 | UINTN ReturnValue;\r | |
1401 | \r | |
1402 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
1403 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r | |
1404 | \r | |
1405 | if (Size == 0) {\r | |
1406 | return 0;\r | |
1407 | }\r | |
1408 | \r | |
1409 | ASSERT (Buffer != NULL);\r | |
1410 | \r | |
1411 | //\r | |
1412 | // Save Size for return\r | |
1413 | //\r | |
1414 | ReturnValue = Size;\r | |
1415 | \r | |
1416 | if ((StartAddress & 1) != 0) {\r | |
1417 | //\r | |
1418 | // Write a byte if StartAddress is byte aligned\r | |
1419 | //\r | |
1420 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1421 | StartAddress += sizeof (UINT8);\r | |
1422 | Size -= sizeof (UINT8);\r | |
1423 | Buffer = (UINT8*)Buffer + 1;\r | |
1424 | }\r | |
1425 | \r | |
1426 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1427 | //\r | |
1428 | // Write a word if StartAddress is word aligned\r | |
1429 | //\r | |
1430 | PciWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1431 | StartAddress += sizeof (UINT16);\r | |
1432 | Size -= sizeof (UINT16);\r | |
1433 | Buffer = (UINT16*)Buffer + 1;\r | |
1434 | }\r | |
1435 | \r | |
1436 | while (Size >= sizeof (UINT32)) {\r | |
1437 | //\r | |
1438 | // Write as many double words as possible\r | |
1439 | //\r | |
1440 | PciWrite32 (StartAddress, *(UINT32*)Buffer);\r | |
1441 | StartAddress += sizeof (UINT32);\r | |
1442 | Size -= sizeof (UINT32);\r | |
1443 | Buffer = (UINT32*)Buffer + 1;\r | |
1444 | }\r | |
1445 | \r | |
1446 | if (Size >= sizeof (UINT16)) {\r | |
1447 | //\r | |
1448 | // Write the last remaining word if exist\r | |
1449 | //\r | |
1450 | PciWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1451 | StartAddress += sizeof (UINT16);\r | |
1452 | Size -= sizeof (UINT16);\r | |
1453 | Buffer = (UINT16*)Buffer + 1;\r | |
1454 | }\r | |
1455 | \r | |
1456 | if (Size >= sizeof (UINT8)) {\r | |
1457 | //\r | |
1458 | // Write the last remaining byte if exist\r | |
1459 | //\r | |
1460 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1461 | }\r | |
1462 | \r | |
1463 | return ReturnValue;\r | |
1464 | }\r |