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1 | /** @file\r |
2 | Provide common routines used by BasePciSegmentLibSegmentInfo and\r | |
3 | DxeRuntimePciSegmentLibSegmentInfo libraries.\r | |
4 | \r | |
5 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
6 | This program and the accompanying materials are\r | |
7 | licensed and made available under the terms and conditions of\r | |
8 | the BSD License which accompanies this distribution. The full\r | |
9 | text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php.\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include "PciSegmentLibCommon.h"\r | |
18 | \r | |
19 | typedef struct {\r | |
20 | UINT64 Register : 12;\r | |
21 | UINT64 Function : 3;\r | |
22 | UINT64 Device : 5;\r | |
23 | UINT64 Bus : 8;\r | |
24 | UINT64 Reserved1 : 4;\r | |
25 | UINT64 Segment : 16;\r | |
26 | UINT64 Reserved2 : 16;\r | |
27 | } PCI_SEGMENT_LIB_ADDRESS_STRUCTURE;\r | |
28 | \r | |
29 | /**\r | |
30 | Internal function that converts PciSegmentLib format address that encodes the PCI Bus, Device,\r | |
31 | Function and Register to ECAM (Enhanced Configuration Access Mechanism) address.\r | |
32 | \r | |
33 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
34 | Register.\r | |
35 | @param SegmentInfo An array of PCI_SEGMENT_INFO holding the segment information.\r | |
36 | @param Count Number of segments.\r | |
37 | \r | |
38 | @retval ECAM address.\r | |
39 | **/\r | |
40 | UINTN\r | |
41 | PciSegmentLibGetEcamAddress (\r | |
42 | IN UINT64 Address,\r | |
43 | IN CONST PCI_SEGMENT_INFO *SegmentInfo,\r | |
44 | IN UINTN Count\r | |
45 | )\r | |
46 | {\r | |
47 | while (Count != 0) {\r | |
48 | if (SegmentInfo->SegmentNumber == ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Segment) {\r | |
49 | break;\r | |
50 | }\r | |
51 | SegmentInfo++;\r | |
52 | Count--;\r | |
53 | }\r | |
54 | ASSERT (Count != 0);\r | |
55 | ASSERT (\r | |
56 | (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved1 == 0) &&\r | |
57 | (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved2 == 0)\r | |
58 | );\r | |
59 | ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus >= SegmentInfo->StartBusNumber);\r | |
60 | ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus <= SegmentInfo->EndBusNumber);\r | |
61 | \r | |
62 | Address = SegmentInfo->BaseAddress + PCI_ECAM_ADDRESS (\r | |
63 | ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus,\r | |
64 | ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Device,\r | |
65 | ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Function,\r | |
66 | ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Register);\r | |
67 | \r | |
68 | if (sizeof (UINTN) == sizeof (UINT32)) {\r | |
69 | ASSERT (Address < BASE_4GB);\r | |
70 | }\r | |
71 | \r | |
72 | return PciSegmentLibVirtualAddress ((UINTN)Address);\r | |
73 | }\r | |
74 | \r | |
75 | /**\r | |
76 | Reads an 8-bit PCI configuration register.\r | |
77 | \r | |
78 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
79 | This function must guarantee that all PCI read and write operations are serialized.\r | |
80 | \r | |
81 | If any reserved bits in Address are set, then ASSERT().\r | |
82 | \r | |
83 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
84 | \r | |
85 | @return The 8-bit PCI configuration register specified by Address.\r | |
86 | \r | |
87 | **/\r | |
88 | UINT8\r | |
89 | EFIAPI\r | |
90 | PciSegmentRead8 (\r | |
91 | IN UINT64 Address\r | |
92 | )\r | |
93 | {\r | |
94 | UINTN Count;\r | |
95 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
96 | \r | |
97 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
98 | return MmioRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));\r | |
99 | }\r | |
100 | \r | |
101 | /**\r | |
102 | Writes an 8-bit PCI configuration register.\r | |
103 | \r | |
104 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
105 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
106 | \r | |
107 | If any reserved bits in Address are set, then ASSERT().\r | |
108 | \r | |
109 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
110 | @param Value The value to write.\r | |
111 | \r | |
112 | @return The value written to the PCI configuration register.\r | |
113 | \r | |
114 | **/\r | |
115 | UINT8\r | |
116 | EFIAPI\r | |
117 | PciSegmentWrite8 (\r | |
118 | IN UINT64 Address,\r | |
119 | IN UINT8 Value\r | |
120 | )\r | |
121 | {\r | |
122 | UINTN Count;\r | |
123 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
124 | \r | |
125 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
126 | return MmioWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);\r | |
127 | }\r | |
128 | \r | |
129 | /**\r | |
130 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r | |
131 | \r | |
132 | Reads the 8-bit PCI configuration register specified by Address,\r | |
133 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
134 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
135 | The value written to the PCI configuration register is returned.\r | |
136 | This function must guarantee that all PCI read and write operations are serialized.\r | |
137 | \r | |
138 | If any reserved bits in Address are set, then ASSERT().\r | |
139 | \r | |
140 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
141 | @param OrData The value to OR with the PCI configuration register.\r | |
142 | \r | |
143 | @return The value written to the PCI configuration register.\r | |
144 | \r | |
145 | **/\r | |
146 | UINT8\r | |
147 | EFIAPI\r | |
148 | PciSegmentOr8 (\r | |
149 | IN UINT64 Address,\r | |
150 | IN UINT8 OrData\r | |
151 | )\r | |
152 | {\r | |
153 | UINTN Count;\r | |
154 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
155 | \r | |
156 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
157 | return MmioOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);\r | |
158 | }\r | |
159 | \r | |
160 | /**\r | |
161 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r | |
162 | \r | |
163 | Reads the 8-bit PCI configuration register specified by Address,\r | |
164 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
165 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
166 | The value written to the PCI configuration register is returned.\r | |
167 | This function must guarantee that all PCI read and write operations are serialized.\r | |
168 | If any reserved bits in Address are set, then ASSERT().\r | |
169 | \r | |
170 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
171 | @param AndData The value to AND with the PCI configuration register.\r | |
172 | \r | |
173 | @return The value written to the PCI configuration register.\r | |
174 | \r | |
175 | **/\r | |
176 | UINT8\r | |
177 | EFIAPI\r | |
178 | PciSegmentAnd8 (\r | |
179 | IN UINT64 Address,\r | |
180 | IN UINT8 AndData\r | |
181 | )\r | |
182 | {\r | |
183 | UINTN Count;\r | |
184 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
185 | \r | |
186 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
187 | return MmioAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);\r | |
188 | }\r | |
189 | \r | |
190 | /**\r | |
191 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
192 | followed a bitwise OR with another 8-bit value.\r | |
193 | \r | |
194 | Reads the 8-bit PCI configuration register specified by Address,\r | |
195 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
196 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
197 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
198 | The value written to the PCI configuration register is returned.\r | |
199 | This function must guarantee that all PCI read and write operations are serialized.\r | |
200 | \r | |
201 | If any reserved bits in Address are set, then ASSERT().\r | |
202 | \r | |
203 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
204 | @param AndData The value to AND with the PCI configuration register.\r | |
205 | @param OrData The value to OR with the PCI configuration register.\r | |
206 | \r | |
207 | @return The value written to the PCI configuration register.\r | |
208 | \r | |
209 | **/\r | |
210 | UINT8\r | |
211 | EFIAPI\r | |
212 | PciSegmentAndThenOr8 (\r | |
213 | IN UINT64 Address,\r | |
214 | IN UINT8 AndData,\r | |
215 | IN UINT8 OrData\r | |
216 | )\r | |
217 | {\r | |
218 | UINTN Count;\r | |
219 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
220 | \r | |
221 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
222 | return MmioAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);\r | |
223 | }\r | |
224 | \r | |
225 | /**\r | |
226 | Reads a bit field of a PCI configuration register.\r | |
227 | \r | |
228 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
229 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
230 | returned.\r | |
231 | \r | |
232 | If any reserved bits in Address are set, then ASSERT().\r | |
233 | If StartBit is greater than 7, then ASSERT().\r | |
234 | If EndBit is greater than 7, then ASSERT().\r | |
235 | If EndBit is less than StartBit, then ASSERT().\r | |
236 | \r | |
237 | @param Address PCI configuration register to read.\r | |
238 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
239 | Range 0..7.\r | |
240 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
241 | Range 0..7.\r | |
242 | \r | |
243 | @return The value of the bit field read from the PCI configuration register.\r | |
244 | \r | |
245 | **/\r | |
246 | UINT8\r | |
247 | EFIAPI\r | |
248 | PciSegmentBitFieldRead8 (\r | |
249 | IN UINT64 Address,\r | |
250 | IN UINTN StartBit,\r | |
251 | IN UINTN EndBit\r | |
252 | )\r | |
253 | {\r | |
254 | UINTN Count;\r | |
255 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
256 | \r | |
257 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
258 | return MmioBitFieldRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);\r | |
259 | }\r | |
260 | \r | |
261 | /**\r | |
262 | Writes a bit field to a PCI configuration register.\r | |
263 | \r | |
264 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
265 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
266 | destination PCI configuration register are preserved. The new value of the\r | |
267 | 8-bit register is returned.\r | |
268 | \r | |
269 | If any reserved bits in Address are set, then ASSERT().\r | |
270 | If StartBit is greater than 7, then ASSERT().\r | |
271 | If EndBit is greater than 7, then ASSERT().\r | |
272 | If EndBit is less than StartBit, then ASSERT().\r | |
273 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
274 | \r | |
275 | @param Address PCI configuration register to write.\r | |
276 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
277 | Range 0..7.\r | |
278 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
279 | Range 0..7.\r | |
280 | @param Value New value of the bit field.\r | |
281 | \r | |
282 | @return The value written back to the PCI configuration register.\r | |
283 | \r | |
284 | **/\r | |
285 | UINT8\r | |
286 | EFIAPI\r | |
287 | PciSegmentBitFieldWrite8 (\r | |
288 | IN UINT64 Address,\r | |
289 | IN UINTN StartBit,\r | |
290 | IN UINTN EndBit,\r | |
291 | IN UINT8 Value\r | |
292 | )\r | |
293 | {\r | |
294 | UINTN Count;\r | |
295 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
296 | \r | |
297 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
298 | return MmioBitFieldWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);\r | |
299 | }\r | |
300 | \r | |
301 | /**\r | |
302 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
303 | writes the result back to the bit field in the 8-bit port.\r | |
304 | \r | |
305 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
306 | bitwise OR between the read result and the value specified by\r | |
307 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
308 | specified by Address. The value written to the PCI configuration register is\r | |
309 | returned. This function must guarantee that all PCI read and write operations\r | |
310 | are serialized. Extra left bits in OrData are stripped.\r | |
311 | \r | |
312 | If any reserved bits in Address are set, then ASSERT().\r | |
313 | If StartBit is greater than 7, then ASSERT().\r | |
314 | If EndBit is greater than 7, then ASSERT().\r | |
315 | If EndBit is less than StartBit, then ASSERT().\r | |
316 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
317 | \r | |
318 | @param Address PCI configuration register to write.\r | |
319 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
320 | Range 0..7.\r | |
321 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
322 | Range 0..7.\r | |
323 | @param OrData The value to OR with the PCI configuration register.\r | |
324 | \r | |
325 | @return The value written back to the PCI configuration register.\r | |
326 | \r | |
327 | **/\r | |
328 | UINT8\r | |
329 | EFIAPI\r | |
330 | PciSegmentBitFieldOr8 (\r | |
331 | IN UINT64 Address,\r | |
332 | IN UINTN StartBit,\r | |
333 | IN UINTN EndBit,\r | |
334 | IN UINT8 OrData\r | |
335 | )\r | |
336 | {\r | |
337 | UINTN Count;\r | |
338 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
339 | \r | |
340 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
341 | return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);\r | |
342 | }\r | |
343 | \r | |
344 | /**\r | |
345 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
346 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
347 | \r | |
348 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
349 | bitwise AND between the read result and the value specified by AndData, and\r | |
350 | writes the result to the 8-bit PCI configuration register specified by\r | |
351 | Address. The value written to the PCI configuration register is returned.\r | |
352 | This function must guarantee that all PCI read and write operations are\r | |
353 | serialized. Extra left bits in AndData are stripped.\r | |
354 | \r | |
355 | If any reserved bits in Address are set, then ASSERT().\r | |
356 | If StartBit is greater than 7, then ASSERT().\r | |
357 | If EndBit is greater than 7, then ASSERT().\r | |
358 | If EndBit is less than StartBit, then ASSERT().\r | |
359 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
360 | \r | |
361 | @param Address PCI configuration register to write.\r | |
362 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
363 | Range 0..7.\r | |
364 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
365 | Range 0..7.\r | |
366 | @param AndData The value to AND with the PCI configuration register.\r | |
367 | \r | |
368 | @return The value written back to the PCI configuration register.\r | |
369 | \r | |
370 | **/\r | |
371 | UINT8\r | |
372 | EFIAPI\r | |
373 | PciSegmentBitFieldAnd8 (\r | |
374 | IN UINT64 Address,\r | |
375 | IN UINTN StartBit,\r | |
376 | IN UINTN EndBit,\r | |
377 | IN UINT8 AndData\r | |
378 | )\r | |
379 | {\r | |
380 | UINTN Count;\r | |
381 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
382 | \r | |
383 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
7d8e8474 | 384 | return MmioBitFieldAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);\r |
5c9bb86f RN |
385 | }\r |
386 | \r | |
387 | /**\r | |
388 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
389 | bitwise OR, and writes the result back to the bit field in the 8-bit port.\r | |
390 | \r | |
391 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
392 | bitwise AND followed by a bitwise OR between the read result and\r | |
393 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
394 | configuration register specified by Address. The value written to the PCI\r | |
395 | configuration register is returned. This function must guarantee that all PCI\r | |
396 | read and write operations are serialized. Extra left bits in both AndData and\r | |
397 | OrData are stripped.\r | |
398 | \r | |
399 | If any reserved bits in Address are set, then ASSERT().\r | |
400 | If StartBit is greater than 7, then ASSERT().\r | |
401 | If EndBit is greater than 7, then ASSERT().\r | |
402 | If EndBit is less than StartBit, then ASSERT().\r | |
403 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
404 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
405 | \r | |
406 | @param Address PCI configuration register to write.\r | |
407 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
408 | Range 0..7.\r | |
409 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
410 | Range 0..7.\r | |
411 | @param AndData The value to AND with the PCI configuration register.\r | |
412 | @param OrData The value to OR with the result of the AND operation.\r | |
413 | \r | |
414 | @return The value written back to the PCI configuration register.\r | |
415 | \r | |
416 | **/\r | |
417 | UINT8\r | |
418 | EFIAPI\r | |
419 | PciSegmentBitFieldAndThenOr8 (\r | |
420 | IN UINT64 Address,\r | |
421 | IN UINTN StartBit,\r | |
422 | IN UINTN EndBit,\r | |
423 | IN UINT8 AndData,\r | |
424 | IN UINT8 OrData\r | |
425 | )\r | |
426 | {\r | |
427 | UINTN Count;\r | |
428 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
429 | \r | |
430 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
431 | return MmioBitFieldAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);\r | |
432 | }\r | |
433 | \r | |
434 | /**\r | |
435 | Reads a 16-bit PCI configuration register.\r | |
436 | \r | |
437 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
438 | This function must guarantee that all PCI read and write operations are serialized.\r | |
439 | \r | |
440 | If any reserved bits in Address are set, then ASSERT().\r | |
441 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
442 | \r | |
443 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
444 | \r | |
445 | @return The 16-bit PCI configuration register specified by Address.\r | |
446 | \r | |
447 | **/\r | |
448 | UINT16\r | |
449 | EFIAPI\r | |
450 | PciSegmentRead16 (\r | |
451 | IN UINT64 Address\r | |
452 | )\r | |
453 | {\r | |
454 | UINTN Count;\r | |
455 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
456 | \r | |
457 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
458 | return MmioRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));\r | |
459 | }\r | |
460 | \r | |
461 | /**\r | |
462 | Writes a 16-bit PCI configuration register.\r | |
463 | \r | |
464 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
465 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
466 | \r | |
467 | If any reserved bits in Address are set, then ASSERT().\r | |
468 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
469 | \r | |
470 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
471 | @param Value The value to write.\r | |
472 | \r | |
473 | @return The parameter of Value.\r | |
474 | \r | |
475 | **/\r | |
476 | UINT16\r | |
477 | EFIAPI\r | |
478 | PciSegmentWrite16 (\r | |
479 | IN UINT64 Address,\r | |
480 | IN UINT16 Value\r | |
481 | )\r | |
482 | {\r | |
483 | UINTN Count;\r | |
484 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
485 | \r | |
486 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
487 | return MmioWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);\r | |
488 | }\r | |
489 | \r | |
490 | /**\r | |
491 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
492 | a 16-bit value.\r | |
493 | \r | |
494 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
495 | bitwise OR between the read result and the value specified by OrData, and\r | |
496 | writes the result to the 16-bit PCI configuration register specified by Address.\r | |
497 | The value written to the PCI configuration register is returned. This function\r | |
498 | must guarantee that all PCI read and write operations are serialized.\r | |
499 | \r | |
500 | If any reserved bits in Address are set, then ASSERT().\r | |
501 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
502 | \r | |
503 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
504 | Register.\r | |
505 | @param OrData The value to OR with the PCI configuration register.\r | |
506 | \r | |
507 | @return The value written back to the PCI configuration register.\r | |
508 | \r | |
509 | **/\r | |
510 | UINT16\r | |
511 | EFIAPI\r | |
512 | PciSegmentOr16 (\r | |
513 | IN UINT64 Address,\r | |
514 | IN UINT16 OrData\r | |
515 | )\r | |
516 | {\r | |
517 | UINTN Count;\r | |
518 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
519 | \r | |
520 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
521 | return MmioOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);\r | |
522 | }\r | |
523 | \r | |
524 | /**\r | |
525 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r | |
526 | \r | |
527 | Reads the 16-bit PCI configuration register specified by Address,\r | |
528 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
529 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
530 | The value written to the PCI configuration register is returned.\r | |
531 | This function must guarantee that all PCI read and write operations are serialized.\r | |
532 | \r | |
533 | If any reserved bits in Address are set, then ASSERT().\r | |
534 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
535 | \r | |
536 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
537 | @param AndData The value to AND with the PCI configuration register.\r | |
538 | \r | |
539 | @return The value written to the PCI configuration register.\r | |
540 | \r | |
541 | **/\r | |
542 | UINT16\r | |
543 | EFIAPI\r | |
544 | PciSegmentAnd16 (\r | |
545 | IN UINT64 Address,\r | |
546 | IN UINT16 AndData\r | |
547 | )\r | |
548 | {\r | |
549 | UINTN Count;\r | |
550 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
551 | \r | |
552 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
553 | return MmioAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);\r | |
554 | }\r | |
555 | \r | |
556 | /**\r | |
557 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
558 | followed a bitwise OR with another 16-bit value.\r | |
559 | \r | |
560 | Reads the 16-bit PCI configuration register specified by Address,\r | |
561 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
562 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
563 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
564 | The value written to the PCI configuration register is returned.\r | |
565 | This function must guarantee that all PCI read and write operations are serialized.\r | |
566 | \r | |
567 | If any reserved bits in Address are set, then ASSERT().\r | |
568 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
569 | \r | |
570 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
571 | @param AndData The value to AND with the PCI configuration register.\r | |
572 | @param OrData The value to OR with the PCI configuration register.\r | |
573 | \r | |
574 | @return The value written to the PCI configuration register.\r | |
575 | \r | |
576 | **/\r | |
577 | UINT16\r | |
578 | EFIAPI\r | |
579 | PciSegmentAndThenOr16 (\r | |
580 | IN UINT64 Address,\r | |
581 | IN UINT16 AndData,\r | |
582 | IN UINT16 OrData\r | |
583 | )\r | |
584 | {\r | |
585 | UINTN Count;\r | |
586 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
587 | \r | |
588 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
589 | return MmioAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);\r | |
590 | }\r | |
591 | \r | |
592 | /**\r | |
593 | Reads a bit field of a PCI configuration register.\r | |
594 | \r | |
595 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
596 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
597 | returned.\r | |
598 | \r | |
599 | If any reserved bits in Address are set, then ASSERT().\r | |
600 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
601 | If StartBit is greater than 15, then ASSERT().\r | |
602 | If EndBit is greater than 15, then ASSERT().\r | |
603 | If EndBit is less than StartBit, then ASSERT().\r | |
604 | \r | |
605 | @param Address PCI configuration register to read.\r | |
606 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
607 | Range 0..15.\r | |
608 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
609 | Range 0..15.\r | |
610 | \r | |
611 | @return The value of the bit field read from the PCI configuration register.\r | |
612 | \r | |
613 | **/\r | |
614 | UINT16\r | |
615 | EFIAPI\r | |
616 | PciSegmentBitFieldRead16 (\r | |
617 | IN UINT64 Address,\r | |
618 | IN UINTN StartBit,\r | |
619 | IN UINTN EndBit\r | |
620 | )\r | |
621 | {\r | |
622 | UINTN Count;\r | |
623 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
624 | \r | |
625 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
626 | return MmioBitFieldRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);\r | |
627 | }\r | |
628 | \r | |
629 | /**\r | |
630 | Writes a bit field to a PCI configuration register.\r | |
631 | \r | |
632 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
633 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
634 | destination PCI configuration register are preserved. The new value of the\r | |
635 | 16-bit register is returned.\r | |
636 | \r | |
637 | If any reserved bits in Address are set, then ASSERT().\r | |
638 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
639 | If StartBit is greater than 15, then ASSERT().\r | |
640 | If EndBit is greater than 15, then ASSERT().\r | |
641 | If EndBit is less than StartBit, then ASSERT().\r | |
642 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
643 | \r | |
644 | @param Address PCI configuration register to write.\r | |
645 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
646 | Range 0..15.\r | |
647 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
648 | Range 0..15.\r | |
649 | @param Value New value of the bit field.\r | |
650 | \r | |
651 | @return The value written back to the PCI configuration register.\r | |
652 | \r | |
653 | **/\r | |
654 | UINT16\r | |
655 | EFIAPI\r | |
656 | PciSegmentBitFieldWrite16 (\r | |
657 | IN UINT64 Address,\r | |
658 | IN UINTN StartBit,\r | |
659 | IN UINTN EndBit,\r | |
660 | IN UINT16 Value\r | |
661 | )\r | |
662 | {\r | |
663 | UINTN Count;\r | |
664 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
665 | \r | |
666 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
667 | return MmioBitFieldWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);\r | |
668 | }\r | |
669 | \r | |
670 | /**\r | |
671 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r | |
672 | the result back to the bit field in the 16-bit port.\r | |
673 | \r | |
674 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
675 | bitwise OR between the read result and the value specified by\r | |
676 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
677 | specified by Address. The value written to the PCI configuration register is\r | |
678 | returned. This function must guarantee that all PCI read and write operations\r | |
679 | are serialized. Extra left bits in OrData are stripped.\r | |
680 | \r | |
681 | If any reserved bits in Address are set, then ASSERT().\r | |
682 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
683 | If StartBit is greater than 15, then ASSERT().\r | |
684 | If EndBit is greater than 15, then ASSERT().\r | |
685 | If EndBit is less than StartBit, then ASSERT().\r | |
686 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
687 | \r | |
688 | @param Address PCI configuration register to write.\r | |
689 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
690 | Range 0..15.\r | |
691 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
692 | Range 0..15.\r | |
693 | @param OrData The value to OR with the PCI configuration register.\r | |
694 | \r | |
695 | @return The value written back to the PCI configuration register.\r | |
696 | \r | |
697 | **/\r | |
698 | UINT16\r | |
699 | EFIAPI\r | |
700 | PciSegmentBitFieldOr16 (\r | |
701 | IN UINT64 Address,\r | |
702 | IN UINTN StartBit,\r | |
703 | IN UINTN EndBit,\r | |
704 | IN UINT16 OrData\r | |
705 | )\r | |
706 | {\r | |
707 | UINTN Count;\r | |
708 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
709 | \r | |
710 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
711 | return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);\r | |
712 | }\r | |
713 | \r | |
714 | /**\r | |
715 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
716 | AND, writes the result back to the bit field in the 16-bit register.\r | |
717 | \r | |
718 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
719 | bitwise AND between the read result and the value specified by AndData, and\r | |
720 | writes the result to the 16-bit PCI configuration register specified by\r | |
721 | Address. The value written to the PCI configuration register is returned.\r | |
722 | This function must guarantee that all PCI read and write operations are\r | |
723 | serialized. Extra left bits in AndData are stripped.\r | |
724 | \r | |
725 | If any reserved bits in Address are set, then ASSERT().\r | |
726 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
727 | If StartBit is greater than 15, then ASSERT().\r | |
728 | If EndBit is greater than 15, then ASSERT().\r | |
729 | If EndBit is less than StartBit, then ASSERT().\r | |
730 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
731 | \r | |
732 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
733 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
734 | Range 0..15.\r | |
735 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
736 | Range 0..15.\r | |
737 | @param AndData The value to AND with the PCI configuration register.\r | |
738 | \r | |
739 | @return The value written back to the PCI configuration register.\r | |
740 | \r | |
741 | **/\r | |
742 | UINT16\r | |
743 | EFIAPI\r | |
744 | PciSegmentBitFieldAnd16 (\r | |
745 | IN UINT64 Address,\r | |
746 | IN UINTN StartBit,\r | |
747 | IN UINTN EndBit,\r | |
748 | IN UINT16 AndData\r | |
749 | )\r | |
750 | {\r | |
751 | UINTN Count;\r | |
752 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
753 | \r | |
754 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
7d8e8474 | 755 | return MmioBitFieldAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);\r |
5c9bb86f RN |
756 | }\r |
757 | \r | |
758 | /**\r | |
759 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
760 | bitwise OR, and writes the result back to the bit field in the\r | |
761 | 16-bit port.\r | |
762 | \r | |
763 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
764 | bitwise AND followed by a bitwise OR between the read result and\r | |
765 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
766 | configuration register specified by Address. The value written to the PCI\r | |
767 | configuration register is returned. This function must guarantee that all PCI\r | |
768 | read and write operations are serialized. Extra left bits in both AndData and\r | |
769 | OrData are stripped.\r | |
770 | \r | |
771 | If any reserved bits in Address are set, then ASSERT().\r | |
772 | If StartBit is greater than 15, then ASSERT().\r | |
773 | If EndBit is greater than 15, then ASSERT().\r | |
774 | If EndBit is less than StartBit, then ASSERT().\r | |
775 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
776 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
777 | \r | |
778 | @param Address PCI configuration register to write.\r | |
779 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
780 | Range 0..15.\r | |
781 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
782 | Range 0..15.\r | |
783 | @param AndData The value to AND with the PCI configuration register.\r | |
784 | @param OrData The value to OR with the result of the AND operation.\r | |
785 | \r | |
786 | @return The value written back to the PCI configuration register.\r | |
787 | \r | |
788 | **/\r | |
789 | UINT16\r | |
790 | EFIAPI\r | |
791 | PciSegmentBitFieldAndThenOr16 (\r | |
792 | IN UINT64 Address,\r | |
793 | IN UINTN StartBit,\r | |
794 | IN UINTN EndBit,\r | |
795 | IN UINT16 AndData,\r | |
796 | IN UINT16 OrData\r | |
797 | )\r | |
798 | {\r | |
799 | UINTN Count;\r | |
800 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
801 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
802 | return MmioBitFieldAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);\r | |
803 | }\r | |
804 | \r | |
805 | /**\r | |
806 | Reads a 32-bit PCI configuration register.\r | |
807 | \r | |
808 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
809 | This function must guarantee that all PCI read and write operations are serialized.\r | |
810 | \r | |
811 | If any reserved bits in Address are set, then ASSERT().\r | |
812 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
813 | \r | |
814 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
815 | \r | |
816 | @return The 32-bit PCI configuration register specified by Address.\r | |
817 | \r | |
818 | **/\r | |
819 | UINT32\r | |
820 | EFIAPI\r | |
821 | PciSegmentRead32 (\r | |
822 | IN UINT64 Address\r | |
823 | )\r | |
824 | {\r | |
825 | UINTN Count;\r | |
826 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
827 | \r | |
828 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
829 | return MmioRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));\r | |
830 | }\r | |
831 | \r | |
832 | /**\r | |
833 | Writes a 32-bit PCI configuration register.\r | |
834 | \r | |
835 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
836 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
837 | \r | |
838 | If any reserved bits in Address are set, then ASSERT().\r | |
839 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
840 | \r | |
841 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
842 | @param Value The value to write.\r | |
843 | \r | |
844 | @return The parameter of Value.\r | |
845 | \r | |
846 | **/\r | |
847 | UINT32\r | |
848 | EFIAPI\r | |
849 | PciSegmentWrite32 (\r | |
850 | IN UINT64 Address,\r | |
851 | IN UINT32 Value\r | |
852 | )\r | |
853 | {\r | |
854 | UINTN Count;\r | |
855 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
856 | \r | |
857 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
858 | return MmioWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);\r | |
859 | }\r | |
860 | \r | |
861 | /**\r | |
862 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r | |
863 | \r | |
864 | Reads the 32-bit PCI configuration register specified by Address,\r | |
865 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
866 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
867 | The value written to the PCI configuration register is returned.\r | |
868 | This function must guarantee that all PCI read and write operations are serialized.\r | |
869 | \r | |
870 | If any reserved bits in Address are set, then ASSERT().\r | |
871 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
872 | \r | |
873 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
874 | @param OrData The value to OR with the PCI configuration register.\r | |
875 | \r | |
876 | @return The value written to the PCI configuration register.\r | |
877 | \r | |
878 | **/\r | |
879 | UINT32\r | |
880 | EFIAPI\r | |
881 | PciSegmentOr32 (\r | |
882 | IN UINT64 Address,\r | |
883 | IN UINT32 OrData\r | |
884 | )\r | |
885 | {\r | |
886 | UINTN Count;\r | |
887 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
888 | \r | |
889 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
890 | return MmioOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);\r | |
891 | }\r | |
892 | \r | |
893 | /**\r | |
894 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r | |
895 | \r | |
896 | Reads the 32-bit PCI configuration register specified by Address,\r | |
897 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
898 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
899 | The value written to the PCI configuration register is returned.\r | |
900 | This function must guarantee that all PCI read and write operations are serialized.\r | |
901 | \r | |
902 | If any reserved bits in Address are set, then ASSERT().\r | |
903 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
904 | \r | |
905 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
906 | @param AndData The value to AND with the PCI configuration register.\r | |
907 | \r | |
908 | @return The value written to the PCI configuration register.\r | |
909 | \r | |
910 | **/\r | |
911 | UINT32\r | |
912 | EFIAPI\r | |
913 | PciSegmentAnd32 (\r | |
914 | IN UINT64 Address,\r | |
915 | IN UINT32 AndData\r | |
916 | )\r | |
917 | {\r | |
918 | UINTN Count;\r | |
919 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
920 | \r | |
921 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
922 | return MmioAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);\r | |
923 | }\r | |
924 | \r | |
925 | /**\r | |
926 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
927 | followed a bitwise OR with another 32-bit value.\r | |
928 | \r | |
929 | Reads the 32-bit PCI configuration register specified by Address,\r | |
930 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
931 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
932 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
933 | The value written to the PCI configuration register is returned.\r | |
934 | This function must guarantee that all PCI read and write operations are serialized.\r | |
935 | \r | |
936 | If any reserved bits in Address are set, then ASSERT().\r | |
937 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
938 | \r | |
939 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
940 | @param AndData The value to AND with the PCI configuration register.\r | |
941 | @param OrData The value to OR with the PCI configuration register.\r | |
942 | \r | |
943 | @return The value written to the PCI configuration register.\r | |
944 | \r | |
945 | **/\r | |
946 | UINT32\r | |
947 | EFIAPI\r | |
948 | PciSegmentAndThenOr32 (\r | |
949 | IN UINT64 Address,\r | |
950 | IN UINT32 AndData,\r | |
951 | IN UINT32 OrData\r | |
952 | )\r | |
953 | {\r | |
954 | UINTN Count;\r | |
955 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
956 | \r | |
957 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
958 | return MmioAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);\r | |
959 | }\r | |
960 | \r | |
961 | /**\r | |
962 | Reads a bit field of a PCI configuration register.\r | |
963 | \r | |
964 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
965 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
966 | returned.\r | |
967 | \r | |
968 | If any reserved bits in Address are set, then ASSERT().\r | |
969 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
970 | If StartBit is greater than 31, then ASSERT().\r | |
971 | If EndBit is greater than 31, then ASSERT().\r | |
972 | If EndBit is less than StartBit, then ASSERT().\r | |
973 | \r | |
974 | @param Address PCI configuration register to read.\r | |
975 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
976 | Range 0..31.\r | |
977 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
978 | Range 0..31.\r | |
979 | \r | |
980 | @return The value of the bit field read from the PCI configuration register.\r | |
981 | \r | |
982 | **/\r | |
983 | UINT32\r | |
984 | EFIAPI\r | |
985 | PciSegmentBitFieldRead32 (\r | |
986 | IN UINT64 Address,\r | |
987 | IN UINTN StartBit,\r | |
988 | IN UINTN EndBit\r | |
989 | )\r | |
990 | {\r | |
991 | UINTN Count;\r | |
992 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
993 | \r | |
994 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
995 | return MmioBitFieldRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);\r | |
996 | }\r | |
997 | \r | |
998 | /**\r | |
999 | Writes a bit field to a PCI configuration register.\r | |
1000 | \r | |
1001 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1002 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1003 | destination PCI configuration register are preserved. The new value of the\r | |
1004 | 32-bit register is returned.\r | |
1005 | \r | |
1006 | If any reserved bits in Address are set, then ASSERT().\r | |
1007 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1008 | If StartBit is greater than 31, then ASSERT().\r | |
1009 | If EndBit is greater than 31, then ASSERT().\r | |
1010 | If EndBit is less than StartBit, then ASSERT().\r | |
1011 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1012 | \r | |
1013 | @param Address PCI configuration register to write.\r | |
1014 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1015 | Range 0..31.\r | |
1016 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1017 | Range 0..31.\r | |
1018 | @param Value New value of the bit field.\r | |
1019 | \r | |
1020 | @return The value written back to the PCI configuration register.\r | |
1021 | \r | |
1022 | **/\r | |
1023 | UINT32\r | |
1024 | EFIAPI\r | |
1025 | PciSegmentBitFieldWrite32 (\r | |
1026 | IN UINT64 Address,\r | |
1027 | IN UINTN StartBit,\r | |
1028 | IN UINTN EndBit,\r | |
1029 | IN UINT32 Value\r | |
1030 | )\r | |
1031 | {\r | |
1032 | UINTN Count;\r | |
1033 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
1034 | \r | |
1035 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
1036 | return MmioBitFieldWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);\r | |
1037 | }\r | |
1038 | \r | |
1039 | /**\r | |
1040 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1041 | writes the result back to the bit field in the 32-bit port.\r | |
1042 | \r | |
1043 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1044 | bitwise OR between the read result and the value specified by\r | |
1045 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1046 | specified by Address. The value written to the PCI configuration register is\r | |
1047 | returned. This function must guarantee that all PCI read and write operations\r | |
1048 | are serialized. Extra left bits in OrData are stripped.\r | |
1049 | \r | |
1050 | If any reserved bits in Address are set, then ASSERT().\r | |
1051 | If StartBit is greater than 31, then ASSERT().\r | |
1052 | If EndBit is greater than 31, then ASSERT().\r | |
1053 | If EndBit is less than StartBit, then ASSERT().\r | |
1054 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1055 | \r | |
1056 | @param Address PCI configuration register to write.\r | |
1057 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1058 | Range 0..31.\r | |
1059 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1060 | Range 0..31.\r | |
1061 | @param OrData The value to OR with the PCI configuration register.\r | |
1062 | \r | |
1063 | @return The value written back to the PCI configuration register.\r | |
1064 | \r | |
1065 | **/\r | |
1066 | UINT32\r | |
1067 | EFIAPI\r | |
1068 | PciSegmentBitFieldOr32 (\r | |
1069 | IN UINT64 Address,\r | |
1070 | IN UINTN StartBit,\r | |
1071 | IN UINTN EndBit,\r | |
1072 | IN UINT32 OrData\r | |
1073 | )\r | |
1074 | {\r | |
1075 | UINTN Count;\r | |
1076 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
1077 | \r | |
1078 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
1079 | return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);\r | |
1080 | }\r | |
1081 | \r | |
1082 | /**\r | |
1083 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1084 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1085 | \r | |
1086 | \r | |
1087 | Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r | |
1088 | AND between the read result and the value specified by AndData, and writes the result\r | |
1089 | to the 32-bit PCI configuration register specified by Address. The value written to\r | |
1090 | the PCI configuration register is returned. This function must guarantee that all PCI\r | |
1091 | read and write operations are serialized. Extra left bits in AndData are stripped.\r | |
1092 | If any reserved bits in Address are set, then ASSERT().\r | |
1093 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1094 | If StartBit is greater than 31, then ASSERT().\r | |
1095 | If EndBit is greater than 31, then ASSERT().\r | |
1096 | If EndBit is less than StartBit, then ASSERT().\r | |
1097 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1098 | \r | |
1099 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
1100 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1101 | Range 0..31.\r | |
1102 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1103 | Range 0..31.\r | |
1104 | @param AndData The value to AND with the PCI configuration register.\r | |
1105 | \r | |
1106 | @return The value written back to the PCI configuration register.\r | |
1107 | \r | |
1108 | **/\r | |
1109 | UINT32\r | |
1110 | EFIAPI\r | |
1111 | PciSegmentBitFieldAnd32 (\r | |
1112 | IN UINT64 Address,\r | |
1113 | IN UINTN StartBit,\r | |
1114 | IN UINTN EndBit,\r | |
1115 | IN UINT32 AndData\r | |
1116 | )\r | |
1117 | {\r | |
1118 | UINTN Count;\r | |
1119 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
1120 | \r | |
1121 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
7d8e8474 | 1122 | return MmioBitFieldAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);\r |
5c9bb86f RN |
1123 | }\r |
1124 | \r | |
1125 | /**\r | |
1126 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1127 | bitwise OR, and writes the result back to the bit field in the\r | |
1128 | 32-bit port.\r | |
1129 | \r | |
1130 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1131 | bitwise AND followed by a bitwise OR between the read result and\r | |
1132 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1133 | configuration register specified by Address. The value written to the PCI\r | |
1134 | configuration register is returned. This function must guarantee that all PCI\r | |
1135 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1136 | OrData are stripped.\r | |
1137 | \r | |
1138 | If any reserved bits in Address are set, then ASSERT().\r | |
1139 | If StartBit is greater than 31, then ASSERT().\r | |
1140 | If EndBit is greater than 31, then ASSERT().\r | |
1141 | If EndBit is less than StartBit, then ASSERT().\r | |
1142 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1143 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1144 | \r | |
1145 | @param Address PCI configuration register to write.\r | |
1146 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1147 | Range 0..31.\r | |
1148 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1149 | Range 0..31.\r | |
1150 | @param AndData The value to AND with the PCI configuration register.\r | |
1151 | @param OrData The value to OR with the result of the AND operation.\r | |
1152 | \r | |
1153 | @return The value written back to the PCI configuration register.\r | |
1154 | \r | |
1155 | **/\r | |
1156 | UINT32\r | |
1157 | EFIAPI\r | |
1158 | PciSegmentBitFieldAndThenOr32 (\r | |
1159 | IN UINT64 Address,\r | |
1160 | IN UINTN StartBit,\r | |
1161 | IN UINTN EndBit,\r | |
1162 | IN UINT32 AndData,\r | |
1163 | IN UINT32 OrData\r | |
1164 | )\r | |
1165 | {\r | |
1166 | UINTN Count;\r | |
1167 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
1168 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
1169 | return MmioBitFieldAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);\r | |
1170 | }\r | |
1171 | \r | |
1172 | /**\r | |
1173 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1174 | \r | |
1175 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1176 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1177 | configuration registers from a single PCI function to be read. Size is\r | |
1178 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1179 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1180 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1181 | end of the range.\r | |
1182 | \r | |
1183 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1184 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1185 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1186 | \r | |
1187 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1188 | Function and Register.\r | |
1189 | @param Size Size in bytes of the transfer.\r | |
1190 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1191 | \r | |
1192 | @return Size\r | |
1193 | \r | |
1194 | **/\r | |
1195 | UINTN\r | |
1196 | EFIAPI\r | |
1197 | PciSegmentReadBuffer (\r | |
1198 | IN UINT64 StartAddress,\r | |
1199 | IN UINTN Size,\r | |
1200 | OUT VOID *Buffer\r | |
1201 | )\r | |
1202 | {\r | |
1203 | UINTN ReturnValue;\r | |
1204 | UINTN Count;\r | |
1205 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
1206 | UINTN Address;\r | |
1207 | \r | |
1208 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1209 | \r | |
1210 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
1211 | Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);\r | |
1212 | \r | |
1213 | if (Size == 0) {\r | |
1214 | return 0;\r | |
1215 | }\r | |
1216 | \r | |
1217 | ASSERT (Buffer != NULL);\r | |
1218 | \r | |
1219 | //\r | |
1220 | // Save Size for return\r | |
1221 | //\r | |
1222 | ReturnValue = Size;\r | |
1223 | \r | |
1224 | if ((Address & BIT0) != 0) {\r | |
1225 | //\r | |
1226 | // Read a byte if StartAddress is byte aligned\r | |
1227 | //\r | |
1228 | *(volatile UINT8 *)Buffer = MmioRead8 (Address);\r | |
1229 | Address += sizeof (UINT8);\r | |
1230 | Size -= sizeof (UINT8);\r | |
1231 | Buffer = (UINT8*)Buffer + 1;\r | |
1232 | }\r | |
1233 | \r | |
1234 | if (Size >= sizeof (UINT16) && (Address & BIT1) != 0) {\r | |
1235 | //\r | |
1236 | // Read a word if StartAddress is word aligned\r | |
1237 | //\r | |
1238 | WriteUnaligned16 (Buffer, MmioRead16 (Address));\r | |
1239 | Address += sizeof (UINT16);\r | |
1240 | Size -= sizeof (UINT16);\r | |
1241 | Buffer = (UINT16*)Buffer + 1;\r | |
1242 | }\r | |
1243 | \r | |
1244 | while (Size >= sizeof (UINT32)) {\r | |
1245 | //\r | |
1246 | // Read as many double words as possible\r | |
1247 | //\r | |
1248 | WriteUnaligned32 (Buffer, MmioRead32 (Address));\r | |
1249 | Address += sizeof (UINT32);\r | |
1250 | Size -= sizeof (UINT32);\r | |
1251 | Buffer = (UINT32*)Buffer + 1;\r | |
1252 | }\r | |
1253 | \r | |
1254 | if (Size >= sizeof (UINT16)) {\r | |
1255 | //\r | |
1256 | // Read the last remaining word if exist\r | |
1257 | //\r | |
1258 | WriteUnaligned16 (Buffer, MmioRead16 (Address));\r | |
1259 | Address += sizeof (UINT16);\r | |
1260 | Size -= sizeof (UINT16);\r | |
1261 | Buffer = (UINT16*)Buffer + 1;\r | |
1262 | }\r | |
1263 | \r | |
1264 | if (Size >= sizeof (UINT8)) {\r | |
1265 | //\r | |
1266 | // Read the last remaining byte if exist\r | |
1267 | //\r | |
1268 | *(volatile UINT8 *)Buffer = MmioRead8 (Address);\r | |
1269 | }\r | |
1270 | \r | |
1271 | return ReturnValue;\r | |
1272 | }\r | |
1273 | \r | |
1274 | /**\r | |
1275 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1276 | configuration space.\r | |
1277 | \r | |
1278 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1279 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1280 | configuration registers from a single PCI function to be written. Size is\r | |
1281 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1282 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1283 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1284 | and the end of the range.\r | |
1285 | \r | |
1286 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1287 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1288 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1289 | \r | |
1290 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1291 | Function and Register.\r | |
1292 | @param Size Size in bytes of the transfer.\r | |
1293 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1294 | \r | |
1295 | @return The parameter of Size.\r | |
1296 | \r | |
1297 | **/\r | |
1298 | UINTN\r | |
1299 | EFIAPI\r | |
1300 | PciSegmentWriteBuffer (\r | |
1301 | IN UINT64 StartAddress,\r | |
1302 | IN UINTN Size,\r | |
1303 | IN VOID *Buffer\r | |
1304 | )\r | |
1305 | {\r | |
1306 | UINTN ReturnValue;\r | |
1307 | UINTN Count;\r | |
1308 | PCI_SEGMENT_INFO *SegmentInfo;\r | |
1309 | UINTN Address;\r | |
1310 | \r | |
1311 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1312 | \r | |
1313 | SegmentInfo = GetPciSegmentInfo (&Count);\r | |
1314 | Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);\r | |
1315 | \r | |
1316 | if (Size == 0) {\r | |
1317 | return 0;\r | |
1318 | }\r | |
1319 | \r | |
1320 | ASSERT (Buffer != NULL);\r | |
1321 | \r | |
1322 | //\r | |
1323 | // Save Size for return\r | |
1324 | //\r | |
1325 | ReturnValue = Size;\r | |
1326 | \r | |
1327 | if ((Address & BIT0) != 0) {\r | |
1328 | //\r | |
1329 | // Write a byte if StartAddress is byte aligned\r | |
1330 | //\r | |
1331 | MmioWrite8 (Address, *(UINT8*)Buffer);\r | |
1332 | Address += sizeof (UINT8);\r | |
1333 | Size -= sizeof (UINT8);\r | |
1334 | Buffer = (UINT8*)Buffer + 1;\r | |
1335 | }\r | |
1336 | \r | |
1337 | if (Size >= sizeof (UINT16) && (Address & BIT1) != 0) {\r | |
1338 | //\r | |
1339 | // Write a word if StartAddress is word aligned\r | |
1340 | //\r | |
1341 | MmioWrite16 (Address, ReadUnaligned16 (Buffer));\r | |
1342 | Address += sizeof (UINT16);\r | |
1343 | Size -= sizeof (UINT16);\r | |
1344 | Buffer = (UINT16*)Buffer + 1;\r | |
1345 | }\r | |
1346 | \r | |
1347 | while (Size >= sizeof (UINT32)) {\r | |
1348 | //\r | |
1349 | // Write as many double words as possible\r | |
1350 | //\r | |
1351 | MmioWrite32 (Address, ReadUnaligned32 (Buffer));\r | |
1352 | Address += sizeof (UINT32);\r | |
1353 | Size -= sizeof (UINT32);\r | |
1354 | Buffer = (UINT32*)Buffer + 1;\r | |
1355 | }\r | |
1356 | \r | |
1357 | if (Size >= sizeof (UINT16)) {\r | |
1358 | //\r | |
1359 | // Write the last remaining word if exist\r | |
1360 | //\r | |
1361 | MmioWrite16 (Address, ReadUnaligned16 (Buffer));\r | |
1362 | Address += sizeof (UINT16);\r | |
1363 | Size -= sizeof (UINT16);\r | |
1364 | Buffer = (UINT16*)Buffer + 1;\r | |
1365 | }\r | |
1366 | \r | |
1367 | if (Size >= sizeof (UINT8)) {\r | |
1368 | //\r | |
1369 | // Write the last remaining byte if exist\r | |
1370 | //\r | |
1371 | MmioWrite8 (Address, *(UINT8*)Buffer);\r | |
1372 | }\r | |
1373 | \r | |
1374 | return ReturnValue;\r | |
1375 | }\r |