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1a3eaf06 | 1 | /** @file\r |
2 | PCI Library using PCI CFG2 PPI.\r | |
3 | \r | |
58380e9c | 4 | Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r |
19388d29 | 5 | This program and the accompanying materials are\r |
1a3eaf06 | 6 | licensed and made available under the terms and conditions of\r |
7 | the BSD License which accompanies this distribution. The full\r | |
8 | text of the license may be found at\r | |
2fc59a00 | 9 | http://opensource.org/licenses/bsd-license.php.\r |
1a3eaf06 | 10 | \r |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <PiPei.h>\r | |
17 | \r | |
18 | #include <Ppi/PciCfg2.h>\r | |
19 | \r | |
20 | #include <Library/PciLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/PeiServicesTablePointerLib.h>\r | |
23 | #include <Library/DebugLib.h>\r | |
24 | #include <Library/PeiServicesLib.h>\r | |
25 | \r | |
26 | /**\r | |
27 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
28 | only in the low 28 bits.\r | |
29 | \r | |
30 | @param A The address to validate.\r | |
31 | @param M Additional bits to assert to be zero.\r | |
32 | \r | |
33 | **/\r | |
34 | #define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r | |
35 | ASSERT (((A) & (~0xfffffff | (M))) == 0)\r | |
36 | \r | |
37 | /**\r | |
38 | Translate PCI Lib address into format of PCI CFG2 PPI.\r | |
39 | \r | |
2fc59a00 | 40 | @param A The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 41 | Register.\r |
42 | \r | |
43 | **/\r | |
44 | #define PCI_TO_PCICFG2_ADDRESS(A) \\r | |
e43e4b3e | 45 | ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r |
1a3eaf06 | 46 | \r |
47 | /**\r | |
48 | Internal worker function to read a PCI configuration register.\r | |
49 | \r | |
50 | This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.\r | |
51 | It reads and returns the PCI configuration register specified by Address,\r | |
52 | the width of data is specified by Width.\r | |
53 | \r | |
2fc59a00 | 54 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 55 | Register.\r |
58380e9c | 56 | @param Width The width of data to read\r |
1a3eaf06 | 57 | \r |
58 | @return The value read from the PCI configuration register.\r | |
59 | \r | |
60 | **/\r | |
61 | UINT32\r | |
62 | PeiPciLibPciCfg2ReadWorker (\r | |
63 | IN UINTN Address,\r | |
64 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r | |
65 | )\r | |
66 | {\r | |
67 | EFI_STATUS Status;\r | |
68 | UINT32 Data;\r | |
69 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 70 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 71 | \r |
72 | Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r | |
73 | ASSERT_EFI_ERROR (Status);\r | |
74 | ASSERT (PciCfg2Ppi != NULL);\r | |
75 | \r | |
43fe5cdc | 76 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 77 | PciCfg2Ppi->Read (\r |
78 | GetPeiServicesTablePointer (),\r | |
79 | PciCfg2Ppi,\r | |
80 | Width,\r | |
43fe5cdc | 81 | PciCfg2Address,\r |
1a3eaf06 | 82 | &Data\r |
83 | );\r | |
84 | \r | |
85 | return Data;\r | |
86 | }\r | |
87 | \r | |
88 | /**\r | |
89 | Internal worker function to writes a PCI configuration register.\r | |
90 | \r | |
91 | This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.\r | |
92 | It writes the PCI configuration register specified by Address with the\r | |
93 | value specified by Data. The width of data is specifed by Width.\r | |
94 | Data is returned.\r | |
95 | \r | |
2fc59a00 | 96 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 97 | Register.\r |
58380e9c | 98 | @param Width The width of data to write\r |
1a3eaf06 | 99 | @param Data The value to write.\r |
100 | \r | |
101 | @return The value written to the PCI configuration register.\r | |
102 | \r | |
103 | **/\r | |
104 | UINT32\r | |
105 | PeiPciLibPciCfg2WriteWorker (\r | |
106 | IN UINTN Address,\r | |
107 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r | |
108 | IN UINT32 Data\r | |
109 | )\r | |
110 | {\r | |
111 | EFI_STATUS Status;\r | |
112 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 113 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 114 | \r |
115 | Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r | |
116 | ASSERT_EFI_ERROR (Status);\r | |
117 | ASSERT (PciCfg2Ppi != NULL);\r | |
118 | \r | |
43fe5cdc | 119 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 120 | PciCfg2Ppi->Write (\r |
121 | GetPeiServicesTablePointer (),\r | |
122 | PciCfg2Ppi,\r | |
123 | Width,\r | |
43fe5cdc | 124 | PciCfg2Address,\r |
1a3eaf06 | 125 | &Data\r |
126 | );\r | |
127 | \r | |
128 | return Data;\r | |
129 | }\r | |
130 | \r | |
3e3ae634 | 131 | /**\r |
d11195a3 | 132 | Registers a PCI device so PCI configuration registers may be accessed after \r |
3e3ae634 | 133 | SetVirtualAddressMap().\r |
134 | \r | |
d11195a3 | 135 | Registers the PCI device specified by Address so all the PCI configuration registers \r |
136 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r | |
137 | \r | |
3e3ae634 | 138 | If Address > 0x0FFFFFFF, then ASSERT().\r |
139 | \r | |
2fc59a00 | 140 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 141 | Register.\r |
142 | \r | |
143 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
144 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
145 | after ExitBootServices().\r | |
146 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
147 | at runtime could not be mapped.\r | |
148 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
149 | complete the registration.\r | |
150 | \r | |
151 | **/\r | |
152 | RETURN_STATUS\r | |
153 | EFIAPI\r | |
154 | PciRegisterForRuntimeAccess (\r | |
155 | IN UINTN Address\r | |
156 | )\r | |
157 | {\r | |
59ceeabe | 158 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
3e3ae634 | 159 | return RETURN_UNSUPPORTED;\r |
160 | }\r | |
161 | \r | |
1a3eaf06 | 162 | /**\r |
163 | Reads an 8-bit PCI configuration register.\r | |
164 | \r | |
165 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
166 | This function must guarantee that all PCI read and write operations are\r | |
167 | serialized.\r | |
168 | \r | |
169 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
170 | \r | |
2fc59a00 | 171 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 172 | Register.\r |
173 | \r | |
0c3437e0 | 174 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 175 | \r |
176 | **/\r | |
177 | UINT8\r | |
178 | EFIAPI\r | |
179 | PciRead8 (\r | |
180 | IN UINTN Address\r | |
181 | )\r | |
182 | {\r | |
183 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
184 | \r | |
185 | return (UINT8) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r | |
186 | }\r | |
187 | \r | |
188 | /**\r | |
189 | Writes an 8-bit PCI configuration register.\r | |
190 | \r | |
191 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
192 | value specified by Value. Value is returned. This function must guarantee\r | |
193 | that all PCI read and write operations are serialized.\r | |
194 | \r | |
195 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
196 | \r | |
2fc59a00 | 197 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 198 | Register.\r |
0c3437e0 | 199 | @param Value The value to write.\r |
1a3eaf06 | 200 | \r |
201 | @return The value written to the PCI configuration register.\r | |
202 | \r | |
203 | **/\r | |
204 | UINT8\r | |
205 | EFIAPI\r | |
206 | PciWrite8 (\r | |
207 | IN UINTN Address,\r | |
0c3437e0 | 208 | IN UINT8 Value\r |
1a3eaf06 | 209 | )\r |
210 | {\r | |
211 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
212 | \r | |
0c3437e0 | 213 | return (UINT8) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r |
1a3eaf06 | 214 | }\r |
215 | \r | |
216 | /**\r | |
62991af2 | 217 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
1a3eaf06 | 218 | an 8-bit value.\r |
219 | \r | |
220 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 221 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 222 | OrData, and writes the result to the 8-bit PCI configuration register\r |
223 | specified by Address. The value written to the PCI configuration register is\r | |
224 | returned. This function must guarantee that all PCI read and write operations\r | |
225 | are serialized.\r | |
226 | \r | |
227 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
228 | \r | |
2fc59a00 | 229 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 230 | Register.\r |
231 | @param OrData The value to OR with the PCI configuration register.\r | |
232 | \r | |
233 | @return The value written back to the PCI configuration register.\r | |
234 | \r | |
235 | **/\r | |
236 | UINT8\r | |
237 | EFIAPI\r | |
238 | PciOr8 (\r | |
239 | IN UINTN Address,\r | |
240 | IN UINT8 OrData\r | |
241 | )\r | |
242 | {\r | |
243 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r | |
244 | }\r | |
245 | \r | |
246 | /**\r | |
247 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
248 | value.\r | |
249 | \r | |
250 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
251 | bitwise AND between the read result and the value specified by AndData, and\r | |
252 | writes the result to the 8-bit PCI configuration register specified by\r | |
253 | Address. The value written to the PCI configuration register is returned.\r | |
254 | This function must guarantee that all PCI read and write operations are\r | |
255 | serialized.\r | |
256 | \r | |
257 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
258 | \r | |
2fc59a00 | 259 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 260 | Register.\r |
261 | @param AndData The value to AND with the PCI configuration register.\r | |
262 | \r | |
263 | @return The value written back to the PCI configuration register.\r | |
264 | \r | |
265 | **/\r | |
266 | UINT8\r | |
267 | EFIAPI\r | |
268 | PciAnd8 (\r | |
269 | IN UINTN Address,\r | |
270 | IN UINT8 AndData\r | |
271 | )\r | |
272 | {\r | |
273 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r | |
274 | }\r | |
275 | \r | |
276 | /**\r | |
277 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 278 | value, followed a bitwise OR with another 8-bit value.\r |
1a3eaf06 | 279 | \r |
280 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
281 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 282 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 283 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
284 | configuration register specified by Address. The value written to the PCI\r | |
285 | configuration register is returned. This function must guarantee that all PCI\r | |
286 | read and write operations are serialized.\r | |
287 | \r | |
288 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
289 | \r | |
2fc59a00 | 290 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 291 | Register.\r |
292 | @param AndData The value to AND with the PCI configuration register.\r | |
293 | @param OrData The value to OR with the result of the AND operation.\r | |
294 | \r | |
295 | @return The value written back to the PCI configuration register.\r | |
296 | \r | |
297 | **/\r | |
298 | UINT8\r | |
299 | EFIAPI\r | |
300 | PciAndThenOr8 (\r | |
301 | IN UINTN Address,\r | |
302 | IN UINT8 AndData,\r | |
303 | IN UINT8 OrData\r | |
304 | )\r | |
305 | {\r | |
306 | return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r | |
307 | }\r | |
308 | \r | |
309 | /**\r | |
310 | Reads a bit field of a PCI configuration register.\r | |
311 | \r | |
312 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
313 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
314 | returned.\r | |
315 | \r | |
316 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
317 | If StartBit is greater than 7, then ASSERT().\r | |
318 | If EndBit is greater than 7, then ASSERT().\r | |
319 | If EndBit is less than StartBit, then ASSERT().\r | |
320 | \r | |
2fc59a00 | 321 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 322 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
323 | Range 0..7.\r | |
324 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
325 | Range 0..7.\r | |
326 | \r | |
327 | @return The value of the bit field read from the PCI configuration register.\r | |
328 | \r | |
329 | **/\r | |
330 | UINT8\r | |
331 | EFIAPI\r | |
332 | PciBitFieldRead8 (\r | |
333 | IN UINTN Address,\r | |
334 | IN UINTN StartBit,\r | |
335 | IN UINTN EndBit\r | |
336 | )\r | |
337 | {\r | |
338 | return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r | |
339 | }\r | |
340 | \r | |
341 | /**\r | |
342 | Writes a bit field to a PCI configuration register.\r | |
343 | \r | |
344 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
345 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
346 | destination PCI configuration register are preserved. The new value of the\r | |
347 | 8-bit register is returned.\r | |
348 | \r | |
349 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
350 | If StartBit is greater than 7, then ASSERT().\r | |
351 | If EndBit is greater than 7, then ASSERT().\r | |
352 | If EndBit is less than StartBit, then ASSERT().\r | |
353 | \r | |
2fc59a00 | 354 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 355 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
356 | Range 0..7.\r | |
357 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
358 | Range 0..7.\r | |
2fc59a00 | 359 | @param Value The new value of the bit field.\r |
1a3eaf06 | 360 | \r |
361 | @return The value written back to the PCI configuration register.\r | |
362 | \r | |
363 | **/\r | |
364 | UINT8\r | |
365 | EFIAPI\r | |
366 | PciBitFieldWrite8 (\r | |
367 | IN UINTN Address,\r | |
368 | IN UINTN StartBit,\r | |
369 | IN UINTN EndBit,\r | |
370 | IN UINT8 Value\r | |
371 | )\r | |
372 | {\r | |
373 | return PciWrite8 (\r | |
374 | Address,\r | |
375 | BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)\r | |
376 | );\r | |
377 | }\r | |
378 | \r | |
379 | /**\r | |
380 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
381 | writes the result back to the bit field in the 8-bit port.\r | |
382 | \r | |
383 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 384 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 385 | OrData, and writes the result to the 8-bit PCI configuration register\r |
386 | specified by Address. The value written to the PCI configuration register is\r | |
387 | returned. This function must guarantee that all PCI read and write operations\r | |
388 | are serialized. Extra left bits in OrData are stripped.\r | |
389 | \r | |
390 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
391 | If StartBit is greater than 7, then ASSERT().\r | |
392 | If EndBit is greater than 7, then ASSERT().\r | |
393 | If EndBit is less than StartBit, then ASSERT().\r | |
394 | \r | |
2fc59a00 | 395 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 396 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
397 | Range 0..7.\r | |
398 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
399 | Range 0..7.\r | |
400 | @param OrData The value to OR with the PCI configuration register.\r | |
401 | \r | |
402 | @return The value written back to the PCI configuration register.\r | |
403 | \r | |
404 | **/\r | |
405 | UINT8\r | |
406 | EFIAPI\r | |
407 | PciBitFieldOr8 (\r | |
408 | IN UINTN Address,\r | |
409 | IN UINTN StartBit,\r | |
410 | IN UINTN EndBit,\r | |
411 | IN UINT8 OrData\r | |
412 | )\r | |
413 | {\r | |
414 | return PciWrite8 (\r | |
415 | Address,\r | |
416 | BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)\r | |
417 | );\r | |
418 | }\r | |
419 | \r | |
420 | /**\r | |
421 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
422 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
423 | \r | |
424 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
425 | bitwise AND between the read result and the value specified by AndData, and\r | |
426 | writes the result to the 8-bit PCI configuration register specified by\r | |
427 | Address. The value written to the PCI configuration register is returned.\r | |
428 | This function must guarantee that all PCI read and write operations are\r | |
429 | serialized. Extra left bits in AndData are stripped.\r | |
430 | \r | |
431 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
432 | If StartBit is greater than 7, then ASSERT().\r | |
433 | If EndBit is greater than 7, then ASSERT().\r | |
434 | If EndBit is less than StartBit, then ASSERT().\r | |
435 | \r | |
2fc59a00 | 436 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 437 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
438 | Range 0..7.\r | |
439 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
440 | Range 0..7.\r | |
441 | @param AndData The value to AND with the PCI configuration register.\r | |
442 | \r | |
443 | @return The value written back to the PCI configuration register.\r | |
444 | \r | |
445 | **/\r | |
446 | UINT8\r | |
447 | EFIAPI\r | |
448 | PciBitFieldAnd8 (\r | |
449 | IN UINTN Address,\r | |
450 | IN UINTN StartBit,\r | |
451 | IN UINTN EndBit,\r | |
452 | IN UINT8 AndData\r | |
453 | )\r | |
454 | {\r | |
455 | return PciWrite8 (\r | |
456 | Address,\r | |
457 | BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)\r | |
458 | );\r | |
459 | }\r | |
460 | \r | |
461 | /**\r | |
462 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 463 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 464 | 8-bit port.\r |
465 | \r | |
466 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 467 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 468 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
469 | configuration register specified by Address. The value written to the PCI\r | |
470 | configuration register is returned. This function must guarantee that all PCI\r | |
471 | read and write operations are serialized. Extra left bits in both AndData and\r | |
472 | OrData are stripped.\r | |
473 | \r | |
474 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
475 | If StartBit is greater than 7, then ASSERT().\r | |
476 | If EndBit is greater than 7, then ASSERT().\r | |
477 | If EndBit is less than StartBit, then ASSERT().\r | |
478 | \r | |
2fc59a00 | 479 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 480 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
481 | Range 0..7.\r | |
482 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
483 | Range 0..7.\r | |
484 | @param AndData The value to AND with the PCI configuration register.\r | |
485 | @param OrData The value to OR with the result of the AND operation.\r | |
486 | \r | |
487 | @return The value written back to the PCI configuration register.\r | |
488 | \r | |
489 | **/\r | |
490 | UINT8\r | |
491 | EFIAPI\r | |
492 | PciBitFieldAndThenOr8 (\r | |
493 | IN UINTN Address,\r | |
494 | IN UINTN StartBit,\r | |
495 | IN UINTN EndBit,\r | |
496 | IN UINT8 AndData,\r | |
497 | IN UINT8 OrData\r | |
498 | )\r | |
499 | {\r | |
500 | return PciWrite8 (\r | |
501 | Address,\r | |
502 | BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
503 | );\r | |
504 | }\r | |
505 | \r | |
506 | /**\r | |
507 | Reads a 16-bit PCI configuration register.\r | |
508 | \r | |
509 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
510 | This function must guarantee that all PCI read and write operations are\r | |
511 | serialized.\r | |
512 | \r | |
513 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
514 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
515 | \r | |
2fc59a00 | 516 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 517 | Register.\r |
518 | \r | |
9638ba6d | 519 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 520 | \r |
521 | **/\r | |
522 | UINT16\r | |
523 | EFIAPI\r | |
524 | PciRead16 (\r | |
525 | IN UINTN Address\r | |
526 | )\r | |
527 | {\r | |
528 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
529 | \r | |
530 | return (UINT16) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r | |
531 | }\r | |
532 | \r | |
533 | /**\r | |
534 | Writes a 16-bit PCI configuration register.\r | |
535 | \r | |
536 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
537 | value specified by Value. Value is returned. This function must guarantee\r | |
538 | that all PCI read and write operations are serialized.\r | |
539 | \r | |
540 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
541 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
542 | \r | |
2fc59a00 | 543 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 544 | Register.\r |
9638ba6d | 545 | @param Value The value to write.\r |
1a3eaf06 | 546 | \r |
547 | @return The value written to the PCI configuration register.\r | |
548 | \r | |
549 | **/\r | |
550 | UINT16\r | |
551 | EFIAPI\r | |
552 | PciWrite16 (\r | |
553 | IN UINTN Address,\r | |
0c3437e0 | 554 | IN UINT16 Value\r |
1a3eaf06 | 555 | )\r |
556 | {\r | |
557 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
558 | \r | |
0c3437e0 | 559 | return (UINT16) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r |
1a3eaf06 | 560 | }\r |
561 | \r | |
562 | /**\r | |
62991af2 | 563 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
1a3eaf06 | 564 | a 16-bit value.\r |
565 | \r | |
566 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 567 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 568 | OrData, and writes the result to the 16-bit PCI configuration register\r |
569 | specified by Address. The value written to the PCI configuration register is\r | |
570 | returned. This function must guarantee that all PCI read and write operations\r | |
571 | are serialized.\r | |
572 | \r | |
573 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
574 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
575 | \r | |
2fc59a00 | 576 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 577 | Register.\r |
578 | @param OrData The value to OR with the PCI configuration register.\r | |
579 | \r | |
580 | @return The value written back to the PCI configuration register.\r | |
581 | \r | |
582 | **/\r | |
583 | UINT16\r | |
584 | EFIAPI\r | |
585 | PciOr16 (\r | |
586 | IN UINTN Address,\r | |
587 | IN UINT16 OrData\r | |
588 | )\r | |
589 | {\r | |
590 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r | |
591 | }\r | |
592 | \r | |
593 | /**\r | |
594 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
595 | value.\r | |
596 | \r | |
597 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
598 | bitwise AND between the read result and the value specified by AndData, and\r | |
599 | writes the result to the 16-bit PCI configuration register specified by\r | |
600 | Address. The value written to the PCI configuration register is returned.\r | |
601 | This function must guarantee that all PCI read and write operations are\r | |
602 | serialized.\r | |
603 | \r | |
604 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
605 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
606 | \r | |
2fc59a00 | 607 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 608 | Register.\r |
609 | @param AndData The value to AND with the PCI configuration register.\r | |
610 | \r | |
611 | @return The value written back to the PCI configuration register.\r | |
612 | \r | |
613 | **/\r | |
614 | UINT16\r | |
615 | EFIAPI\r | |
616 | PciAnd16 (\r | |
617 | IN UINTN Address,\r | |
618 | IN UINT16 AndData\r | |
619 | )\r | |
620 | {\r | |
621 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r | |
622 | }\r | |
623 | \r | |
624 | /**\r | |
625 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 626 | value, followed a bitwise OR with another 16-bit value.\r |
1a3eaf06 | 627 | \r |
628 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
629 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 630 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 631 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
632 | configuration register specified by Address. The value written to the PCI\r | |
633 | configuration register is returned. This function must guarantee that all PCI\r | |
634 | read and write operations are serialized.\r | |
635 | \r | |
636 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
637 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
638 | \r | |
2fc59a00 | 639 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 640 | Register.\r |
641 | @param AndData The value to AND with the PCI configuration register.\r | |
642 | @param OrData The value to OR with the result of the AND operation.\r | |
643 | \r | |
644 | @return The value written back to the PCI configuration register.\r | |
645 | \r | |
646 | **/\r | |
647 | UINT16\r | |
648 | EFIAPI\r | |
649 | PciAndThenOr16 (\r | |
650 | IN UINTN Address,\r | |
651 | IN UINT16 AndData,\r | |
652 | IN UINT16 OrData\r | |
653 | )\r | |
654 | {\r | |
655 | return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r | |
656 | }\r | |
657 | \r | |
658 | /**\r | |
659 | Reads a bit field of a PCI configuration register.\r | |
660 | \r | |
661 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
662 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
663 | returned.\r | |
664 | \r | |
665 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
666 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
667 | If StartBit is greater than 15, then ASSERT().\r | |
668 | If EndBit is greater than 15, then ASSERT().\r | |
669 | If EndBit is less than StartBit, then ASSERT().\r | |
670 | \r | |
2fc59a00 | 671 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 672 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
673 | Range 0..15.\r | |
674 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
675 | Range 0..15.\r | |
676 | \r | |
677 | @return The value of the bit field read from the PCI configuration register.\r | |
678 | \r | |
679 | **/\r | |
680 | UINT16\r | |
681 | EFIAPI\r | |
682 | PciBitFieldRead16 (\r | |
683 | IN UINTN Address,\r | |
684 | IN UINTN StartBit,\r | |
685 | IN UINTN EndBit\r | |
686 | )\r | |
687 | {\r | |
688 | return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r | |
689 | }\r | |
690 | \r | |
691 | /**\r | |
692 | Writes a bit field to a PCI configuration register.\r | |
693 | \r | |
694 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
695 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
696 | destination PCI configuration register are preserved. The new value of the\r | |
697 | 16-bit register is returned.\r | |
698 | \r | |
699 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
700 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
701 | If StartBit is greater than 15, then ASSERT().\r | |
702 | If EndBit is greater than 15, then ASSERT().\r | |
703 | If EndBit is less than StartBit, then ASSERT().\r | |
704 | \r | |
2fc59a00 | 705 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 706 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
707 | Range 0..15.\r | |
708 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
709 | Range 0..15.\r | |
2fc59a00 | 710 | @param Value The new value of the bit field.\r |
1a3eaf06 | 711 | \r |
712 | @return The value written back to the PCI configuration register.\r | |
713 | \r | |
714 | **/\r | |
715 | UINT16\r | |
716 | EFIAPI\r | |
717 | PciBitFieldWrite16 (\r | |
718 | IN UINTN Address,\r | |
719 | IN UINTN StartBit,\r | |
720 | IN UINTN EndBit,\r | |
721 | IN UINT16 Value\r | |
722 | )\r | |
723 | {\r | |
724 | return PciWrite16 (\r | |
725 | Address,\r | |
726 | BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)\r | |
727 | );\r | |
728 | }\r | |
729 | \r | |
730 | /**\r | |
731 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
732 | writes the result back to the bit field in the 16-bit port.\r | |
733 | \r | |
734 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 735 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 736 | OrData, and writes the result to the 16-bit PCI configuration register\r |
737 | specified by Address. The value written to the PCI configuration register is\r | |
738 | returned. This function must guarantee that all PCI read and write operations\r | |
739 | are serialized. Extra left bits in OrData are stripped.\r | |
740 | \r | |
741 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
742 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
743 | If StartBit is greater than 15, then ASSERT().\r | |
744 | If EndBit is greater than 15, then ASSERT().\r | |
745 | If EndBit is less than StartBit, then ASSERT().\r | |
746 | \r | |
2fc59a00 | 747 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 748 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
749 | Range 0..15.\r | |
750 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
751 | Range 0..15.\r | |
752 | @param OrData The value to OR with the PCI configuration register.\r | |
753 | \r | |
754 | @return The value written back to the PCI configuration register.\r | |
755 | \r | |
756 | **/\r | |
757 | UINT16\r | |
758 | EFIAPI\r | |
759 | PciBitFieldOr16 (\r | |
760 | IN UINTN Address,\r | |
761 | IN UINTN StartBit,\r | |
762 | IN UINTN EndBit,\r | |
763 | IN UINT16 OrData\r | |
764 | )\r | |
765 | {\r | |
766 | return PciWrite16 (\r | |
767 | Address,\r | |
768 | BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)\r | |
769 | );\r | |
770 | }\r | |
771 | \r | |
772 | /**\r | |
773 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
774 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
775 | \r | |
776 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
777 | bitwise AND between the read result and the value specified by AndData, and\r | |
778 | writes the result to the 16-bit PCI configuration register specified by\r | |
779 | Address. The value written to the PCI configuration register is returned.\r | |
780 | This function must guarantee that all PCI read and write operations are\r | |
781 | serialized. Extra left bits in AndData are stripped.\r | |
782 | \r | |
783 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
784 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
785 | If StartBit is greater than 15, then ASSERT().\r | |
786 | If EndBit is greater than 15, then ASSERT().\r | |
787 | If EndBit is less than StartBit, then ASSERT().\r | |
788 | \r | |
2fc59a00 | 789 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 790 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
791 | Range 0..15.\r | |
792 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
793 | Range 0..15.\r | |
794 | @param AndData The value to AND with the PCI configuration register.\r | |
795 | \r | |
796 | @return The value written back to the PCI configuration register.\r | |
797 | \r | |
798 | **/\r | |
799 | UINT16\r | |
800 | EFIAPI\r | |
801 | PciBitFieldAnd16 (\r | |
802 | IN UINTN Address,\r | |
803 | IN UINTN StartBit,\r | |
804 | IN UINTN EndBit,\r | |
805 | IN UINT16 AndData\r | |
806 | )\r | |
807 | {\r | |
808 | return PciWrite16 (\r | |
809 | Address,\r | |
810 | BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)\r | |
811 | );\r | |
812 | }\r | |
813 | \r | |
814 | /**\r | |
815 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 816 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 817 | 16-bit port.\r |
818 | \r | |
819 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 820 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 821 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
822 | configuration register specified by Address. The value written to the PCI\r | |
823 | configuration register is returned. This function must guarantee that all PCI\r | |
824 | read and write operations are serialized. Extra left bits in both AndData and\r | |
825 | OrData are stripped.\r | |
826 | \r | |
827 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
828 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
829 | If StartBit is greater than 15, then ASSERT().\r | |
830 | If EndBit is greater than 15, then ASSERT().\r | |
831 | If EndBit is less than StartBit, then ASSERT().\r | |
832 | \r | |
2fc59a00 | 833 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 834 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
835 | Range 0..15.\r | |
836 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
837 | Range 0..15.\r | |
838 | @param AndData The value to AND with the PCI configuration register.\r | |
839 | @param OrData The value to OR with the result of the AND operation.\r | |
840 | \r | |
841 | @return The value written back to the PCI configuration register.\r | |
842 | \r | |
843 | **/\r | |
844 | UINT16\r | |
845 | EFIAPI\r | |
846 | PciBitFieldAndThenOr16 (\r | |
847 | IN UINTN Address,\r | |
848 | IN UINTN StartBit,\r | |
849 | IN UINTN EndBit,\r | |
850 | IN UINT16 AndData,\r | |
851 | IN UINT16 OrData\r | |
852 | )\r | |
853 | {\r | |
854 | return PciWrite16 (\r | |
855 | Address,\r | |
856 | BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
857 | );\r | |
858 | }\r | |
859 | \r | |
860 | /**\r | |
861 | Reads a 32-bit PCI configuration register.\r | |
862 | \r | |
863 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
864 | This function must guarantee that all PCI read and write operations are\r | |
865 | serialized.\r | |
866 | \r | |
867 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
868 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
869 | \r | |
2fc59a00 | 870 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 871 | Register.\r |
872 | \r | |
9638ba6d | 873 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 874 | \r |
875 | **/\r | |
876 | UINT32\r | |
877 | EFIAPI\r | |
878 | PciRead32 (\r | |
879 | IN UINTN Address\r | |
880 | )\r | |
881 | {\r | |
882 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
883 | \r | |
884 | return PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);\r | |
885 | }\r | |
886 | \r | |
887 | /**\r | |
888 | Writes a 32-bit PCI configuration register.\r | |
889 | \r | |
890 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
891 | value specified by Value. Value is returned. This function must guarantee\r | |
892 | that all PCI read and write operations are serialized.\r | |
893 | \r | |
894 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
895 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
896 | \r | |
2fc59a00 | 897 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 898 | Register.\r |
9638ba6d | 899 | @param Value The value to write.\r |
1a3eaf06 | 900 | \r |
901 | @return The value written to the PCI configuration register.\r | |
902 | \r | |
903 | **/\r | |
904 | UINT32\r | |
905 | EFIAPI\r | |
906 | PciWrite32 (\r | |
907 | IN UINTN Address,\r | |
0c3437e0 | 908 | IN UINT32 Value\r |
1a3eaf06 | 909 | )\r |
910 | {\r | |
911 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
912 | \r | |
0c3437e0 | 913 | return PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Value);\r |
1a3eaf06 | 914 | }\r |
915 | \r | |
916 | /**\r | |
62991af2 | 917 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
1a3eaf06 | 918 | a 32-bit value.\r |
919 | \r | |
920 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 921 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 922 | OrData, and writes the result to the 32-bit PCI configuration register\r |
923 | specified by Address. The value written to the PCI configuration register is\r | |
924 | returned. This function must guarantee that all PCI read and write operations\r | |
925 | are serialized.\r | |
926 | \r | |
927 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
928 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
929 | \r | |
2fc59a00 | 930 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 931 | Register.\r |
932 | @param OrData The value to OR with the PCI configuration register.\r | |
933 | \r | |
934 | @return The value written back to the PCI configuration register.\r | |
935 | \r | |
936 | **/\r | |
937 | UINT32\r | |
938 | EFIAPI\r | |
939 | PciOr32 (\r | |
940 | IN UINTN Address,\r | |
941 | IN UINT32 OrData\r | |
942 | )\r | |
943 | {\r | |
944 | return PciWrite32 (Address, PciRead32 (Address) | OrData);\r | |
945 | }\r | |
946 | \r | |
947 | /**\r | |
948 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
949 | value.\r | |
950 | \r | |
951 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
952 | bitwise AND between the read result and the value specified by AndData, and\r | |
953 | writes the result to the 32-bit PCI configuration register specified by\r | |
954 | Address. The value written to the PCI configuration register is returned.\r | |
955 | This function must guarantee that all PCI read and write operations are\r | |
956 | serialized.\r | |
957 | \r | |
958 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
959 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
960 | \r | |
2fc59a00 | 961 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 962 | Register.\r |
963 | @param AndData The value to AND with the PCI configuration register.\r | |
964 | \r | |
965 | @return The value written back to the PCI configuration register.\r | |
966 | \r | |
967 | **/\r | |
968 | UINT32\r | |
969 | EFIAPI\r | |
970 | PciAnd32 (\r | |
971 | IN UINTN Address,\r | |
972 | IN UINT32 AndData\r | |
973 | )\r | |
974 | {\r | |
975 | return PciWrite32 (Address, PciRead32 (Address) & AndData);\r | |
976 | }\r | |
977 | \r | |
978 | /**\r | |
979 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 980 | value, followed a bitwise OR with another 32-bit value.\r |
1a3eaf06 | 981 | \r |
982 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
983 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 984 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 985 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
986 | configuration register specified by Address. The value written to the PCI\r | |
987 | configuration register is returned. This function must guarantee that all PCI\r | |
988 | read and write operations are serialized.\r | |
989 | \r | |
990 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
991 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
992 | \r | |
2fc59a00 | 993 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 994 | Register.\r |
995 | @param AndData The value to AND with the PCI configuration register.\r | |
996 | @param OrData The value to OR with the result of the AND operation.\r | |
997 | \r | |
998 | @return The value written back to the PCI configuration register.\r | |
999 | \r | |
1000 | **/\r | |
1001 | UINT32\r | |
1002 | EFIAPI\r | |
1003 | PciAndThenOr32 (\r | |
1004 | IN UINTN Address,\r | |
1005 | IN UINT32 AndData,\r | |
1006 | IN UINT32 OrData\r | |
1007 | )\r | |
1008 | {\r | |
1009 | return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r | |
1010 | }\r | |
1011 | \r | |
1012 | /**\r | |
1013 | Reads a bit field of a PCI configuration register.\r | |
1014 | \r | |
1015 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1016 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1017 | returned.\r | |
1018 | \r | |
1019 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1020 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1021 | If StartBit is greater than 31, then ASSERT().\r | |
1022 | If EndBit is greater than 31, then ASSERT().\r | |
1023 | If EndBit is less than StartBit, then ASSERT().\r | |
1024 | \r | |
2fc59a00 | 1025 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 1026 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1027 | Range 0..31.\r | |
1028 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1029 | Range 0..31.\r | |
1030 | \r | |
1031 | @return The value of the bit field read from the PCI configuration register.\r | |
1032 | \r | |
1033 | **/\r | |
1034 | UINT32\r | |
1035 | EFIAPI\r | |
1036 | PciBitFieldRead32 (\r | |
1037 | IN UINTN Address,\r | |
1038 | IN UINTN StartBit,\r | |
1039 | IN UINTN EndBit\r | |
1040 | )\r | |
1041 | {\r | |
1042 | return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r | |
1043 | }\r | |
1044 | \r | |
1045 | /**\r | |
1046 | Writes a bit field to a PCI configuration register.\r | |
1047 | \r | |
1048 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1049 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1050 | destination PCI configuration register are preserved. The new value of the\r | |
1051 | 32-bit register is returned.\r | |
1052 | \r | |
1053 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1054 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1055 | If StartBit is greater than 31, then ASSERT().\r | |
1056 | If EndBit is greater than 31, then ASSERT().\r | |
1057 | If EndBit is less than StartBit, then ASSERT().\r | |
1058 | \r | |
2fc59a00 | 1059 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1060 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1061 | Range 0..31.\r | |
1062 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1063 | Range 0..31.\r | |
2fc59a00 | 1064 | @param Value The new value of the bit field.\r |
1a3eaf06 | 1065 | \r |
1066 | @return The value written back to the PCI configuration register.\r | |
1067 | \r | |
1068 | **/\r | |
1069 | UINT32\r | |
1070 | EFIAPI\r | |
1071 | PciBitFieldWrite32 (\r | |
1072 | IN UINTN Address,\r | |
1073 | IN UINTN StartBit,\r | |
1074 | IN UINTN EndBit,\r | |
1075 | IN UINT32 Value\r | |
1076 | )\r | |
1077 | {\r | |
1078 | return PciWrite32 (\r | |
1079 | Address,\r | |
1080 | BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)\r | |
1081 | );\r | |
1082 | }\r | |
1083 | \r | |
1084 | /**\r | |
1085 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1086 | writes the result back to the bit field in the 32-bit port.\r | |
1087 | \r | |
1088 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1089 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 1090 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1091 | specified by Address. The value written to the PCI configuration register is\r | |
1092 | returned. This function must guarantee that all PCI read and write operations\r | |
1093 | are serialized. Extra left bits in OrData are stripped.\r | |
1094 | \r | |
1095 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1096 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1097 | If StartBit is greater than 31, then ASSERT().\r | |
1098 | If EndBit is greater than 31, then ASSERT().\r | |
1099 | If EndBit is less than StartBit, then ASSERT().\r | |
1100 | \r | |
2fc59a00 | 1101 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1102 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1103 | Range 0..31.\r | |
1104 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1105 | Range 0..31.\r | |
1106 | @param OrData The value to OR with the PCI configuration register.\r | |
1107 | \r | |
1108 | @return The value written back to the PCI configuration register.\r | |
1109 | \r | |
1110 | **/\r | |
1111 | UINT32\r | |
1112 | EFIAPI\r | |
1113 | PciBitFieldOr32 (\r | |
1114 | IN UINTN Address,\r | |
1115 | IN UINTN StartBit,\r | |
1116 | IN UINTN EndBit,\r | |
1117 | IN UINT32 OrData\r | |
1118 | )\r | |
1119 | {\r | |
1120 | return PciWrite32 (\r | |
1121 | Address,\r | |
1122 | BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)\r | |
1123 | );\r | |
1124 | }\r | |
1125 | \r | |
1126 | /**\r | |
1127 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1128 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1129 | \r | |
1130 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1131 | bitwise AND between the read result and the value specified by AndData, and\r | |
1132 | writes the result to the 32-bit PCI configuration register specified by\r | |
1133 | Address. The value written to the PCI configuration register is returned.\r | |
1134 | This function must guarantee that all PCI read and write operations are\r | |
1135 | serialized. Extra left bits in AndData are stripped.\r | |
1136 | \r | |
1137 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1138 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1139 | If StartBit is greater than 31, then ASSERT().\r | |
1140 | If EndBit is greater than 31, then ASSERT().\r | |
1141 | If EndBit is less than StartBit, then ASSERT().\r | |
1142 | \r | |
2fc59a00 | 1143 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1144 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1145 | Range 0..31.\r | |
1146 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1147 | Range 0..31.\r | |
1148 | @param AndData The value to AND with the PCI configuration register.\r | |
1149 | \r | |
1150 | @return The value written back to the PCI configuration register.\r | |
1151 | \r | |
1152 | **/\r | |
1153 | UINT32\r | |
1154 | EFIAPI\r | |
1155 | PciBitFieldAnd32 (\r | |
1156 | IN UINTN Address,\r | |
1157 | IN UINTN StartBit,\r | |
1158 | IN UINTN EndBit,\r | |
1159 | IN UINT32 AndData\r | |
1160 | )\r | |
1161 | {\r | |
1162 | return PciWrite32 (\r | |
1163 | Address,\r | |
1164 | BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)\r | |
1165 | );\r | |
1166 | }\r | |
1167 | \r | |
1168 | /**\r | |
1169 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1170 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 1171 | 32-bit port.\r |
1172 | \r | |
1173 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1174 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 1175 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1176 | configuration register specified by Address. The value written to the PCI\r | |
1177 | configuration register is returned. This function must guarantee that all PCI\r | |
1178 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1179 | OrData are stripped.\r | |
1180 | \r | |
1181 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1182 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1183 | If StartBit is greater than 31, then ASSERT().\r | |
1184 | If EndBit is greater than 31, then ASSERT().\r | |
1185 | If EndBit is less than StartBit, then ASSERT().\r | |
1186 | \r | |
2fc59a00 | 1187 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1188 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1189 | Range 0..31.\r | |
1190 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1191 | Range 0..31.\r | |
1192 | @param AndData The value to AND with the PCI configuration register.\r | |
1193 | @param OrData The value to OR with the result of the AND operation.\r | |
1194 | \r | |
1195 | @return The value written back to the PCI configuration register.\r | |
1196 | \r | |
1197 | **/\r | |
1198 | UINT32\r | |
1199 | EFIAPI\r | |
1200 | PciBitFieldAndThenOr32 (\r | |
1201 | IN UINTN Address,\r | |
1202 | IN UINTN StartBit,\r | |
1203 | IN UINTN EndBit,\r | |
1204 | IN UINT32 AndData,\r | |
1205 | IN UINT32 OrData\r | |
1206 | )\r | |
1207 | {\r | |
1208 | return PciWrite32 (\r | |
1209 | Address,\r | |
1210 | BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1211 | );\r | |
1212 | }\r | |
1213 | \r | |
1214 | /**\r | |
1215 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1216 | \r | |
1217 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1218 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1219 | configuration registers from a single PCI function to be read. Size is\r | |
1220 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1221 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1222 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1223 | end of the range.\r | |
1224 | \r | |
1225 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1226 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1227 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1228 | \r | |
2fc59a00 | 1229 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
1a3eaf06 | 1230 | Function and Register.\r |
2fc59a00 | 1231 | @param Size The size in bytes of the transfer.\r |
1232 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1a3eaf06 | 1233 | \r |
1234 | @return Size\r | |
1235 | \r | |
1236 | **/\r | |
1237 | UINTN\r | |
1238 | EFIAPI\r | |
1239 | PciReadBuffer (\r | |
1240 | IN UINTN StartAddress,\r | |
1241 | IN UINTN Size,\r | |
1242 | OUT VOID *Buffer\r | |
1243 | )\r | |
1244 | {\r | |
1245 | UINTN ReturnValue;\r | |
1246 | \r | |
1247 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1248 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1249 | \r |
1250 | if (Size == 0) {\r | |
1251 | return Size;\r | |
1252 | }\r | |
1253 | \r | |
1254 | ASSERT (Buffer != NULL);\r | |
1255 | \r | |
1256 | //\r | |
1257 | // Save Size for return\r | |
1258 | //\r | |
1259 | ReturnValue = Size;\r | |
1260 | \r | |
e43e4b3e | 1261 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1262 | //\r |
1263 | // Read a byte if StartAddress is byte aligned\r | |
1264 | //\r | |
1265 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1266 | StartAddress += sizeof (UINT8);\r | |
1267 | Size -= sizeof (UINT8);\r | |
1268 | Buffer = (UINT8*)Buffer + 1;\r | |
1269 | }\r | |
1270 | \r | |
e43e4b3e | 1271 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1272 | //\r |
1273 | // Read a word if StartAddress is word aligned\r | |
1274 | //\r | |
5dc4fd78 | 1275 | WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r |
1a3eaf06 | 1276 | StartAddress += sizeof (UINT16);\r |
1277 | Size -= sizeof (UINT16);\r | |
1278 | Buffer = (UINT16*)Buffer + 1;\r | |
1279 | }\r | |
1280 | \r | |
1281 | while (Size >= sizeof (UINT32)) {\r | |
1282 | //\r | |
1283 | // Read as many double words as possible\r | |
1284 | //\r | |
5dc4fd78 | 1285 | WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r |
1a3eaf06 | 1286 | StartAddress += sizeof (UINT32);\r |
1287 | Size -= sizeof (UINT32);\r | |
1288 | Buffer = (UINT32*)Buffer + 1;\r | |
1289 | }\r | |
1290 | \r | |
1291 | if (Size >= sizeof (UINT16)) {\r | |
1292 | //\r | |
1293 | // Read the last remaining word if exist\r | |
1294 | //\r | |
5dc4fd78 | 1295 | WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r |
1a3eaf06 | 1296 | StartAddress += sizeof (UINT16);\r |
1297 | Size -= sizeof (UINT16);\r | |
1298 | Buffer = (UINT16*)Buffer + 1;\r | |
1299 | }\r | |
1300 | \r | |
1301 | if (Size >= sizeof (UINT8)) {\r | |
1302 | //\r | |
1303 | // Read the last remaining byte if exist\r | |
1304 | //\r | |
1305 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1306 | }\r | |
1307 | \r | |
1308 | return ReturnValue;\r | |
1309 | }\r | |
1310 | \r | |
1311 | /**\r | |
1312 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1313 | configuration space.\r | |
1314 | \r | |
1315 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1316 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1317 | configuration registers from a single PCI function to be written. Size is\r | |
1318 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1319 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1320 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1321 | and the end of the range.\r | |
1322 | \r | |
1323 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1324 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1325 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1326 | \r | |
2fc59a00 | 1327 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
1a3eaf06 | 1328 | Function and Register.\r |
2fc59a00 | 1329 | @param Size The size in bytes of the transfer.\r |
1330 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1a3eaf06 | 1331 | \r |
0c3437e0 | 1332 | @return Size written to StartAddress.\r |
1a3eaf06 | 1333 | \r |
1334 | **/\r | |
1335 | UINTN\r | |
1336 | EFIAPI\r | |
1337 | PciWriteBuffer (\r | |
1338 | IN UINTN StartAddress,\r | |
1339 | IN UINTN Size,\r | |
1340 | IN VOID *Buffer\r | |
1341 | )\r | |
1342 | {\r | |
1343 | UINTN ReturnValue;\r | |
1344 | \r | |
1345 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1346 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1347 | \r |
1348 | if (Size == 0) {\r | |
1349 | return 0;\r | |
1350 | }\r | |
1351 | \r | |
1352 | ASSERT (Buffer != NULL);\r | |
1353 | \r | |
1354 | //\r | |
1355 | // Save Size for return\r | |
1356 | //\r | |
1357 | ReturnValue = Size;\r | |
1358 | \r | |
e43e4b3e | 1359 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1360 | //\r |
1361 | // Write a byte if StartAddress is byte aligned\r | |
1362 | //\r | |
1363 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1364 | StartAddress += sizeof (UINT8);\r | |
1365 | Size -= sizeof (UINT8);\r | |
1366 | Buffer = (UINT8*)Buffer + 1;\r | |
1367 | }\r | |
1368 | \r | |
e43e4b3e | 1369 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1370 | //\r |
1371 | // Write a word if StartAddress is word aligned\r | |
1372 | //\r | |
5dc4fd78 | 1373 | PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1374 | StartAddress += sizeof (UINT16);\r |
1375 | Size -= sizeof (UINT16);\r | |
1376 | Buffer = (UINT16*)Buffer + 1;\r | |
1377 | }\r | |
1378 | \r | |
1379 | while (Size >= sizeof (UINT32)) {\r | |
1380 | //\r | |
1381 | // Write as many double words as possible\r | |
1382 | //\r | |
5dc4fd78 | 1383 | PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r |
1a3eaf06 | 1384 | StartAddress += sizeof (UINT32);\r |
1385 | Size -= sizeof (UINT32);\r | |
1386 | Buffer = (UINT32*)Buffer + 1;\r | |
1387 | }\r | |
1388 | \r | |
1389 | if (Size >= sizeof (UINT16)) {\r | |
1390 | //\r | |
1391 | // Write the last remaining word if exist\r | |
1392 | //\r | |
5dc4fd78 | 1393 | PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1394 | StartAddress += sizeof (UINT16);\r |
1395 | Size -= sizeof (UINT16);\r | |
1396 | Buffer = (UINT16*)Buffer + 1;\r | |
1397 | }\r | |
1398 | \r | |
1399 | if (Size >= sizeof (UINT8)) {\r | |
1400 | //\r | |
1401 | // Write the last remaining byte if exist\r | |
1402 | //\r | |
1403 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1404 | }\r | |
1405 | \r | |
1406 | return ReturnValue;\r | |
1407 | }\r |