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84ace59f LG |
1 | /** @file\r |
2 | Functions in this library instance make use of MMIO functions in IoLib to\r | |
3 | access memory mapped PCI configuration space.\r | |
4 | \r | |
5 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r | |
6 | Library.\r | |
7 | \r | |
8 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.\r | |
9 | Portions copyright (c) 2016, American Megatrends, Inc. All rights reserved.\r | |
9344f092 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
84ace59f LG |
11 | \r |
12 | **/\r | |
13 | \r | |
14 | #include <PiDxe.h>\r | |
15 | \r | |
16 | #include <Library/BaseLib.h>\r | |
17 | #include <Library/PciExpressLib.h>\r | |
18 | #include <Library/IoLib.h>\r | |
19 | #include <Library/DebugLib.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | \r | |
22 | ///\r | |
5c065855 | 23 | /// Module global that contains the base physical address and size of the PCI Express MMIO range.\r |
84ace59f LG |
24 | ///\r |
25 | UINTN mSmmPciExpressLibPciExpressBaseAddress = 0;\r | |
5c065855 | 26 | UINTN mSmmPciExpressLibPciExpressBaseSize = 0;\r |
84ace59f LG |
27 | \r |
28 | /**\r | |
29 | The constructor function caches the PCI Express Base Address\r | |
30 | \r | |
31 | @param ImageHandle The firmware allocated handle for the EFI image.\r | |
32 | @param SystemTable A pointer to the EFI System Table.\r | |
33 | \r | |
34 | @retval EFI_SUCCESS The constructor completed successfully.\r | |
35 | **/\r | |
36 | EFI_STATUS\r | |
37 | EFIAPI\r | |
38 | SmmPciExpressLibConstructor (\r | |
39 | IN EFI_HANDLE ImageHandle,\r | |
40 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
41 | )\r | |
42 | {\r | |
43 | //\r | |
5c065855 | 44 | // Cache the physical address and size of the PCI Express MMIO range into a module global variable\r |
84ace59f LG |
45 | //\r |
46 | mSmmPciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r | |
5c065855 | 47 | mSmmPciExpressLibPciExpressBaseSize = (UINTN) PcdGet64 (PcdPciExpressBaseSize);\r |
84ace59f LG |
48 | \r |
49 | return EFI_SUCCESS;\r | |
50 | }\r | |
51 | \r | |
52 | /**\r | |
53 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
54 | only in the low 28 bits.\r | |
55 | \r | |
56 | @param A The address to validate.\r | |
57 | \r | |
58 | **/\r | |
59 | #define ASSERT_INVALID_PCI_ADDRESS(A) \\r | |
60 | ASSERT (((A) & ~0xfffffff) == 0)\r | |
61 | \r | |
62 | /**\r | |
63 | Registers a PCI device so PCI configuration registers may be accessed after\r | |
64 | SetVirtualAddressMap().\r | |
65 | \r | |
66 | Registers the PCI device specified by Address so all the PCI configuration\r | |
67 | registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r | |
68 | is called.\r | |
69 | \r | |
70 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
71 | \r | |
72 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
73 | Register.\r | |
74 | \r | |
75 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
76 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r | |
77 | after ExitBootServices().\r | |
78 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
79 | at runtime could not be mapped.\r | |
80 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
81 | complete the registration.\r | |
82 | \r | |
83 | **/\r | |
84 | RETURN_STATUS\r | |
85 | EFIAPI\r | |
86 | PciExpressRegisterForRuntimeAccess (\r | |
87 | IN UINTN Address\r | |
88 | )\r | |
89 | {\r | |
90 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
91 | return RETURN_UNSUPPORTED;\r | |
92 | }\r | |
93 | \r | |
94 | /**\r | |
95 | Gets MMIO address that can be used to access PCI Express location defined by Address.\r | |
96 | \r | |
97 | This internal functions converts PCI Express address to a CPU MMIO address by adding\r | |
98 | PCI Express Base Address stored in a global variable mSmmPciExpressLibPciExpressBaseAddress.\r | |
99 | mSmmPciExpressLibPciExpressBaseAddress is initialized in the library constructor from PCD entry\r | |
100 | PcdPciExpressBaseAddress.\r | |
101 | \r | |
5c065855 MSB |
102 | If Address > 0x0FFFFFFF, then ASSERT().\r |
103 | \r | |
84ace59f | 104 | @param Address The address that encodes the PCI Bus, Device, Function and Register.\r |
5c065855 MSB |
105 | \r |
106 | @retval (UINTN)-1 Invalid PCI address.\r | |
107 | @retval other MMIO address corresponding to Address.\r | |
84ace59f LG |
108 | \r |
109 | **/\r | |
110 | UINTN\r | |
111 | GetPciExpressAddress (\r | |
112 | IN UINTN Address\r | |
113 | )\r | |
114 | {\r | |
115 | //\r | |
116 | // Make sure Address is valid\r | |
117 | //\r | |
118 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
5c065855 MSB |
119 | //\r |
120 | // Make sure the Address is in MMCONF address space\r | |
121 | //\r | |
122 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r | |
123 | return (UINTN) -1;\r | |
124 | }\r | |
84ace59f LG |
125 | return mSmmPciExpressLibPciExpressBaseAddress + Address;\r |
126 | }\r | |
127 | \r | |
128 | /**\r | |
129 | Reads an 8-bit PCI configuration register.\r | |
130 | \r | |
131 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
132 | This function must guarantee that all PCI read and write operations are\r | |
133 | serialized.\r | |
134 | \r | |
135 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
136 | \r | |
137 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
138 | Register.\r | |
139 | \r | |
5c065855 MSB |
140 | @retval 0xFF Invalid PCI address.\r |
141 | @retval other The read value from the PCI configuration register.\r | |
84ace59f LG |
142 | \r |
143 | **/\r | |
144 | UINT8\r | |
145 | EFIAPI\r | |
146 | PciExpressRead8 (\r | |
147 | IN UINTN Address\r | |
148 | )\r | |
149 | {\r | |
5c065855 MSB |
150 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
151 | return (UINT8) -1;\r | |
152 | }\r | |
84ace59f LG |
153 | return MmioRead8 (GetPciExpressAddress (Address));\r |
154 | }\r | |
155 | \r | |
156 | /**\r | |
157 | Writes an 8-bit PCI configuration register.\r | |
158 | \r | |
159 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
160 | value specified by Value. Value is returned. This function must guarantee\r | |
161 | that all PCI read and write operations are serialized.\r | |
162 | \r | |
163 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
164 | \r | |
165 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
166 | Register.\r | |
167 | @param Value The value to write.\r | |
168 | \r | |
5c065855 MSB |
169 | @retval 0xFF Invalid PCI address.\r |
170 | @retval other The value written to the PCI configuration register.\r | |
84ace59f LG |
171 | \r |
172 | **/\r | |
173 | UINT8\r | |
174 | EFIAPI\r | |
175 | PciExpressWrite8 (\r | |
176 | IN UINTN Address,\r | |
177 | IN UINT8 Value\r | |
178 | )\r | |
179 | {\r | |
5c065855 MSB |
180 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
181 | return (UINT8) -1;\r | |
182 | }\r | |
84ace59f LG |
183 | return MmioWrite8 (GetPciExpressAddress (Address), Value);\r |
184 | }\r | |
185 | \r | |
186 | /**\r | |
187 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
188 | an 8-bit value.\r | |
189 | \r | |
190 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
191 | bitwise OR between the read result and the value specified by\r | |
192 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
193 | specified by Address. The value written to the PCI configuration register is\r | |
194 | returned. This function must guarantee that all PCI read and write operations\r | |
195 | are serialized.\r | |
196 | \r | |
197 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
198 | \r | |
199 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
200 | Register.\r | |
201 | @param OrData The value to OR with the PCI configuration register.\r | |
202 | \r | |
5c065855 MSB |
203 | @retval 0xFF Invalid PCI address.\r |
204 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
205 | \r |
206 | **/\r | |
207 | UINT8\r | |
208 | EFIAPI\r | |
209 | PciExpressOr8 (\r | |
210 | IN UINTN Address,\r | |
211 | IN UINT8 OrData\r | |
212 | )\r | |
213 | {\r | |
5c065855 MSB |
214 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
215 | return (UINT8) -1;\r | |
216 | }\r | |
84ace59f LG |
217 | return MmioOr8 (GetPciExpressAddress (Address), OrData);\r |
218 | }\r | |
219 | \r | |
220 | /**\r | |
221 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
222 | value.\r | |
223 | \r | |
224 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
225 | bitwise AND between the read result and the value specified by AndData, and\r | |
226 | writes the result to the 8-bit PCI configuration register specified by\r | |
227 | Address. The value written to the PCI configuration register is returned.\r | |
228 | This function must guarantee that all PCI read and write operations are\r | |
229 | serialized.\r | |
230 | \r | |
231 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
232 | \r | |
233 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
234 | Register.\r | |
235 | @param AndData The value to AND with the PCI configuration register.\r | |
236 | \r | |
5c065855 MSB |
237 | @retval 0xFF Invalid PCI address.\r |
238 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
239 | \r |
240 | **/\r | |
241 | UINT8\r | |
242 | EFIAPI\r | |
243 | PciExpressAnd8 (\r | |
244 | IN UINTN Address,\r | |
245 | IN UINT8 AndData\r | |
246 | )\r | |
247 | {\r | |
5c065855 MSB |
248 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
249 | return (UINT8) -1;\r | |
250 | }\r | |
84ace59f LG |
251 | return MmioAnd8 (GetPciExpressAddress (Address), AndData);\r |
252 | }\r | |
253 | \r | |
254 | /**\r | |
255 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
256 | value, followed a bitwise OR with another 8-bit value.\r | |
257 | \r | |
258 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
259 | bitwise AND between the read result and the value specified by AndData,\r | |
260 | performs a bitwise OR between the result of the AND operation and\r | |
261 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
262 | configuration register specified by Address. The value written to the PCI\r | |
263 | configuration register is returned. This function must guarantee that all PCI\r | |
264 | read and write operations are serialized.\r | |
265 | \r | |
266 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
267 | \r | |
268 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
269 | Register.\r | |
270 | @param AndData The value to AND with the PCI configuration register.\r | |
271 | @param OrData The value to OR with the result of the AND operation.\r | |
272 | \r | |
5c065855 MSB |
273 | @retval 0xFF Invalid PCI address.\r |
274 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
275 | \r |
276 | **/\r | |
277 | UINT8\r | |
278 | EFIAPI\r | |
279 | PciExpressAndThenOr8 (\r | |
280 | IN UINTN Address,\r | |
281 | IN UINT8 AndData,\r | |
282 | IN UINT8 OrData\r | |
283 | )\r | |
284 | {\r | |
5c065855 MSB |
285 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
286 | return (UINT8) -1;\r | |
287 | }\r | |
84ace59f LG |
288 | return MmioAndThenOr8 (\r |
289 | GetPciExpressAddress (Address),\r | |
290 | AndData,\r | |
291 | OrData\r | |
292 | );\r | |
293 | }\r | |
294 | \r | |
295 | /**\r | |
296 | Reads a bit field of a PCI configuration register.\r | |
297 | \r | |
298 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
299 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
300 | returned.\r | |
301 | \r | |
302 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
303 | If StartBit is greater than 7, then ASSERT().\r | |
304 | If EndBit is greater than 7, then ASSERT().\r | |
305 | If EndBit is less than StartBit, then ASSERT().\r | |
306 | \r | |
307 | @param Address The PCI configuration register to read.\r | |
308 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
309 | Range 0..7.\r | |
310 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
311 | Range 0..7.\r | |
312 | \r | |
5c065855 MSB |
313 | @retval 0xFF Invalid PCI address.\r |
314 | @retval other The value of the bit field read from the PCI configuration register.\r | |
84ace59f LG |
315 | \r |
316 | **/\r | |
317 | UINT8\r | |
318 | EFIAPI\r | |
319 | PciExpressBitFieldRead8 (\r | |
320 | IN UINTN Address,\r | |
321 | IN UINTN StartBit,\r | |
322 | IN UINTN EndBit\r | |
323 | )\r | |
324 | {\r | |
5c065855 MSB |
325 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
326 | return (UINT8) -1;\r | |
327 | }\r | |
84ace59f LG |
328 | return MmioBitFieldRead8 (\r |
329 | GetPciExpressAddress (Address),\r | |
330 | StartBit,\r | |
331 | EndBit\r | |
332 | );\r | |
333 | }\r | |
334 | \r | |
335 | /**\r | |
336 | Writes a bit field to a PCI configuration register.\r | |
337 | \r | |
338 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
339 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
340 | destination PCI configuration register are preserved. The new value of the\r | |
341 | 8-bit register is returned.\r | |
342 | \r | |
343 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
344 | If StartBit is greater than 7, then ASSERT().\r | |
345 | If EndBit is greater than 7, then ASSERT().\r | |
346 | If EndBit is less than StartBit, then ASSERT().\r | |
347 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
348 | \r | |
349 | @param Address The PCI configuration register to write.\r | |
350 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
351 | Range 0..7.\r | |
352 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
353 | Range 0..7.\r | |
354 | @param Value The new value of the bit field.\r | |
355 | \r | |
5c065855 MSB |
356 | @retval 0xFF Invalid PCI address.\r |
357 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
358 | \r |
359 | **/\r | |
360 | UINT8\r | |
361 | EFIAPI\r | |
362 | PciExpressBitFieldWrite8 (\r | |
363 | IN UINTN Address,\r | |
364 | IN UINTN StartBit,\r | |
365 | IN UINTN EndBit,\r | |
366 | IN UINT8 Value\r | |
367 | )\r | |
368 | {\r | |
5c065855 MSB |
369 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
370 | return (UINT8) -1;\r | |
371 | }\r | |
84ace59f LG |
372 | return MmioBitFieldWrite8 (\r |
373 | GetPciExpressAddress (Address),\r | |
374 | StartBit,\r | |
375 | EndBit,\r | |
376 | Value\r | |
377 | );\r | |
378 | }\r | |
379 | \r | |
380 | /**\r | |
381 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
382 | writes the result back to the bit field in the 8-bit port.\r | |
383 | \r | |
384 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
385 | bitwise OR between the read result and the value specified by\r | |
386 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
387 | specified by Address. The value written to the PCI configuration register is\r | |
388 | returned. This function must guarantee that all PCI read and write operations\r | |
389 | are serialized. Extra left bits in OrData are stripped.\r | |
390 | \r | |
391 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
392 | If StartBit is greater than 7, then ASSERT().\r | |
393 | If EndBit is greater than 7, then ASSERT().\r | |
394 | If EndBit is less than StartBit, then ASSERT().\r | |
395 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
396 | \r | |
397 | @param Address The PCI configuration register to write.\r | |
398 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
399 | Range 0..7.\r | |
400 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
401 | Range 0..7.\r | |
402 | @param OrData The value to OR with the PCI configuration register.\r | |
403 | \r | |
5c065855 MSB |
404 | @retval 0xFF Invalid PCI address.\r |
405 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
406 | \r |
407 | **/\r | |
408 | UINT8\r | |
409 | EFIAPI\r | |
410 | PciExpressBitFieldOr8 (\r | |
411 | IN UINTN Address,\r | |
412 | IN UINTN StartBit,\r | |
413 | IN UINTN EndBit,\r | |
414 | IN UINT8 OrData\r | |
415 | )\r | |
416 | {\r | |
5c065855 MSB |
417 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
418 | return (UINT8) -1;\r | |
419 | }\r | |
84ace59f LG |
420 | return MmioBitFieldOr8 (\r |
421 | GetPciExpressAddress (Address),\r | |
422 | StartBit,\r | |
423 | EndBit,\r | |
424 | OrData\r | |
425 | );\r | |
426 | }\r | |
427 | \r | |
428 | /**\r | |
429 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
430 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
431 | \r | |
432 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
433 | bitwise AND between the read result and the value specified by AndData, and\r | |
434 | writes the result to the 8-bit PCI configuration register specified by\r | |
435 | Address. The value written to the PCI configuration register is returned.\r | |
436 | This function must guarantee that all PCI read and write operations are\r | |
437 | serialized. Extra left bits in AndData are stripped.\r | |
438 | \r | |
439 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
440 | If StartBit is greater than 7, then ASSERT().\r | |
441 | If EndBit is greater than 7, then ASSERT().\r | |
442 | If EndBit is less than StartBit, then ASSERT().\r | |
443 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
444 | \r | |
445 | @param Address The PCI configuration register to write.\r | |
446 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
447 | Range 0..7.\r | |
448 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
449 | Range 0..7.\r | |
450 | @param AndData The value to AND with the PCI configuration register.\r | |
451 | \r | |
5c065855 MSB |
452 | @retval 0xFF Invalid PCI address.\r |
453 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
454 | \r |
455 | **/\r | |
456 | UINT8\r | |
457 | EFIAPI\r | |
458 | PciExpressBitFieldAnd8 (\r | |
459 | IN UINTN Address,\r | |
460 | IN UINTN StartBit,\r | |
461 | IN UINTN EndBit,\r | |
462 | IN UINT8 AndData\r | |
463 | )\r | |
464 | {\r | |
5c065855 MSB |
465 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
466 | return (UINT8) -1;\r | |
467 | }\r | |
84ace59f LG |
468 | return MmioBitFieldAnd8 (\r |
469 | GetPciExpressAddress (Address),\r | |
470 | StartBit,\r | |
471 | EndBit,\r | |
472 | AndData\r | |
473 | );\r | |
474 | }\r | |
475 | \r | |
476 | /**\r | |
477 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
478 | bitwise OR, and writes the result back to the bit field in the\r | |
479 | 8-bit port.\r | |
480 | \r | |
481 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
482 | bitwise AND followed by a bitwise OR between the read result and\r | |
483 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
484 | configuration register specified by Address. The value written to the PCI\r | |
485 | configuration register is returned. This function must guarantee that all PCI\r | |
486 | read and write operations are serialized. Extra left bits in both AndData and\r | |
487 | OrData are stripped.\r | |
488 | \r | |
489 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
490 | If StartBit is greater than 7, then ASSERT().\r | |
491 | If EndBit is greater than 7, then ASSERT().\r | |
492 | If EndBit is less than StartBit, then ASSERT().\r | |
493 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
494 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
495 | \r | |
496 | @param Address The PCI configuration register to write.\r | |
497 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
498 | Range 0..7.\r | |
499 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
500 | Range 0..7.\r | |
501 | @param AndData The value to AND with the PCI configuration register.\r | |
502 | @param OrData The value to OR with the result of the AND operation.\r | |
503 | \r | |
5c065855 MSB |
504 | @retval 0xFF Invalid PCI address.\r |
505 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
506 | \r |
507 | **/\r | |
508 | UINT8\r | |
509 | EFIAPI\r | |
510 | PciExpressBitFieldAndThenOr8 (\r | |
511 | IN UINTN Address,\r | |
512 | IN UINTN StartBit,\r | |
513 | IN UINTN EndBit,\r | |
514 | IN UINT8 AndData,\r | |
515 | IN UINT8 OrData\r | |
516 | )\r | |
517 | {\r | |
5c065855 MSB |
518 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
519 | return (UINT8) -1;\r | |
520 | }\r | |
84ace59f LG |
521 | return MmioBitFieldAndThenOr8 (\r |
522 | GetPciExpressAddress (Address),\r | |
523 | StartBit,\r | |
524 | EndBit,\r | |
525 | AndData,\r | |
526 | OrData\r | |
527 | );\r | |
528 | }\r | |
529 | \r | |
530 | /**\r | |
531 | Reads a 16-bit PCI configuration register.\r | |
532 | \r | |
533 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
534 | This function must guarantee that all PCI read and write operations are\r | |
535 | serialized.\r | |
536 | \r | |
537 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
538 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
539 | \r | |
540 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
541 | Register.\r | |
542 | \r | |
5c065855 MSB |
543 | @retval 0xFF Invalid PCI address.\r |
544 | @retval other The read value from the PCI configuration register.\r | |
84ace59f LG |
545 | \r |
546 | **/\r | |
547 | UINT16\r | |
548 | EFIAPI\r | |
549 | PciExpressRead16 (\r | |
550 | IN UINTN Address\r | |
551 | )\r | |
552 | {\r | |
5c065855 MSB |
553 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
554 | return (UINT16) -1;\r | |
555 | }\r | |
84ace59f LG |
556 | return MmioRead16 (GetPciExpressAddress (Address));\r |
557 | }\r | |
558 | \r | |
559 | /**\r | |
560 | Writes a 16-bit PCI configuration register.\r | |
561 | \r | |
562 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
563 | value specified by Value. Value is returned. This function must guarantee\r | |
564 | that all PCI read and write operations are serialized.\r | |
565 | \r | |
566 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
567 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
568 | \r | |
569 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
570 | Register.\r | |
571 | @param Value The value to write.\r | |
572 | \r | |
5c065855 MSB |
573 | @retval 0xFFFF Invalid PCI address.\r |
574 | @retval other The value written to the PCI configuration register.\r | |
84ace59f LG |
575 | \r |
576 | **/\r | |
577 | UINT16\r | |
578 | EFIAPI\r | |
579 | PciExpressWrite16 (\r | |
580 | IN UINTN Address,\r | |
581 | IN UINT16 Value\r | |
582 | )\r | |
583 | {\r | |
5c065855 MSB |
584 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
585 | return (UINT16) -1;\r | |
586 | }\r | |
84ace59f LG |
587 | return MmioWrite16 (GetPciExpressAddress (Address), Value);\r |
588 | }\r | |
589 | \r | |
590 | /**\r | |
591 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
592 | a 16-bit value.\r | |
593 | \r | |
594 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
595 | bitwise OR between the read result and the value specified by\r | |
596 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
597 | specified by Address. The value written to the PCI configuration register is\r | |
598 | returned. This function must guarantee that all PCI read and write operations\r | |
599 | are serialized.\r | |
600 | \r | |
601 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
602 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
603 | \r | |
604 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
605 | Register.\r | |
606 | @param OrData The value to OR with the PCI configuration register.\r | |
607 | \r | |
5c065855 MSB |
608 | @retval 0xFFFF Invalid PCI address.\r |
609 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
610 | \r |
611 | **/\r | |
612 | UINT16\r | |
613 | EFIAPI\r | |
614 | PciExpressOr16 (\r | |
615 | IN UINTN Address,\r | |
616 | IN UINT16 OrData\r | |
617 | )\r | |
618 | {\r | |
5c065855 MSB |
619 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
620 | return (UINT16) -1;\r | |
621 | }\r | |
84ace59f LG |
622 | return MmioOr16 (GetPciExpressAddress (Address), OrData);\r |
623 | }\r | |
624 | \r | |
625 | /**\r | |
626 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
627 | value.\r | |
628 | \r | |
629 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
630 | bitwise AND between the read result and the value specified by AndData, and\r | |
631 | writes the result to the 16-bit PCI configuration register specified by\r | |
632 | Address. The value written to the PCI configuration register is returned.\r | |
633 | This function must guarantee that all PCI read and write operations are\r | |
634 | serialized.\r | |
635 | \r | |
636 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
637 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
638 | \r | |
639 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
640 | Register.\r | |
641 | @param AndData The value to AND with the PCI configuration register.\r | |
642 | \r | |
5c065855 MSB |
643 | @retval 0xFFFF Invalid PCI address.\r |
644 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
645 | \r |
646 | **/\r | |
647 | UINT16\r | |
648 | EFIAPI\r | |
649 | PciExpressAnd16 (\r | |
650 | IN UINTN Address,\r | |
651 | IN UINT16 AndData\r | |
652 | )\r | |
653 | {\r | |
5c065855 MSB |
654 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
655 | return (UINT16) -1;\r | |
656 | }\r | |
84ace59f LG |
657 | return MmioAnd16 (GetPciExpressAddress (Address), AndData);\r |
658 | }\r | |
659 | \r | |
660 | /**\r | |
661 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
662 | value, followed a bitwise OR with another 16-bit value.\r | |
663 | \r | |
664 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
665 | bitwise AND between the read result and the value specified by AndData,\r | |
666 | performs a bitwise OR between the result of the AND operation and\r | |
667 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
668 | configuration register specified by Address. The value written to the PCI\r | |
669 | configuration register is returned. This function must guarantee that all PCI\r | |
670 | read and write operations are serialized.\r | |
671 | \r | |
672 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
673 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
674 | \r | |
675 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
676 | Register.\r | |
677 | @param AndData The value to AND with the PCI configuration register.\r | |
678 | @param OrData The value to OR with the result of the AND operation.\r | |
679 | \r | |
5c065855 MSB |
680 | @retval 0xFFFF Invalid PCI address.\r |
681 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
682 | \r |
683 | **/\r | |
684 | UINT16\r | |
685 | EFIAPI\r | |
686 | PciExpressAndThenOr16 (\r | |
687 | IN UINTN Address,\r | |
688 | IN UINT16 AndData,\r | |
689 | IN UINT16 OrData\r | |
690 | )\r | |
691 | {\r | |
5c065855 MSB |
692 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
693 | return (UINT16) -1;\r | |
694 | }\r | |
84ace59f LG |
695 | return MmioAndThenOr16 (\r |
696 | GetPciExpressAddress (Address),\r | |
697 | AndData,\r | |
698 | OrData\r | |
699 | );\r | |
700 | }\r | |
701 | \r | |
702 | /**\r | |
703 | Reads a bit field of a PCI configuration register.\r | |
704 | \r | |
705 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
706 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
707 | returned.\r | |
708 | \r | |
709 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
710 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
711 | If StartBit is greater than 15, then ASSERT().\r | |
712 | If EndBit is greater than 15, then ASSERT().\r | |
713 | If EndBit is less than StartBit, then ASSERT().\r | |
714 | \r | |
715 | @param Address The PCI configuration register to read.\r | |
716 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
717 | Range 0..15.\r | |
718 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
719 | Range 0..15.\r | |
720 | \r | |
5c065855 MSB |
721 | @retval 0xFFFF Invalid PCI address.\r |
722 | @retval other The value of the bit field read from the PCI configuration register.\r | |
84ace59f LG |
723 | \r |
724 | **/\r | |
725 | UINT16\r | |
726 | EFIAPI\r | |
727 | PciExpressBitFieldRead16 (\r | |
728 | IN UINTN Address,\r | |
729 | IN UINTN StartBit,\r | |
730 | IN UINTN EndBit\r | |
731 | )\r | |
732 | {\r | |
5c065855 MSB |
733 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
734 | return (UINT16) -1;\r | |
735 | }\r | |
84ace59f LG |
736 | return MmioBitFieldRead16 (\r |
737 | GetPciExpressAddress (Address),\r | |
738 | StartBit,\r | |
739 | EndBit\r | |
740 | );\r | |
741 | }\r | |
742 | \r | |
743 | /**\r | |
744 | Writes a bit field to a PCI configuration register.\r | |
745 | \r | |
746 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
747 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
748 | destination PCI configuration register are preserved. The new value of the\r | |
749 | 16-bit register is returned.\r | |
750 | \r | |
751 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
752 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
753 | If StartBit is greater than 15, then ASSERT().\r | |
754 | If EndBit is greater than 15, then ASSERT().\r | |
755 | If EndBit is less than StartBit, then ASSERT().\r | |
756 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
757 | \r | |
758 | @param Address The PCI configuration register to write.\r | |
759 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
760 | Range 0..15.\r | |
761 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
762 | Range 0..15.\r | |
763 | @param Value The new value of the bit field.\r | |
764 | \r | |
5c065855 MSB |
765 | @retval 0xFFFF Invalid PCI address.\r |
766 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
767 | \r |
768 | **/\r | |
769 | UINT16\r | |
770 | EFIAPI\r | |
771 | PciExpressBitFieldWrite16 (\r | |
772 | IN UINTN Address,\r | |
773 | IN UINTN StartBit,\r | |
774 | IN UINTN EndBit,\r | |
775 | IN UINT16 Value\r | |
776 | )\r | |
777 | {\r | |
5c065855 MSB |
778 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
779 | return (UINT16) -1;\r | |
780 | }\r | |
84ace59f LG |
781 | return MmioBitFieldWrite16 (\r |
782 | GetPciExpressAddress (Address),\r | |
783 | StartBit,\r | |
784 | EndBit,\r | |
785 | Value\r | |
786 | );\r | |
787 | }\r | |
788 | \r | |
789 | /**\r | |
790 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
791 | writes the result back to the bit field in the 16-bit port.\r | |
792 | \r | |
793 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
794 | bitwise OR between the read result and the value specified by\r | |
795 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
796 | specified by Address. The value written to the PCI configuration register is\r | |
797 | returned. This function must guarantee that all PCI read and write operations\r | |
798 | are serialized. Extra left bits in OrData are stripped.\r | |
799 | \r | |
800 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
801 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
802 | If StartBit is greater than 15, then ASSERT().\r | |
803 | If EndBit is greater than 15, then ASSERT().\r | |
804 | If EndBit is less than StartBit, then ASSERT().\r | |
805 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
806 | \r | |
807 | @param Address The PCI configuration register to write.\r | |
808 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
809 | Range 0..15.\r | |
810 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
811 | Range 0..15.\r | |
812 | @param OrData The value to OR with the PCI configuration register.\r | |
813 | \r | |
5c065855 MSB |
814 | @retval 0xFFFF Invalid PCI address.\r |
815 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
816 | \r |
817 | **/\r | |
818 | UINT16\r | |
819 | EFIAPI\r | |
820 | PciExpressBitFieldOr16 (\r | |
821 | IN UINTN Address,\r | |
822 | IN UINTN StartBit,\r | |
823 | IN UINTN EndBit,\r | |
824 | IN UINT16 OrData\r | |
825 | )\r | |
826 | {\r | |
5c065855 MSB |
827 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
828 | return (UINT16) -1;\r | |
829 | }\r | |
84ace59f LG |
830 | return MmioBitFieldOr16 (\r |
831 | GetPciExpressAddress (Address),\r | |
832 | StartBit,\r | |
833 | EndBit,\r | |
834 | OrData\r | |
835 | );\r | |
836 | }\r | |
837 | \r | |
838 | /**\r | |
839 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
840 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
841 | \r | |
842 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
843 | bitwise AND between the read result and the value specified by AndData, and\r | |
844 | writes the result to the 16-bit PCI configuration register specified by\r | |
845 | Address. The value written to the PCI configuration register is returned.\r | |
846 | This function must guarantee that all PCI read and write operations are\r | |
847 | serialized. Extra left bits in AndData are stripped.\r | |
848 | \r | |
849 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
850 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
851 | If StartBit is greater than 15, then ASSERT().\r | |
852 | If EndBit is greater than 15, then ASSERT().\r | |
853 | If EndBit is less than StartBit, then ASSERT().\r | |
854 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
855 | \r | |
856 | @param Address The PCI configuration register to write.\r | |
857 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
858 | Range 0..15.\r | |
859 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
860 | Range 0..15.\r | |
861 | @param AndData The value to AND with the PCI configuration register.\r | |
862 | \r | |
5c065855 MSB |
863 | @retval 0xFFFF Invalid PCI address.\r |
864 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
865 | \r |
866 | **/\r | |
867 | UINT16\r | |
868 | EFIAPI\r | |
869 | PciExpressBitFieldAnd16 (\r | |
870 | IN UINTN Address,\r | |
871 | IN UINTN StartBit,\r | |
872 | IN UINTN EndBit,\r | |
873 | IN UINT16 AndData\r | |
874 | )\r | |
875 | {\r | |
5c065855 MSB |
876 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
877 | return (UINT16) -1;\r | |
878 | }\r | |
84ace59f LG |
879 | return MmioBitFieldAnd16 (\r |
880 | GetPciExpressAddress (Address),\r | |
881 | StartBit,\r | |
882 | EndBit,\r | |
883 | AndData\r | |
884 | );\r | |
885 | }\r | |
886 | \r | |
887 | /**\r | |
888 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
889 | bitwise OR, and writes the result back to the bit field in the\r | |
890 | 16-bit port.\r | |
891 | \r | |
892 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
893 | bitwise AND followed by a bitwise OR between the read result and\r | |
894 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
895 | configuration register specified by Address. The value written to the PCI\r | |
896 | configuration register is returned. This function must guarantee that all PCI\r | |
897 | read and write operations are serialized. Extra left bits in both AndData and\r | |
898 | OrData are stripped.\r | |
899 | \r | |
900 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
901 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
902 | If StartBit is greater than 15, then ASSERT().\r | |
903 | If EndBit is greater than 15, then ASSERT().\r | |
904 | If EndBit is less than StartBit, then ASSERT().\r | |
905 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
906 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
907 | \r | |
908 | @param Address The PCI configuration register to write.\r | |
909 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
910 | Range 0..15.\r | |
911 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
912 | Range 0..15.\r | |
913 | @param AndData The value to AND with the PCI configuration register.\r | |
914 | @param OrData The value to OR with the result of the AND operation.\r | |
915 | \r | |
5c065855 MSB |
916 | @retval 0xFFFF Invalid PCI address.\r |
917 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
918 | \r |
919 | **/\r | |
920 | UINT16\r | |
921 | EFIAPI\r | |
922 | PciExpressBitFieldAndThenOr16 (\r | |
923 | IN UINTN Address,\r | |
924 | IN UINTN StartBit,\r | |
925 | IN UINTN EndBit,\r | |
926 | IN UINT16 AndData,\r | |
927 | IN UINT16 OrData\r | |
928 | )\r | |
929 | {\r | |
5c065855 MSB |
930 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
931 | return (UINT16) -1;\r | |
932 | }\r | |
84ace59f LG |
933 | return MmioBitFieldAndThenOr16 (\r |
934 | GetPciExpressAddress (Address),\r | |
935 | StartBit,\r | |
936 | EndBit,\r | |
937 | AndData,\r | |
938 | OrData\r | |
939 | );\r | |
940 | }\r | |
941 | \r | |
942 | /**\r | |
943 | Reads a 32-bit PCI configuration register.\r | |
944 | \r | |
945 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
946 | This function must guarantee that all PCI read and write operations are\r | |
947 | serialized.\r | |
948 | \r | |
949 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
950 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
951 | \r | |
952 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
953 | Register.\r | |
954 | \r | |
5c065855 MSB |
955 | @retval 0xFFFFFFFF Invalid PCI address.\r |
956 | @retval other The read value from the PCI configuration register.\r | |
84ace59f LG |
957 | \r |
958 | **/\r | |
959 | UINT32\r | |
960 | EFIAPI\r | |
961 | PciExpressRead32 (\r | |
962 | IN UINTN Address\r | |
963 | )\r | |
964 | {\r | |
5c065855 MSB |
965 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
966 | return (UINT32) -1;\r | |
967 | }\r | |
84ace59f LG |
968 | return MmioRead32 (GetPciExpressAddress (Address));\r |
969 | }\r | |
970 | \r | |
971 | /**\r | |
972 | Writes a 32-bit PCI configuration register.\r | |
973 | \r | |
974 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
975 | value specified by Value. Value is returned. This function must guarantee\r | |
976 | that all PCI read and write operations are serialized.\r | |
977 | \r | |
978 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
979 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
980 | \r | |
981 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
982 | Register.\r | |
983 | @param Value The value to write.\r | |
984 | \r | |
5c065855 MSB |
985 | @retval 0xFFFFFFFF Invalid PCI address.\r |
986 | @retval other The value written to the PCI configuration register.\r | |
84ace59f LG |
987 | \r |
988 | **/\r | |
989 | UINT32\r | |
990 | EFIAPI\r | |
991 | PciExpressWrite32 (\r | |
992 | IN UINTN Address,\r | |
993 | IN UINT32 Value\r | |
994 | )\r | |
995 | {\r | |
5c065855 MSB |
996 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
997 | return (UINT32) -1;\r | |
998 | }\r | |
84ace59f LG |
999 | return MmioWrite32 (GetPciExpressAddress (Address), Value);\r |
1000 | }\r | |
1001 | \r | |
1002 | /**\r | |
1003 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
1004 | a 32-bit value.\r | |
1005 | \r | |
1006 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1007 | bitwise OR between the read result and the value specified by\r | |
1008 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1009 | specified by Address. The value written to the PCI configuration register is\r | |
1010 | returned. This function must guarantee that all PCI read and write operations\r | |
1011 | are serialized.\r | |
1012 | \r | |
1013 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1014 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1015 | \r | |
1016 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
1017 | Register.\r | |
1018 | @param OrData The value to OR with the PCI configuration register.\r | |
1019 | \r | |
5c065855 MSB |
1020 | @retval 0xFFFFFFFF Invalid PCI address.\r |
1021 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
1022 | \r |
1023 | **/\r | |
1024 | UINT32\r | |
1025 | EFIAPI\r | |
1026 | PciExpressOr32 (\r | |
1027 | IN UINTN Address,\r | |
1028 | IN UINT32 OrData\r | |
1029 | )\r | |
1030 | {\r | |
5c065855 MSB |
1031 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
1032 | return (UINT32) -1;\r | |
1033 | }\r | |
84ace59f LG |
1034 | return MmioOr32 (GetPciExpressAddress (Address), OrData);\r |
1035 | }\r | |
1036 | \r | |
1037 | /**\r | |
1038 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
1039 | value.\r | |
1040 | \r | |
1041 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1042 | bitwise AND between the read result and the value specified by AndData, and\r | |
1043 | writes the result to the 32-bit PCI configuration register specified by\r | |
1044 | Address. The value written to the PCI configuration register is returned.\r | |
1045 | This function must guarantee that all PCI read and write operations are\r | |
1046 | serialized.\r | |
1047 | \r | |
1048 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1049 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1050 | \r | |
1051 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
1052 | Register.\r | |
1053 | @param AndData The value to AND with the PCI configuration register.\r | |
1054 | \r | |
5c065855 MSB |
1055 | @retval 0xFFFFFFFF Invalid PCI address.\r |
1056 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
1057 | \r |
1058 | **/\r | |
1059 | UINT32\r | |
1060 | EFIAPI\r | |
1061 | PciExpressAnd32 (\r | |
1062 | IN UINTN Address,\r | |
1063 | IN UINT32 AndData\r | |
1064 | )\r | |
1065 | {\r | |
5c065855 MSB |
1066 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
1067 | return (UINT32) -1;\r | |
1068 | }\r | |
84ace59f LG |
1069 | return MmioAnd32 (GetPciExpressAddress (Address), AndData);\r |
1070 | }\r | |
1071 | \r | |
1072 | /**\r | |
1073 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
1074 | value, followed a bitwise OR with another 32-bit value.\r | |
1075 | \r | |
1076 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1077 | bitwise AND between the read result and the value specified by AndData,\r | |
1078 | performs a bitwise OR between the result of the AND operation and\r | |
1079 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
1080 | configuration register specified by Address. The value written to the PCI\r | |
1081 | configuration register is returned. This function must guarantee that all PCI\r | |
1082 | read and write operations are serialized.\r | |
1083 | \r | |
1084 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1085 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1086 | \r | |
1087 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
1088 | Register.\r | |
1089 | @param AndData The value to AND with the PCI configuration register.\r | |
1090 | @param OrData The value to OR with the result of the AND operation.\r | |
1091 | \r | |
5c065855 MSB |
1092 | @retval 0xFFFFFFFF Invalid PCI address.\r |
1093 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
1094 | \r |
1095 | **/\r | |
1096 | UINT32\r | |
1097 | EFIAPI\r | |
1098 | PciExpressAndThenOr32 (\r | |
1099 | IN UINTN Address,\r | |
1100 | IN UINT32 AndData,\r | |
1101 | IN UINT32 OrData\r | |
1102 | )\r | |
1103 | {\r | |
5c065855 MSB |
1104 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
1105 | return (UINT32) -1;\r | |
1106 | }\r | |
84ace59f LG |
1107 | return MmioAndThenOr32 (\r |
1108 | GetPciExpressAddress (Address),\r | |
1109 | AndData,\r | |
1110 | OrData\r | |
1111 | );\r | |
1112 | }\r | |
1113 | \r | |
1114 | /**\r | |
1115 | Reads a bit field of a PCI configuration register.\r | |
1116 | \r | |
1117 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1118 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1119 | returned.\r | |
1120 | \r | |
1121 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1122 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1123 | If StartBit is greater than 31, then ASSERT().\r | |
1124 | If EndBit is greater than 31, then ASSERT().\r | |
1125 | If EndBit is less than StartBit, then ASSERT().\r | |
1126 | \r | |
1127 | @param Address The PCI configuration register to read.\r | |
1128 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1129 | Range 0..31.\r | |
1130 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1131 | Range 0..31.\r | |
1132 | \r | |
5c065855 MSB |
1133 | @retval 0xFFFFFFFF Invalid PCI address.\r |
1134 | @retval other The value of the bit field read from the PCI configuration register.\r | |
84ace59f LG |
1135 | \r |
1136 | **/\r | |
1137 | UINT32\r | |
1138 | EFIAPI\r | |
1139 | PciExpressBitFieldRead32 (\r | |
1140 | IN UINTN Address,\r | |
1141 | IN UINTN StartBit,\r | |
1142 | IN UINTN EndBit\r | |
1143 | )\r | |
1144 | {\r | |
5c065855 MSB |
1145 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
1146 | return (UINT32) -1;\r | |
1147 | }\r | |
84ace59f LG |
1148 | return MmioBitFieldRead32 (\r |
1149 | GetPciExpressAddress (Address),\r | |
1150 | StartBit,\r | |
1151 | EndBit\r | |
1152 | );\r | |
1153 | }\r | |
1154 | \r | |
1155 | /**\r | |
1156 | Writes a bit field to a PCI configuration register.\r | |
1157 | \r | |
1158 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1159 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1160 | destination PCI configuration register are preserved. The new value of the\r | |
1161 | 32-bit register is returned.\r | |
1162 | \r | |
1163 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1164 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1165 | If StartBit is greater than 31, then ASSERT().\r | |
1166 | If EndBit is greater than 31, then ASSERT().\r | |
1167 | If EndBit is less than StartBit, then ASSERT().\r | |
1168 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1169 | \r | |
1170 | @param Address The PCI configuration register to write.\r | |
1171 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1172 | Range 0..31.\r | |
1173 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1174 | Range 0..31.\r | |
1175 | @param Value The new value of the bit field.\r | |
1176 | \r | |
5c065855 MSB |
1177 | @retval 0xFFFFFFFF Invalid PCI address.\r |
1178 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
1179 | \r |
1180 | **/\r | |
1181 | UINT32\r | |
1182 | EFIAPI\r | |
1183 | PciExpressBitFieldWrite32 (\r | |
1184 | IN UINTN Address,\r | |
1185 | IN UINTN StartBit,\r | |
1186 | IN UINTN EndBit,\r | |
1187 | IN UINT32 Value\r | |
1188 | )\r | |
1189 | {\r | |
5c065855 MSB |
1190 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
1191 | return (UINT32) -1;\r | |
1192 | }\r | |
84ace59f LG |
1193 | return MmioBitFieldWrite32 (\r |
1194 | GetPciExpressAddress (Address),\r | |
1195 | StartBit,\r | |
1196 | EndBit,\r | |
1197 | Value\r | |
1198 | );\r | |
1199 | }\r | |
1200 | \r | |
1201 | /**\r | |
1202 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1203 | writes the result back to the bit field in the 32-bit port.\r | |
1204 | \r | |
1205 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1206 | bitwise OR between the read result and the value specified by\r | |
1207 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1208 | specified by Address. The value written to the PCI configuration register is\r | |
1209 | returned. This function must guarantee that all PCI read and write operations\r | |
1210 | are serialized. Extra left bits in OrData are stripped.\r | |
1211 | \r | |
1212 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1213 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1214 | If StartBit is greater than 31, then ASSERT().\r | |
1215 | If EndBit is greater than 31, then ASSERT().\r | |
1216 | If EndBit is less than StartBit, then ASSERT().\r | |
1217 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1218 | \r | |
1219 | @param Address The PCI configuration register to write.\r | |
1220 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1221 | Range 0..31.\r | |
1222 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1223 | Range 0..31.\r | |
1224 | @param OrData The value to OR with the PCI configuration register.\r | |
1225 | \r | |
5c065855 MSB |
1226 | @retval 0xFFFFFFFF Invalid PCI address.\r |
1227 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
1228 | \r |
1229 | **/\r | |
1230 | UINT32\r | |
1231 | EFIAPI\r | |
1232 | PciExpressBitFieldOr32 (\r | |
1233 | IN UINTN Address,\r | |
1234 | IN UINTN StartBit,\r | |
1235 | IN UINTN EndBit,\r | |
1236 | IN UINT32 OrData\r | |
1237 | )\r | |
1238 | {\r | |
5c065855 MSB |
1239 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
1240 | return (UINT32) -1;\r | |
1241 | }\r | |
84ace59f LG |
1242 | return MmioBitFieldOr32 (\r |
1243 | GetPciExpressAddress (Address),\r | |
1244 | StartBit,\r | |
1245 | EndBit,\r | |
1246 | OrData\r | |
1247 | );\r | |
1248 | }\r | |
1249 | \r | |
1250 | /**\r | |
1251 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1252 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1253 | \r | |
1254 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1255 | bitwise AND between the read result and the value specified by AndData, and\r | |
1256 | writes the result to the 32-bit PCI configuration register specified by\r | |
1257 | Address. The value written to the PCI configuration register is returned.\r | |
1258 | This function must guarantee that all PCI read and write operations are\r | |
1259 | serialized. Extra left bits in AndData are stripped.\r | |
1260 | \r | |
1261 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1262 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1263 | If StartBit is greater than 31, then ASSERT().\r | |
1264 | If EndBit is greater than 31, then ASSERT().\r | |
1265 | If EndBit is less than StartBit, then ASSERT().\r | |
1266 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1267 | \r | |
1268 | @param Address The PCI configuration register to write.\r | |
1269 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1270 | Range 0..31.\r | |
1271 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1272 | Range 0..31.\r | |
1273 | @param AndData The value to AND with the PCI configuration register.\r | |
1274 | \r | |
5c065855 MSB |
1275 | @retval 0xFFFFFFFF Invalid PCI address.\r |
1276 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
1277 | \r |
1278 | **/\r | |
1279 | UINT32\r | |
1280 | EFIAPI\r | |
1281 | PciExpressBitFieldAnd32 (\r | |
1282 | IN UINTN Address,\r | |
1283 | IN UINTN StartBit,\r | |
1284 | IN UINTN EndBit,\r | |
1285 | IN UINT32 AndData\r | |
1286 | )\r | |
1287 | {\r | |
5c065855 MSB |
1288 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
1289 | return (UINT32) -1;\r | |
1290 | }\r | |
84ace59f LG |
1291 | return MmioBitFieldAnd32 (\r |
1292 | GetPciExpressAddress (Address),\r | |
1293 | StartBit,\r | |
1294 | EndBit,\r | |
1295 | AndData\r | |
1296 | );\r | |
1297 | }\r | |
1298 | \r | |
1299 | /**\r | |
1300 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1301 | bitwise OR, and writes the result back to the bit field in the\r | |
1302 | 32-bit port.\r | |
1303 | \r | |
1304 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1305 | bitwise AND followed by a bitwise OR between the read result and\r | |
1306 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1307 | configuration register specified by Address. The value written to the PCI\r | |
1308 | configuration register is returned. This function must guarantee that all PCI\r | |
1309 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1310 | OrData are stripped.\r | |
1311 | \r | |
1312 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1313 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1314 | If StartBit is greater than 31, then ASSERT().\r | |
1315 | If EndBit is greater than 31, then ASSERT().\r | |
1316 | If EndBit is less than StartBit, then ASSERT().\r | |
1317 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1318 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1319 | \r | |
1320 | @param Address The PCI configuration register to write.\r | |
1321 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1322 | Range 0..31.\r | |
1323 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1324 | Range 0..31.\r | |
1325 | @param AndData The value to AND with the PCI configuration register.\r | |
1326 | @param OrData The value to OR with the result of the AND operation.\r | |
1327 | \r | |
5c065855 MSB |
1328 | @retval 0xFFFFFFFF Invalid PCI address.\r |
1329 | @retval other The value written back to the PCI configuration register.\r | |
84ace59f LG |
1330 | \r |
1331 | **/\r | |
1332 | UINT32\r | |
1333 | EFIAPI\r | |
1334 | PciExpressBitFieldAndThenOr32 (\r | |
1335 | IN UINTN Address,\r | |
1336 | IN UINTN StartBit,\r | |
1337 | IN UINTN EndBit,\r | |
1338 | IN UINT32 AndData,\r | |
1339 | IN UINT32 OrData\r | |
1340 | )\r | |
1341 | {\r | |
5c065855 MSB |
1342 | if (Address >= mSmmPciExpressLibPciExpressBaseSize) {\r |
1343 | return (UINT32) -1;\r | |
1344 | }\r | |
84ace59f LG |
1345 | return MmioBitFieldAndThenOr32 (\r |
1346 | GetPciExpressAddress (Address),\r | |
1347 | StartBit,\r | |
1348 | EndBit,\r | |
1349 | AndData,\r | |
1350 | OrData\r | |
1351 | );\r | |
1352 | }\r | |
1353 | \r | |
1354 | /**\r | |
1355 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1356 | \r | |
1357 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1358 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1359 | configuration registers from a single PCI function to be read. Size is\r | |
1360 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
fae43d06 | 1361 | from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
84ace59f LG |
1362 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
1363 | end of the range.\r | |
1364 | \r | |
1365 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1366 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1367 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1368 | \r | |
1369 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
1370 | Function and Register.\r | |
1371 | @param Size The size in bytes of the transfer.\r | |
1372 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1373 | \r | |
5c065855 MSB |
1374 | @retval (UINTN)-1 Invalid PCI address.\r |
1375 | @retval other Size read data from StartAddress.\r | |
84ace59f LG |
1376 | \r |
1377 | **/\r | |
1378 | UINTN\r | |
1379 | EFIAPI\r | |
1380 | PciExpressReadBuffer (\r | |
1381 | IN UINTN StartAddress,\r | |
1382 | IN UINTN Size,\r | |
1383 | OUT VOID *Buffer\r | |
1384 | )\r | |
1385 | {\r | |
1386 | UINTN ReturnValue;\r | |
1387 | \r | |
1388 | //\r | |
1389 | // Make sure Address is valid\r | |
1390 | //\r | |
1391 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1392 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1393 | \r | |
5c065855 MSB |
1394 | //\r |
1395 | // Make sure the Address is in MMCONF address space\r | |
1396 | //\r | |
1397 | if (StartAddress >= mSmmPciExpressLibPciExpressBaseSize) {\r | |
1398 | return (UINTN) -1;\r | |
1399 | }\r | |
1400 | \r | |
84ace59f LG |
1401 | if (Size == 0) {\r |
1402 | return Size;\r | |
1403 | }\r | |
1404 | \r | |
1405 | ASSERT (Buffer != NULL);\r | |
1406 | \r | |
1407 | //\r | |
1408 | // Save Size for return\r | |
1409 | //\r | |
1410 | ReturnValue = Size;\r | |
1411 | \r | |
1412 | if ((StartAddress & 1) != 0) {\r | |
1413 | //\r | |
1414 | // Read a byte if StartAddress is byte aligned\r | |
1415 | //\r | |
1416 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1417 | StartAddress += sizeof (UINT8);\r | |
1418 | Size -= sizeof (UINT8);\r | |
1419 | Buffer = (UINT8*)Buffer + 1;\r | |
1420 | }\r | |
1421 | \r | |
1422 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1423 | //\r | |
1424 | // Read a word if StartAddress is word aligned\r | |
1425 | //\r | |
1426 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r | |
1427 | \r | |
1428 | StartAddress += sizeof (UINT16);\r | |
1429 | Size -= sizeof (UINT16);\r | |
1430 | Buffer = (UINT16*)Buffer + 1;\r | |
1431 | }\r | |
1432 | \r | |
1433 | while (Size >= sizeof (UINT32)) {\r | |
1434 | //\r | |
1435 | // Read as many double words as possible\r | |
1436 | //\r | |
1437 | WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r | |
1438 | \r | |
1439 | StartAddress += sizeof (UINT32);\r | |
1440 | Size -= sizeof (UINT32);\r | |
1441 | Buffer = (UINT32*)Buffer + 1;\r | |
1442 | }\r | |
1443 | \r | |
1444 | if (Size >= sizeof (UINT16)) {\r | |
1445 | //\r | |
1446 | // Read the last remaining word if exist\r | |
1447 | //\r | |
1448 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r | |
1449 | StartAddress += sizeof (UINT16);\r | |
1450 | Size -= sizeof (UINT16);\r | |
1451 | Buffer = (UINT16*)Buffer + 1;\r | |
1452 | }\r | |
1453 | \r | |
1454 | if (Size >= sizeof (UINT8)) {\r | |
1455 | //\r | |
1456 | // Read the last remaining byte if exist\r | |
1457 | //\r | |
1458 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1459 | }\r | |
1460 | \r | |
1461 | return ReturnValue;\r | |
1462 | }\r | |
1463 | \r | |
1464 | /**\r | |
1465 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1466 | configuration space.\r | |
1467 | \r | |
1468 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1469 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1470 | configuration registers from a single PCI function to be written. Size is\r | |
1471 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
fae43d06 | 1472 | write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r |
84ace59f LG |
1473 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
1474 | and the end of the range.\r | |
1475 | \r | |
1476 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1477 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1478 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1479 | \r | |
1480 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
1481 | Function and Register.\r | |
1482 | @param Size The size in bytes of the transfer.\r | |
1483 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1484 | \r | |
5c065855 MSB |
1485 | @retval (UINTN)-1 Invalid PCI address.\r |
1486 | @retval other Size written to StartAddress.\r | |
84ace59f LG |
1487 | \r |
1488 | **/\r | |
1489 | UINTN\r | |
1490 | EFIAPI\r | |
1491 | PciExpressWriteBuffer (\r | |
1492 | IN UINTN StartAddress,\r | |
1493 | IN UINTN Size,\r | |
1494 | IN VOID *Buffer\r | |
1495 | )\r | |
1496 | {\r | |
1497 | UINTN ReturnValue;\r | |
1498 | \r | |
1499 | //\r | |
1500 | // Make sure Address is valid\r | |
1501 | //\r | |
1502 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1503 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1504 | \r | |
5c065855 MSB |
1505 | //\r |
1506 | // Make sure the Address is in MMCONF address space\r | |
1507 | //\r | |
1508 | if (StartAddress >= mSmmPciExpressLibPciExpressBaseSize) {\r | |
1509 | return (UINTN) -1;\r | |
1510 | }\r | |
1511 | \r | |
84ace59f LG |
1512 | \r |
1513 | if (Size == 0) {\r | |
1514 | return 0;\r | |
1515 | }\r | |
1516 | \r | |
1517 | ASSERT (Buffer != NULL);\r | |
1518 | \r | |
1519 | //\r | |
1520 | // Save Size for return\r | |
1521 | //\r | |
1522 | ReturnValue = Size;\r | |
1523 | \r | |
1524 | if ((StartAddress & 1) != 0) {\r | |
1525 | //\r | |
1526 | // Write a byte if StartAddress is byte aligned\r | |
1527 | //\r | |
1528 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1529 | StartAddress += sizeof (UINT8);\r | |
1530 | Size -= sizeof (UINT8);\r | |
1531 | Buffer = (UINT8*)Buffer + 1;\r | |
1532 | }\r | |
1533 | \r | |
1534 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1535 | //\r | |
1536 | // Write a word if StartAddress is word aligned\r | |
1537 | //\r | |
1538 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r | |
1539 | StartAddress += sizeof (UINT16);\r | |
1540 | Size -= sizeof (UINT16);\r | |
1541 | Buffer = (UINT16*)Buffer + 1;\r | |
1542 | }\r | |
1543 | \r | |
1544 | while (Size >= sizeof (UINT32)) {\r | |
1545 | //\r | |
1546 | // Write as many double words as possible\r | |
1547 | //\r | |
1548 | PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r | |
1549 | StartAddress += sizeof (UINT32);\r | |
1550 | Size -= sizeof (UINT32);\r | |
1551 | Buffer = (UINT32*)Buffer + 1;\r | |
1552 | }\r | |
1553 | \r | |
1554 | if (Size >= sizeof (UINT16)) {\r | |
1555 | //\r | |
1556 | // Write the last remaining word if exist\r | |
1557 | //\r | |
1558 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r | |
1559 | StartAddress += sizeof (UINT16);\r | |
1560 | Size -= sizeof (UINT16);\r | |
1561 | Buffer = (UINT16*)Buffer + 1;\r | |
1562 | }\r | |
1563 | \r | |
1564 | if (Size >= sizeof (UINT8)) {\r | |
1565 | //\r | |
1566 | // Write the last remaining byte if exist\r | |
1567 | //\r | |
1568 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1569 | }\r | |
1570 | \r | |
1571 | return ReturnValue;\r | |
1572 | }\r |