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1a3eaf06 | 1 | /** @file\r |
2 | PCI Library using PCI Root Bridge I/O Protocol.\r | |
3 | \r | |
94952554 | 4 | Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>\r |
19388d29 | 5 | This program and the accompanying materials are\r |
1a3eaf06 | 6 | licensed and made available under the terms and conditions of\r |
7 | the BSD License which accompanies this distribution. The full\r | |
8 | text of the license may be found at\r | |
2fc59a00 | 9 | http://opensource.org/licenses/bsd-license.php.\r |
1a3eaf06 | 10 | \r |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <PiDxe.h>\r | |
17 | \r | |
18 | #include <Protocol/PciRootBridgeIo.h>\r | |
19 | \r | |
20 | #include <Library/PciLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/UefiBootServicesTableLib.h>\r | |
23 | #include <Library/DebugLib.h>\r | |
24 | \r | |
25 | /**\r | |
26 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
27 | only in the low 28 bits.\r | |
28 | \r | |
29 | @param A The address to validate.\r | |
30 | @param M Additional bits to assert to be zero.\r | |
31 | \r | |
32 | **/\r | |
33 | #define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r | |
34 | ASSERT (((A) & (~0xfffffff | (M))) == 0)\r | |
35 | \r | |
36 | /**\r | |
e43e4b3e | 37 | Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.\r |
1a3eaf06 | 38 | \r |
2fc59a00 | 39 | @param A The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 40 | Register.\r |
41 | \r | |
42 | **/\r | |
e43e4b3e | 43 | #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \\r |
44 | ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r | |
1a3eaf06 | 45 | \r |
46 | //\r | |
47 | // Global varible to cache pointer to PCI Root Bridge I/O protocol.\r | |
48 | //\r | |
49 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL; \r | |
50 | \r | |
51 | /**\r | |
52 | The constructor function caches the pointer to PCI Root Bridge I/O protocol.\r | |
53 | \r | |
54 | The constructor function locates PCI Root Bridge I/O protocol from protocol database.\r | |
55 | It will ASSERT() if that operation fails and it will always return EFI_SUCCESS. \r | |
56 | \r | |
57 | @param ImageHandle The firmware allocated handle for the EFI image.\r | |
58 | @param SystemTable A pointer to the EFI System Table.\r | |
59 | \r | |
60 | @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r | |
61 | \r | |
62 | **/\r | |
63 | EFI_STATUS\r | |
64 | EFIAPI\r | |
65 | PciLibConstructor (\r | |
66 | IN EFI_HANDLE ImageHandle,\r | |
67 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
68 | )\r | |
69 | {\r | |
70 | EFI_STATUS Status;\r | |
71 | \r | |
72 | Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, (VOID**) &mPciRootBridgeIo);\r | |
73 | ASSERT_EFI_ERROR (Status);\r | |
74 | ASSERT (mPciRootBridgeIo != NULL);\r | |
75 | \r | |
76 | return EFI_SUCCESS;\r | |
77 | }\r | |
78 | \r | |
79 | /**\r | |
80 | Internal worker function to read a PCI configuration register.\r | |
81 | \r | |
82 | This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.\r | |
83 | It reads and returns the PCI configuration register specified by Address,\r | |
84 | the width of data is specified by Width.\r | |
85 | \r | |
2fc59a00 | 86 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 87 | Register.\r |
58380e9c | 88 | @param Width The width of data to read\r |
1a3eaf06 | 89 | \r |
90 | @return The value read from the PCI configuration register.\r | |
91 | \r | |
92 | **/\r | |
93 | UINT32\r | |
94 | DxePciLibPciRootBridgeIoReadWorker (\r | |
95 | IN UINTN Address,\r | |
96 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width\r | |
97 | )\r | |
98 | {\r | |
99 | UINT32 Data;\r | |
100 | \r | |
101 | mPciRootBridgeIo->Pci.Read (\r | |
102 | mPciRootBridgeIo,\r | |
103 | Width,\r | |
e43e4b3e | 104 | PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r |
1a3eaf06 | 105 | 1,\r |
106 | &Data\r | |
107 | );\r | |
108 | \r | |
109 | return Data;\r | |
110 | }\r | |
111 | \r | |
112 | /**\r | |
113 | Internal worker function to writes a PCI configuration register.\r | |
114 | \r | |
115 | This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.\r | |
116 | It writes the PCI configuration register specified by Address with the\r | |
117 | value specified by Data. The width of data is specifed by Width.\r | |
118 | Data is returned.\r | |
119 | \r | |
2fc59a00 | 120 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 121 | Register.\r |
58380e9c | 122 | @param Width The width of data to write\r |
1a3eaf06 | 123 | @param Data The value to write.\r |
124 | \r | |
125 | @return The value written to the PCI configuration register.\r | |
126 | \r | |
127 | **/\r | |
128 | UINT32\r | |
129 | DxePciLibPciRootBridgeIoWriteWorker (\r | |
130 | IN UINTN Address,\r | |
131 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
132 | IN UINT32 Data\r | |
133 | )\r | |
134 | {\r | |
135 | mPciRootBridgeIo->Pci.Write (\r | |
136 | mPciRootBridgeIo,\r | |
137 | Width,\r | |
e43e4b3e | 138 | PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r |
1a3eaf06 | 139 | 1,\r |
140 | &Data\r | |
141 | );\r | |
142 | return Data;\r | |
143 | }\r | |
144 | \r | |
3e3ae634 | 145 | /**\r |
070a76b1 | 146 | Registers a PCI device so PCI configuration registers may be accessed after \r |
3e3ae634 | 147 | SetVirtualAddressMap().\r |
148 | \r | |
070a76b1 | 149 | Registers the PCI device specified by Address so all the PCI configuration registers \r |
150 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r | |
151 | \r | |
3e3ae634 | 152 | If Address > 0x0FFFFFFF, then ASSERT().\r |
153 | \r | |
2fc59a00 | 154 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 155 | Register.\r |
156 | \r | |
157 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
158 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
159 | after ExitBootServices().\r | |
160 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
161 | at runtime could not be mapped.\r | |
162 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
163 | complete the registration.\r | |
164 | \r | |
165 | **/\r | |
166 | RETURN_STATUS\r | |
167 | EFIAPI\r | |
168 | PciRegisterForRuntimeAccess (\r | |
169 | IN UINTN Address\r | |
170 | )\r | |
171 | {\r | |
59ceeabe | 172 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
3e3ae634 | 173 | return RETURN_UNSUPPORTED;\r |
174 | }\r | |
175 | \r | |
1a3eaf06 | 176 | /**\r |
177 | Reads an 8-bit PCI configuration register.\r | |
178 | \r | |
179 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
180 | This function must guarantee that all PCI read and write operations are\r | |
181 | serialized.\r | |
182 | \r | |
183 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
184 | \r | |
2fc59a00 | 185 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 186 | Register.\r |
187 | \r | |
070a76b1 | 188 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 189 | \r |
190 | **/\r | |
191 | UINT8\r | |
192 | EFIAPI\r | |
193 | PciRead8 (\r | |
194 | IN UINTN Address\r | |
195 | )\r | |
196 | {\r | |
197 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
198 | \r | |
199 | return (UINT8) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r | |
200 | }\r | |
201 | \r | |
202 | /**\r | |
203 | Writes an 8-bit PCI configuration register.\r | |
204 | \r | |
205 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
206 | value specified by Value. Value is returned. This function must guarantee\r | |
207 | that all PCI read and write operations are serialized.\r | |
208 | \r | |
209 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
210 | \r | |
2fc59a00 | 211 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 212 | Register.\r |
070a76b1 | 213 | @param Value The value to write.\r |
1a3eaf06 | 214 | \r |
215 | @return The value written to the PCI configuration register.\r | |
216 | \r | |
217 | **/\r | |
218 | UINT8\r | |
219 | EFIAPI\r | |
220 | PciWrite8 (\r | |
221 | IN UINTN Address,\r | |
070a76b1 | 222 | IN UINT8 Value\r |
1a3eaf06 | 223 | )\r |
224 | {\r | |
225 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
226 | \r | |
070a76b1 | 227 | return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);\r |
1a3eaf06 | 228 | }\r |
229 | \r | |
230 | /**\r | |
62991af2 | 231 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
1a3eaf06 | 232 | an 8-bit value.\r |
233 | \r | |
234 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 235 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 236 | OrData, and writes the result to the 8-bit PCI configuration register\r |
237 | specified by Address. The value written to the PCI configuration register is\r | |
238 | returned. This function must guarantee that all PCI read and write operations\r | |
239 | are serialized.\r | |
240 | \r | |
241 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
242 | \r | |
2fc59a00 | 243 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 244 | Register.\r |
245 | @param OrData The value to OR with the PCI configuration register.\r | |
246 | \r | |
247 | @return The value written back to the PCI configuration register.\r | |
248 | \r | |
249 | **/\r | |
250 | UINT8\r | |
251 | EFIAPI\r | |
252 | PciOr8 (\r | |
253 | IN UINTN Address,\r | |
254 | IN UINT8 OrData\r | |
255 | )\r | |
256 | {\r | |
257 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r | |
258 | }\r | |
259 | \r | |
260 | /**\r | |
261 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
262 | value.\r | |
263 | \r | |
264 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
265 | bitwise AND between the read result and the value specified by AndData, and\r | |
266 | writes the result to the 8-bit PCI configuration register specified by\r | |
267 | Address. The value written to the PCI configuration register is returned.\r | |
268 | This function must guarantee that all PCI read and write operations are\r | |
269 | serialized.\r | |
270 | \r | |
271 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
272 | \r | |
2fc59a00 | 273 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 274 | Register.\r |
275 | @param AndData The value to AND with the PCI configuration register.\r | |
276 | \r | |
277 | @return The value written back to the PCI configuration register.\r | |
278 | \r | |
279 | **/\r | |
280 | UINT8\r | |
281 | EFIAPI\r | |
282 | PciAnd8 (\r | |
283 | IN UINTN Address,\r | |
284 | IN UINT8 AndData\r | |
285 | )\r | |
286 | {\r | |
287 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r | |
288 | }\r | |
289 | \r | |
290 | /**\r | |
291 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 292 | value, followed a bitwise OR with another 8-bit value.\r |
1a3eaf06 | 293 | \r |
294 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
295 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 296 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 297 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
298 | configuration register specified by Address. The value written to the PCI\r | |
299 | configuration register is returned. This function must guarantee that all PCI\r | |
300 | read and write operations are serialized.\r | |
301 | \r | |
302 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
303 | \r | |
2fc59a00 | 304 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 305 | Register.\r |
306 | @param AndData The value to AND with the PCI configuration register.\r | |
307 | @param OrData The value to OR with the result of the AND operation.\r | |
308 | \r | |
309 | @return The value written back to the PCI configuration register.\r | |
310 | \r | |
311 | **/\r | |
312 | UINT8\r | |
313 | EFIAPI\r | |
314 | PciAndThenOr8 (\r | |
315 | IN UINTN Address,\r | |
316 | IN UINT8 AndData,\r | |
317 | IN UINT8 OrData\r | |
318 | )\r | |
319 | {\r | |
320 | return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r | |
321 | }\r | |
322 | \r | |
323 | /**\r | |
324 | Reads a bit field of a PCI configuration register.\r | |
325 | \r | |
326 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
327 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
328 | returned.\r | |
329 | \r | |
330 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
331 | If StartBit is greater than 7, then ASSERT().\r | |
332 | If EndBit is greater than 7, then ASSERT().\r | |
333 | If EndBit is less than StartBit, then ASSERT().\r | |
334 | \r | |
2fc59a00 | 335 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 336 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
337 | Range 0..7.\r | |
338 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
339 | Range 0..7.\r | |
340 | \r | |
341 | @return The value of the bit field read from the PCI configuration register.\r | |
342 | \r | |
343 | **/\r | |
344 | UINT8\r | |
345 | EFIAPI\r | |
346 | PciBitFieldRead8 (\r | |
347 | IN UINTN Address,\r | |
348 | IN UINTN StartBit,\r | |
349 | IN UINTN EndBit\r | |
350 | )\r | |
351 | {\r | |
352 | return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r | |
353 | }\r | |
354 | \r | |
355 | /**\r | |
356 | Writes a bit field to a PCI configuration register.\r | |
357 | \r | |
358 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
359 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
360 | destination PCI configuration register are preserved. The new value of the\r | |
361 | 8-bit register is returned.\r | |
362 | \r | |
363 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
364 | If StartBit is greater than 7, then ASSERT().\r | |
365 | If EndBit is greater than 7, then ASSERT().\r | |
366 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 367 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 368 | \r |
2fc59a00 | 369 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 370 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
371 | Range 0..7.\r | |
372 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
373 | Range 0..7.\r | |
2fc59a00 | 374 | @param Value The new value of the bit field.\r |
1a3eaf06 | 375 | \r |
376 | @return The value written back to the PCI configuration register.\r | |
377 | \r | |
378 | **/\r | |
379 | UINT8\r | |
380 | EFIAPI\r | |
381 | PciBitFieldWrite8 (\r | |
382 | IN UINTN Address,\r | |
383 | IN UINTN StartBit,\r | |
384 | IN UINTN EndBit,\r | |
385 | IN UINT8 Value\r | |
386 | )\r | |
387 | {\r | |
388 | return PciWrite8 (\r | |
389 | Address,\r | |
390 | BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)\r | |
391 | );\r | |
392 | }\r | |
393 | \r | |
394 | /**\r | |
395 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
396 | writes the result back to the bit field in the 8-bit port.\r | |
397 | \r | |
398 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 399 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 400 | OrData, and writes the result to the 8-bit PCI configuration register\r |
401 | specified by Address. The value written to the PCI configuration register is\r | |
402 | returned. This function must guarantee that all PCI read and write operations\r | |
403 | are serialized. Extra left bits in OrData are stripped.\r | |
404 | \r | |
405 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
406 | If StartBit is greater than 7, then ASSERT().\r | |
407 | If EndBit is greater than 7, then ASSERT().\r | |
408 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 409 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 410 | \r |
2fc59a00 | 411 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 412 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
413 | Range 0..7.\r | |
414 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
415 | Range 0..7.\r | |
416 | @param OrData The value to OR with the PCI configuration register.\r | |
417 | \r | |
418 | @return The value written back to the PCI configuration register.\r | |
419 | \r | |
420 | **/\r | |
421 | UINT8\r | |
422 | EFIAPI\r | |
423 | PciBitFieldOr8 (\r | |
424 | IN UINTN Address,\r | |
425 | IN UINTN StartBit,\r | |
426 | IN UINTN EndBit,\r | |
427 | IN UINT8 OrData\r | |
428 | )\r | |
429 | {\r | |
430 | return PciWrite8 (\r | |
431 | Address,\r | |
432 | BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)\r | |
433 | );\r | |
434 | }\r | |
435 | \r | |
436 | /**\r | |
437 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
438 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
439 | \r | |
440 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
441 | bitwise AND between the read result and the value specified by AndData, and\r | |
442 | writes the result to the 8-bit PCI configuration register specified by\r | |
443 | Address. The value written to the PCI configuration register is returned.\r | |
444 | This function must guarantee that all PCI read and write operations are\r | |
445 | serialized. Extra left bits in AndData are stripped.\r | |
446 | \r | |
447 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
448 | If StartBit is greater than 7, then ASSERT().\r | |
449 | If EndBit is greater than 7, then ASSERT().\r | |
450 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 451 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 452 | \r |
2fc59a00 | 453 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 454 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
455 | Range 0..7.\r | |
456 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
457 | Range 0..7.\r | |
458 | @param AndData The value to AND with the PCI configuration register.\r | |
459 | \r | |
460 | @return The value written back to the PCI configuration register.\r | |
461 | \r | |
462 | **/\r | |
463 | UINT8\r | |
464 | EFIAPI\r | |
465 | PciBitFieldAnd8 (\r | |
466 | IN UINTN Address,\r | |
467 | IN UINTN StartBit,\r | |
468 | IN UINTN EndBit,\r | |
469 | IN UINT8 AndData\r | |
470 | )\r | |
471 | {\r | |
472 | return PciWrite8 (\r | |
473 | Address,\r | |
474 | BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)\r | |
475 | );\r | |
476 | }\r | |
477 | \r | |
478 | /**\r | |
479 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 480 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 481 | 8-bit port.\r |
482 | \r | |
483 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 484 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 485 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
486 | configuration register specified by Address. The value written to the PCI\r | |
487 | configuration register is returned. This function must guarantee that all PCI\r | |
488 | read and write operations are serialized. Extra left bits in both AndData and\r | |
489 | OrData are stripped.\r | |
490 | \r | |
491 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
492 | If StartBit is greater than 7, then ASSERT().\r | |
493 | If EndBit is greater than 7, then ASSERT().\r | |
494 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
495 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
496 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1a3eaf06 | 497 | \r |
2fc59a00 | 498 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 499 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
500 | Range 0..7.\r | |
501 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
502 | Range 0..7.\r | |
503 | @param AndData The value to AND with the PCI configuration register.\r | |
504 | @param OrData The value to OR with the result of the AND operation.\r | |
505 | \r | |
506 | @return The value written back to the PCI configuration register.\r | |
507 | \r | |
508 | **/\r | |
509 | UINT8\r | |
510 | EFIAPI\r | |
511 | PciBitFieldAndThenOr8 (\r | |
512 | IN UINTN Address,\r | |
513 | IN UINTN StartBit,\r | |
514 | IN UINTN EndBit,\r | |
515 | IN UINT8 AndData,\r | |
516 | IN UINT8 OrData\r | |
517 | )\r | |
518 | {\r | |
519 | return PciWrite8 (\r | |
520 | Address,\r | |
521 | BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
522 | );\r | |
523 | }\r | |
524 | \r | |
525 | /**\r | |
526 | Reads a 16-bit PCI configuration register.\r | |
527 | \r | |
528 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
529 | This function must guarantee that all PCI read and write operations are\r | |
530 | serialized.\r | |
531 | \r | |
532 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
533 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
534 | \r | |
2fc59a00 | 535 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 536 | Register.\r |
537 | \r | |
070a76b1 | 538 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 539 | \r |
540 | **/\r | |
541 | UINT16\r | |
542 | EFIAPI\r | |
543 | PciRead16 (\r | |
544 | IN UINTN Address\r | |
545 | )\r | |
546 | {\r | |
547 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
548 | \r | |
549 | return (UINT16) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r | |
550 | }\r | |
551 | \r | |
552 | /**\r | |
553 | Writes a 16-bit PCI configuration register.\r | |
554 | \r | |
555 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
556 | value specified by Value. Value is returned. This function must guarantee\r | |
557 | that all PCI read and write operations are serialized.\r | |
558 | \r | |
559 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
560 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
561 | \r | |
2fc59a00 | 562 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 563 | Register.\r |
070a76b1 | 564 | @param Value The value to write.\r |
1a3eaf06 | 565 | \r |
566 | @return The value written to the PCI configuration register.\r | |
567 | \r | |
568 | **/\r | |
569 | UINT16\r | |
570 | EFIAPI\r | |
571 | PciWrite16 (\r | |
572 | IN UINTN Address,\r | |
070a76b1 | 573 | IN UINT16 Value\r |
1a3eaf06 | 574 | )\r |
575 | {\r | |
576 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
577 | \r | |
070a76b1 | 578 | return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);\r |
1a3eaf06 | 579 | }\r |
580 | \r | |
581 | /**\r | |
62991af2 | 582 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
1a3eaf06 | 583 | a 16-bit value.\r |
584 | \r | |
585 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 586 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 587 | OrData, and writes the result to the 16-bit PCI configuration register\r |
588 | specified by Address. The value written to the PCI configuration register is\r | |
589 | returned. This function must guarantee that all PCI read and write operations\r | |
590 | are serialized.\r | |
591 | \r | |
592 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
593 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
594 | \r | |
2fc59a00 | 595 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 596 | Register.\r |
597 | @param OrData The value to OR with the PCI configuration register.\r | |
598 | \r | |
599 | @return The value written back to the PCI configuration register.\r | |
600 | \r | |
601 | **/\r | |
602 | UINT16\r | |
603 | EFIAPI\r | |
604 | PciOr16 (\r | |
605 | IN UINTN Address,\r | |
606 | IN UINT16 OrData\r | |
607 | )\r | |
608 | {\r | |
609 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r | |
610 | }\r | |
611 | \r | |
612 | /**\r | |
613 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
614 | value.\r | |
615 | \r | |
616 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
617 | bitwise AND between the read result and the value specified by AndData, and\r | |
618 | writes the result to the 16-bit PCI configuration register specified by\r | |
619 | Address. The value written to the PCI configuration register is returned.\r | |
620 | This function must guarantee that all PCI read and write operations are\r | |
621 | serialized.\r | |
622 | \r | |
623 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
624 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
625 | \r | |
2fc59a00 | 626 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 627 | Register.\r |
628 | @param AndData The value to AND with the PCI configuration register.\r | |
629 | \r | |
630 | @return The value written back to the PCI configuration register.\r | |
631 | \r | |
632 | **/\r | |
633 | UINT16\r | |
634 | EFIAPI\r | |
635 | PciAnd16 (\r | |
636 | IN UINTN Address,\r | |
637 | IN UINT16 AndData\r | |
638 | )\r | |
639 | {\r | |
640 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r | |
641 | }\r | |
642 | \r | |
643 | /**\r | |
644 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 645 | value, followed a bitwise OR with another 16-bit value.\r |
1a3eaf06 | 646 | \r |
647 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
648 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 649 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 650 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
651 | configuration register specified by Address. The value written to the PCI\r | |
652 | configuration register is returned. This function must guarantee that all PCI\r | |
653 | read and write operations are serialized.\r | |
654 | \r | |
655 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
656 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
657 | \r | |
2fc59a00 | 658 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 659 | Register.\r |
660 | @param AndData The value to AND with the PCI configuration register.\r | |
661 | @param OrData The value to OR with the result of the AND operation.\r | |
662 | \r | |
663 | @return The value written back to the PCI configuration register.\r | |
664 | \r | |
665 | **/\r | |
666 | UINT16\r | |
667 | EFIAPI\r | |
668 | PciAndThenOr16 (\r | |
669 | IN UINTN Address,\r | |
670 | IN UINT16 AndData,\r | |
671 | IN UINT16 OrData\r | |
672 | )\r | |
673 | {\r | |
674 | return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r | |
675 | }\r | |
676 | \r | |
677 | /**\r | |
678 | Reads a bit field of a PCI configuration register.\r | |
679 | \r | |
680 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
681 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
682 | returned.\r | |
683 | \r | |
684 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
685 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
686 | If StartBit is greater than 15, then ASSERT().\r | |
687 | If EndBit is greater than 15, then ASSERT().\r | |
688 | If EndBit is less than StartBit, then ASSERT().\r | |
689 | \r | |
2fc59a00 | 690 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 691 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
692 | Range 0..15.\r | |
693 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
694 | Range 0..15.\r | |
695 | \r | |
696 | @return The value of the bit field read from the PCI configuration register.\r | |
697 | \r | |
698 | **/\r | |
699 | UINT16\r | |
700 | EFIAPI\r | |
701 | PciBitFieldRead16 (\r | |
702 | IN UINTN Address,\r | |
703 | IN UINTN StartBit,\r | |
704 | IN UINTN EndBit\r | |
705 | )\r | |
706 | {\r | |
707 | return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r | |
708 | }\r | |
709 | \r | |
710 | /**\r | |
711 | Writes a bit field to a PCI configuration register.\r | |
712 | \r | |
713 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
714 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
715 | destination PCI configuration register are preserved. The new value of the\r | |
716 | 16-bit register is returned.\r | |
717 | \r | |
718 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
719 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
720 | If StartBit is greater than 15, then ASSERT().\r | |
721 | If EndBit is greater than 15, then ASSERT().\r | |
722 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 723 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 724 | \r |
2fc59a00 | 725 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 726 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
727 | Range 0..15.\r | |
728 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
729 | Range 0..15.\r | |
2fc59a00 | 730 | @param Value The new value of the bit field.\r |
1a3eaf06 | 731 | \r |
732 | @return The value written back to the PCI configuration register.\r | |
733 | \r | |
734 | **/\r | |
735 | UINT16\r | |
736 | EFIAPI\r | |
737 | PciBitFieldWrite16 (\r | |
738 | IN UINTN Address,\r | |
739 | IN UINTN StartBit,\r | |
740 | IN UINTN EndBit,\r | |
741 | IN UINT16 Value\r | |
742 | )\r | |
743 | {\r | |
744 | return PciWrite16 (\r | |
745 | Address,\r | |
746 | BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)\r | |
747 | );\r | |
748 | }\r | |
749 | \r | |
750 | /**\r | |
751 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
752 | writes the result back to the bit field in the 16-bit port.\r | |
753 | \r | |
754 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 755 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 756 | OrData, and writes the result to the 16-bit PCI configuration register\r |
757 | specified by Address. The value written to the PCI configuration register is\r | |
758 | returned. This function must guarantee that all PCI read and write operations\r | |
759 | are serialized. Extra left bits in OrData are stripped.\r | |
760 | \r | |
761 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
762 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
763 | If StartBit is greater than 15, then ASSERT().\r | |
764 | If EndBit is greater than 15, then ASSERT().\r | |
765 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 766 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 767 | \r |
2fc59a00 | 768 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 769 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
770 | Range 0..15.\r | |
771 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
772 | Range 0..15.\r | |
773 | @param OrData The value to OR with the PCI configuration register.\r | |
774 | \r | |
775 | @return The value written back to the PCI configuration register.\r | |
776 | \r | |
777 | **/\r | |
778 | UINT16\r | |
779 | EFIAPI\r | |
780 | PciBitFieldOr16 (\r | |
781 | IN UINTN Address,\r | |
782 | IN UINTN StartBit,\r | |
783 | IN UINTN EndBit,\r | |
784 | IN UINT16 OrData\r | |
785 | )\r | |
786 | {\r | |
787 | return PciWrite16 (\r | |
788 | Address,\r | |
789 | BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)\r | |
790 | );\r | |
791 | }\r | |
792 | \r | |
793 | /**\r | |
794 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
795 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
796 | \r | |
797 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
798 | bitwise AND between the read result and the value specified by AndData, and\r | |
799 | writes the result to the 16-bit PCI configuration register specified by\r | |
800 | Address. The value written to the PCI configuration register is returned.\r | |
801 | This function must guarantee that all PCI read and write operations are\r | |
802 | serialized. Extra left bits in AndData are stripped.\r | |
803 | \r | |
804 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
805 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
806 | If StartBit is greater than 15, then ASSERT().\r | |
807 | If EndBit is greater than 15, then ASSERT().\r | |
808 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 809 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 810 | \r |
2fc59a00 | 811 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 812 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
813 | Range 0..15.\r | |
814 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
815 | Range 0..15.\r | |
816 | @param AndData The value to AND with the PCI configuration register.\r | |
817 | \r | |
818 | @return The value written back to the PCI configuration register.\r | |
819 | \r | |
820 | **/\r | |
821 | UINT16\r | |
822 | EFIAPI\r | |
823 | PciBitFieldAnd16 (\r | |
824 | IN UINTN Address,\r | |
825 | IN UINTN StartBit,\r | |
826 | IN UINTN EndBit,\r | |
827 | IN UINT16 AndData\r | |
828 | )\r | |
829 | {\r | |
830 | return PciWrite16 (\r | |
831 | Address,\r | |
832 | BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)\r | |
833 | );\r | |
834 | }\r | |
835 | \r | |
836 | /**\r | |
837 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 838 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 839 | 16-bit port.\r |
840 | \r | |
841 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 842 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 843 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
844 | configuration register specified by Address. The value written to the PCI\r | |
845 | configuration register is returned. This function must guarantee that all PCI\r | |
846 | read and write operations are serialized. Extra left bits in both AndData and\r | |
847 | OrData are stripped.\r | |
848 | \r | |
849 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
850 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
851 | If StartBit is greater than 15, then ASSERT().\r | |
852 | If EndBit is greater than 15, then ASSERT().\r | |
853 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
854 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
855 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1a3eaf06 | 856 | \r |
2fc59a00 | 857 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 858 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
859 | Range 0..15.\r | |
860 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
861 | Range 0..15.\r | |
862 | @param AndData The value to AND with the PCI configuration register.\r | |
863 | @param OrData The value to OR with the result of the AND operation.\r | |
864 | \r | |
865 | @return The value written back to the PCI configuration register.\r | |
866 | \r | |
867 | **/\r | |
868 | UINT16\r | |
869 | EFIAPI\r | |
870 | PciBitFieldAndThenOr16 (\r | |
871 | IN UINTN Address,\r | |
872 | IN UINTN StartBit,\r | |
873 | IN UINTN EndBit,\r | |
874 | IN UINT16 AndData,\r | |
875 | IN UINT16 OrData\r | |
876 | )\r | |
877 | {\r | |
878 | return PciWrite16 (\r | |
879 | Address,\r | |
880 | BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
881 | );\r | |
882 | }\r | |
883 | \r | |
884 | /**\r | |
885 | Reads a 32-bit PCI configuration register.\r | |
886 | \r | |
887 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
888 | This function must guarantee that all PCI read and write operations are\r | |
889 | serialized.\r | |
890 | \r | |
891 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
892 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
893 | \r | |
2fc59a00 | 894 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 895 | Register.\r |
896 | \r | |
070a76b1 | 897 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 898 | \r |
899 | **/\r | |
900 | UINT32\r | |
901 | EFIAPI\r | |
902 | PciRead32 (\r | |
903 | IN UINTN Address\r | |
904 | )\r | |
905 | {\r | |
906 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
907 | \r | |
908 | return DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint32);\r | |
909 | }\r | |
910 | \r | |
911 | /**\r | |
912 | Writes a 32-bit PCI configuration register.\r | |
913 | \r | |
914 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
915 | value specified by Value. Value is returned. This function must guarantee\r | |
916 | that all PCI read and write operations are serialized.\r | |
917 | \r | |
918 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
919 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
920 | \r | |
2fc59a00 | 921 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 922 | Register.\r |
070a76b1 | 923 | @param Value The value to write.\r |
1a3eaf06 | 924 | \r |
925 | @return The value written to the PCI configuration register.\r | |
926 | \r | |
927 | **/\r | |
928 | UINT32\r | |
929 | EFIAPI\r | |
930 | PciWrite32 (\r | |
931 | IN UINTN Address,\r | |
070a76b1 | 932 | IN UINT32 Value\r |
1a3eaf06 | 933 | )\r |
934 | {\r | |
935 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
936 | \r | |
070a76b1 | 937 | return DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);\r |
1a3eaf06 | 938 | }\r |
939 | \r | |
940 | /**\r | |
62991af2 | 941 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
1a3eaf06 | 942 | a 32-bit value.\r |
943 | \r | |
944 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 945 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 946 | OrData, and writes the result to the 32-bit PCI configuration register\r |
947 | specified by Address. The value written to the PCI configuration register is\r | |
948 | returned. This function must guarantee that all PCI read and write operations\r | |
949 | are serialized.\r | |
950 | \r | |
951 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
952 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
953 | \r | |
2fc59a00 | 954 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 955 | Register.\r |
956 | @param OrData The value to OR with the PCI configuration register.\r | |
957 | \r | |
958 | @return The value written back to the PCI configuration register.\r | |
959 | \r | |
960 | **/\r | |
961 | UINT32\r | |
962 | EFIAPI\r | |
963 | PciOr32 (\r | |
964 | IN UINTN Address,\r | |
965 | IN UINT32 OrData\r | |
966 | )\r | |
967 | {\r | |
968 | return PciWrite32 (Address, PciRead32 (Address) | OrData);\r | |
969 | }\r | |
970 | \r | |
971 | /**\r | |
972 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
973 | value.\r | |
974 | \r | |
975 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
976 | bitwise AND between the read result and the value specified by AndData, and\r | |
977 | writes the result to the 32-bit PCI configuration register specified by\r | |
978 | Address. The value written to the PCI configuration register is returned.\r | |
979 | This function must guarantee that all PCI read and write operations are\r | |
980 | serialized.\r | |
981 | \r | |
982 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
983 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
984 | \r | |
2fc59a00 | 985 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 986 | Register.\r |
987 | @param AndData The value to AND with the PCI configuration register.\r | |
988 | \r | |
989 | @return The value written back to the PCI configuration register.\r | |
990 | \r | |
991 | **/\r | |
992 | UINT32\r | |
993 | EFIAPI\r | |
994 | PciAnd32 (\r | |
995 | IN UINTN Address,\r | |
996 | IN UINT32 AndData\r | |
997 | )\r | |
998 | {\r | |
999 | return PciWrite32 (Address, PciRead32 (Address) & AndData);\r | |
1000 | }\r | |
1001 | \r | |
1002 | /**\r | |
1003 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 1004 | value, followed a bitwise OR with another 32-bit value.\r |
1a3eaf06 | 1005 | \r |
1006 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1007 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 1008 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 1009 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
1010 | configuration register specified by Address. The value written to the PCI\r | |
1011 | configuration register is returned. This function must guarantee that all PCI\r | |
1012 | read and write operations are serialized.\r | |
1013 | \r | |
1014 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1015 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1016 | \r | |
2fc59a00 | 1017 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 1018 | Register.\r |
1019 | @param AndData The value to AND with the PCI configuration register.\r | |
1020 | @param OrData The value to OR with the result of the AND operation.\r | |
1021 | \r | |
1022 | @return The value written back to the PCI configuration register.\r | |
1023 | \r | |
1024 | **/\r | |
1025 | UINT32\r | |
1026 | EFIAPI\r | |
1027 | PciAndThenOr32 (\r | |
1028 | IN UINTN Address,\r | |
1029 | IN UINT32 AndData,\r | |
1030 | IN UINT32 OrData\r | |
1031 | )\r | |
1032 | {\r | |
1033 | return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r | |
1034 | }\r | |
1035 | \r | |
1036 | /**\r | |
1037 | Reads a bit field of a PCI configuration register.\r | |
1038 | \r | |
1039 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1040 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1041 | returned.\r | |
1042 | \r | |
1043 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1044 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1045 | If StartBit is greater than 31, then ASSERT().\r | |
1046 | If EndBit is greater than 31, then ASSERT().\r | |
1047 | If EndBit is less than StartBit, then ASSERT().\r | |
1048 | \r | |
2fc59a00 | 1049 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 1050 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1051 | Range 0..31.\r | |
1052 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1053 | Range 0..31.\r | |
1054 | \r | |
1055 | @return The value of the bit field read from the PCI configuration register.\r | |
1056 | \r | |
1057 | **/\r | |
1058 | UINT32\r | |
1059 | EFIAPI\r | |
1060 | PciBitFieldRead32 (\r | |
1061 | IN UINTN Address,\r | |
1062 | IN UINTN StartBit,\r | |
1063 | IN UINTN EndBit\r | |
1064 | )\r | |
1065 | {\r | |
1066 | return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r | |
1067 | }\r | |
1068 | \r | |
1069 | /**\r | |
1070 | Writes a bit field to a PCI configuration register.\r | |
1071 | \r | |
1072 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1073 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1074 | destination PCI configuration register are preserved. The new value of the\r | |
1075 | 32-bit register is returned.\r | |
1076 | \r | |
1077 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1078 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1079 | If StartBit is greater than 31, then ASSERT().\r | |
1080 | If EndBit is greater than 31, then ASSERT().\r | |
1081 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1082 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 1083 | \r |
2fc59a00 | 1084 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1085 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1086 | Range 0..31.\r | |
1087 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1088 | Range 0..31.\r | |
2fc59a00 | 1089 | @param Value The new value of the bit field.\r |
1a3eaf06 | 1090 | \r |
1091 | @return The value written back to the PCI configuration register.\r | |
1092 | \r | |
1093 | **/\r | |
1094 | UINT32\r | |
1095 | EFIAPI\r | |
1096 | PciBitFieldWrite32 (\r | |
1097 | IN UINTN Address,\r | |
1098 | IN UINTN StartBit,\r | |
1099 | IN UINTN EndBit,\r | |
1100 | IN UINT32 Value\r | |
1101 | )\r | |
1102 | {\r | |
1103 | return PciWrite32 (\r | |
1104 | Address,\r | |
1105 | BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)\r | |
1106 | );\r | |
1107 | }\r | |
1108 | \r | |
1109 | /**\r | |
1110 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1111 | writes the result back to the bit field in the 32-bit port.\r | |
1112 | \r | |
1113 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1114 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 1115 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1116 | specified by Address. The value written to the PCI configuration register is\r | |
1117 | returned. This function must guarantee that all PCI read and write operations\r | |
1118 | are serialized. Extra left bits in OrData are stripped.\r | |
1119 | \r | |
1120 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1121 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1122 | If StartBit is greater than 31, then ASSERT().\r | |
1123 | If EndBit is greater than 31, then ASSERT().\r | |
1124 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1125 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 1126 | \r |
2fc59a00 | 1127 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1128 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1129 | Range 0..31.\r | |
1130 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1131 | Range 0..31.\r | |
1132 | @param OrData The value to OR with the PCI configuration register.\r | |
1133 | \r | |
1134 | @return The value written back to the PCI configuration register.\r | |
1135 | \r | |
1136 | **/\r | |
1137 | UINT32\r | |
1138 | EFIAPI\r | |
1139 | PciBitFieldOr32 (\r | |
1140 | IN UINTN Address,\r | |
1141 | IN UINTN StartBit,\r | |
1142 | IN UINTN EndBit,\r | |
1143 | IN UINT32 OrData\r | |
1144 | )\r | |
1145 | {\r | |
1146 | return PciWrite32 (\r | |
1147 | Address,\r | |
1148 | BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)\r | |
1149 | );\r | |
1150 | }\r | |
1151 | \r | |
1152 | /**\r | |
1153 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1154 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1155 | \r | |
1156 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1157 | bitwise AND between the read result and the value specified by AndData, and\r | |
1158 | writes the result to the 32-bit PCI configuration register specified by\r | |
1159 | Address. The value written to the PCI configuration register is returned.\r | |
1160 | This function must guarantee that all PCI read and write operations are\r | |
1161 | serialized. Extra left bits in AndData are stripped.\r | |
1162 | \r | |
1163 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1164 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1165 | If StartBit is greater than 31, then ASSERT().\r | |
1166 | If EndBit is greater than 31, then ASSERT().\r | |
1167 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1168 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 1169 | \r |
2fc59a00 | 1170 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1171 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1172 | Range 0..31.\r | |
1173 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1174 | Range 0..31.\r | |
1175 | @param AndData The value to AND with the PCI configuration register.\r | |
1176 | \r | |
1177 | @return The value written back to the PCI configuration register.\r | |
1178 | \r | |
1179 | **/\r | |
1180 | UINT32\r | |
1181 | EFIAPI\r | |
1182 | PciBitFieldAnd32 (\r | |
1183 | IN UINTN Address,\r | |
1184 | IN UINTN StartBit,\r | |
1185 | IN UINTN EndBit,\r | |
1186 | IN UINT32 AndData\r | |
1187 | )\r | |
1188 | {\r | |
1189 | return PciWrite32 (\r | |
1190 | Address,\r | |
1191 | BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)\r | |
1192 | );\r | |
1193 | }\r | |
1194 | \r | |
1195 | /**\r | |
1196 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1197 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 1198 | 32-bit port.\r |
1199 | \r | |
1200 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1201 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 1202 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1203 | configuration register specified by Address. The value written to the PCI\r | |
1204 | configuration register is returned. This function must guarantee that all PCI\r | |
1205 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1206 | OrData are stripped.\r | |
1207 | \r | |
1208 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1209 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1210 | If StartBit is greater than 31, then ASSERT().\r | |
1211 | If EndBit is greater than 31, then ASSERT().\r | |
1212 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1213 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1214 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1a3eaf06 | 1215 | \r |
2fc59a00 | 1216 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1217 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1218 | Range 0..31.\r | |
1219 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1220 | Range 0..31.\r | |
1221 | @param AndData The value to AND with the PCI configuration register.\r | |
1222 | @param OrData The value to OR with the result of the AND operation.\r | |
1223 | \r | |
1224 | @return The value written back to the PCI configuration register.\r | |
1225 | \r | |
1226 | **/\r | |
1227 | UINT32\r | |
1228 | EFIAPI\r | |
1229 | PciBitFieldAndThenOr32 (\r | |
1230 | IN UINTN Address,\r | |
1231 | IN UINTN StartBit,\r | |
1232 | IN UINTN EndBit,\r | |
1233 | IN UINT32 AndData,\r | |
1234 | IN UINT32 OrData\r | |
1235 | )\r | |
1236 | {\r | |
1237 | return PciWrite32 (\r | |
1238 | Address,\r | |
1239 | BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1240 | );\r | |
1241 | }\r | |
1242 | \r | |
1243 | /**\r | |
1244 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1245 | \r | |
1246 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1247 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1248 | configuration registers from a single PCI function to be read. Size is\r | |
1249 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1250 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1251 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1252 | end of the range.\r | |
1253 | \r | |
1254 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1255 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1256 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1257 | \r | |
2fc59a00 | 1258 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
1a3eaf06 | 1259 | Function and Register.\r |
2fc59a00 | 1260 | @param Size The size in bytes of the transfer.\r |
1261 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1a3eaf06 | 1262 | \r |
1263 | @return Size\r | |
1264 | \r | |
1265 | **/\r | |
1266 | UINTN\r | |
1267 | EFIAPI\r | |
1268 | PciReadBuffer (\r | |
1269 | IN UINTN StartAddress,\r | |
1270 | IN UINTN Size,\r | |
1271 | OUT VOID *Buffer\r | |
1272 | )\r | |
1273 | {\r | |
1274 | UINTN ReturnValue;\r | |
1275 | \r | |
1276 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1277 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1278 | \r |
1279 | if (Size == 0) {\r | |
1280 | return Size;\r | |
1281 | }\r | |
1282 | \r | |
1283 | ASSERT (Buffer != NULL);\r | |
1284 | \r | |
1285 | //\r | |
1286 | // Save Size for return\r | |
1287 | //\r | |
1288 | ReturnValue = Size;\r | |
1289 | \r | |
e43e4b3e | 1290 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1291 | //\r |
1292 | // Read a byte if StartAddress is byte aligned\r | |
1293 | //\r | |
1294 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1295 | StartAddress += sizeof (UINT8);\r | |
1296 | Size -= sizeof (UINT8);\r | |
1297 | Buffer = (UINT8*)Buffer + 1;\r | |
1298 | }\r | |
1299 | \r | |
e43e4b3e | 1300 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1301 | //\r |
1302 | // Read a word if StartAddress is word aligned\r | |
1303 | //\r | |
5dc4fd78 | 1304 | WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r |
1a3eaf06 | 1305 | StartAddress += sizeof (UINT16);\r |
1306 | Size -= sizeof (UINT16);\r | |
1307 | Buffer = (UINT16*)Buffer + 1;\r | |
1308 | }\r | |
1309 | \r | |
1310 | while (Size >= sizeof (UINT32)) {\r | |
1311 | //\r | |
1312 | // Read as many double words as possible\r | |
1313 | //\r | |
5dc4fd78 | 1314 | WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r |
1a3eaf06 | 1315 | StartAddress += sizeof (UINT32);\r |
1316 | Size -= sizeof (UINT32);\r | |
1317 | Buffer = (UINT32*)Buffer + 1;\r | |
1318 | }\r | |
1319 | \r | |
1320 | if (Size >= sizeof (UINT16)) {\r | |
1321 | //\r | |
1322 | // Read the last remaining word if exist\r | |
1323 | //\r | |
5dc4fd78 | 1324 | WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r |
1a3eaf06 | 1325 | StartAddress += sizeof (UINT16);\r |
1326 | Size -= sizeof (UINT16);\r | |
1327 | Buffer = (UINT16*)Buffer + 1;\r | |
1328 | }\r | |
1329 | \r | |
1330 | if (Size >= sizeof (UINT8)) {\r | |
1331 | //\r | |
1332 | // Read the last remaining byte if exist\r | |
1333 | //\r | |
1334 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1335 | }\r | |
1336 | \r | |
1337 | return ReturnValue;\r | |
1338 | }\r | |
1339 | \r | |
1340 | /**\r | |
1341 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1342 | configuration space.\r | |
1343 | \r | |
1344 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1345 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1346 | configuration registers from a single PCI function to be written. Size is\r | |
1347 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1348 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1349 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1350 | and the end of the range.\r | |
1351 | \r | |
1352 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1353 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1354 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1355 | \r | |
2fc59a00 | 1356 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
1a3eaf06 | 1357 | Function and Register.\r |
2fc59a00 | 1358 | @param Size The size in bytes of the transfer.\r |
1359 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1a3eaf06 | 1360 | \r |
070a76b1 | 1361 | @return Size written to StartAddress.\r |
1a3eaf06 | 1362 | \r |
1363 | **/\r | |
1364 | UINTN\r | |
1365 | EFIAPI\r | |
1366 | PciWriteBuffer (\r | |
1367 | IN UINTN StartAddress,\r | |
1368 | IN UINTN Size,\r | |
1369 | IN VOID *Buffer\r | |
1370 | )\r | |
1371 | {\r | |
1372 | UINTN ReturnValue;\r | |
1373 | \r | |
1374 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1375 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1376 | \r |
1377 | if (Size == 0) {\r | |
1378 | return 0;\r | |
1379 | }\r | |
1380 | \r | |
1381 | ASSERT (Buffer != NULL);\r | |
1382 | \r | |
1383 | //\r | |
1384 | // Save Size for return\r | |
1385 | //\r | |
1386 | ReturnValue = Size;\r | |
1387 | \r | |
e43e4b3e | 1388 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1389 | //\r |
1390 | // Write a byte if StartAddress is byte aligned\r | |
1391 | //\r | |
1392 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1393 | StartAddress += sizeof (UINT8);\r | |
1394 | Size -= sizeof (UINT8);\r | |
1395 | Buffer = (UINT8*)Buffer + 1;\r | |
1396 | }\r | |
1397 | \r | |
e43e4b3e | 1398 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1399 | //\r |
1400 | // Write a word if StartAddress is word aligned\r | |
1401 | //\r | |
5dc4fd78 | 1402 | PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1403 | StartAddress += sizeof (UINT16);\r |
1404 | Size -= sizeof (UINT16);\r | |
1405 | Buffer = (UINT16*)Buffer + 1;\r | |
1406 | }\r | |
1407 | \r | |
1408 | while (Size >= sizeof (UINT32)) {\r | |
1409 | //\r | |
1410 | // Write as many double words as possible\r | |
1411 | //\r | |
5dc4fd78 | 1412 | PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r |
1a3eaf06 | 1413 | StartAddress += sizeof (UINT32);\r |
1414 | Size -= sizeof (UINT32);\r | |
1415 | Buffer = (UINT32*)Buffer + 1;\r | |
1416 | }\r | |
1417 | \r | |
1418 | if (Size >= sizeof (UINT16)) {\r | |
1419 | //\r | |
1420 | // Write the last remaining word if exist\r | |
1421 | //\r | |
5dc4fd78 | 1422 | PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1423 | StartAddress += sizeof (UINT16);\r |
1424 | Size -= sizeof (UINT16);\r | |
1425 | Buffer = (UINT16*)Buffer + 1;\r | |
1426 | }\r | |
1427 | \r | |
1428 | if (Size >= sizeof (UINT8)) {\r | |
1429 | //\r | |
1430 | // Write the last remaining byte if exist\r | |
1431 | //\r | |
1432 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1433 | }\r | |
1434 | \r | |
1435 | return ReturnValue;\r | |
1436 | }\r |