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63afc360 | 1 | /** @file\r |
2 | PAL Call Services\r | |
3 | \r | |
de4eb1da | 4 | Copyright (c) 2006 -2007, Intel Corporation All rights\r |
5 | reserved. This program and the accompanying materials are\r | |
6 | licensed and made available under the terms and conditions of\r | |
7 | the BSD License which accompanies this distribution. The full\r | |
8 | text of the license may be found at\r | |
63afc360 | 9 | http://opensource.org/licenses/bsd-license.php\r |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | Module Name: PalCallLib.h\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #ifndef __PAL_CALL_LIB_H__\r | |
19 | #define __PAL_CALL_LIB_H__\r | |
20 | \r | |
f4acdaec | 21 | #define PAL_SUCCESS 0x0\r |
22 | \r | |
de4eb1da | 23 | //\r |
24 | // CacheType of PAL_CACHE_FLUSH.\r | |
25 | //\r | |
26 | #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r | |
27 | #define PAL_CACHE_FLUSH_DATA_ALL 2\r | |
28 | #define PAL_CACHE_FLUSH_ALL 3\r | |
29 | #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r | |
30 | \r | |
31 | \r | |
32 | //\r | |
33 | // Bitmask of Opearation of PAL_CACHE_FLUSH.\r | |
34 | // \r | |
2b5f1d9f | 35 | #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0\r |
36 | #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0\r | |
37 | #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1\r | |
38 | #define PAL_CACHE_FLUSH_NO_INTERRUPT 0\r | |
de4eb1da | 39 | \r |
40 | /**\r | |
41 | \r | |
42 | PAL Procedure - PAL_CACHE_FLUSH.\r | |
43 | \r | |
44 | Flush the instruction or data caches. It is required by IPF.\r | |
45 | The PAL procedure supports the Static Registers calling\r | |
46 | convention. It could be called at virtual mode and physical\r | |
47 | mode.\r | |
48 | \r | |
49 | @param Index Index of PAL_CACHE_FLUSH within the\r | |
50 | list of PAL procedures.\r | |
51 | \r | |
52 | @param CacheType Unsigned 64-bit integer indicating\r | |
53 | which cache to flush.\r | |
54 | \r | |
55 | @param Operation Formatted bit vector indicating the\r | |
56 | operation of this call.\r | |
57 | \r | |
58 | @param ProgressIndicator Unsigned 64-bit integer specifying\r | |
59 | the starting position of the flush\r | |
60 | operation.\r | |
61 | \r | |
62 | @return R9 Unsigned 64-bit integer specifying the vector\r | |
63 | number of the pending interrupt.\r | |
64 | \r | |
65 | @return R10 Unsigned 64-bit integer specifying the\r | |
66 | starting position of the flush operation.\r | |
67 | \r | |
68 | @return R11 Unsigned 64-bit integer specifying the vector\r | |
69 | number of the pending interrupt.\r | |
70 | \r | |
71 | @return Status 2 - Call completed without error, but a PMI\r | |
72 | was taken during the execution of this\r | |
73 | procedure.\r | |
74 | \r | |
75 | @return Status 1 - Call has not completed flushing due to\r | |
76 | a pending interrupt.\r | |
77 | \r | |
78 | @return Status 0 - Call completed without error\r | |
79 | \r | |
80 | @return Status -2 - Invalid argument\r | |
81 | \r | |
82 | @return Status -3 - Call completed with error\r | |
83 | \r | |
84 | **/\r | |
85 | #define PAL_CACHE_FLUSH 1\r | |
86 | \r | |
87 | \r | |
88 | //\r | |
89 | // Attributes of PAL_CACHE_CONFIG_INFO1\r | |
90 | // \r | |
91 | #define PAL_CACHE_ATTR_WT 0\r | |
92 | #define PAL_CACHE_ATTR_WB 1\r | |
93 | \r | |
94 | //\r | |
95 | // PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
96 | // \r | |
97 | #define PAL_CACHE_STORE_TEMPORAL 0\r | |
98 | #define PAL_CACHE_STORE_NONE_TEMPORAL 3\r | |
99 | \r | |
100 | //\r | |
101 | // PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
102 | // \r | |
103 | #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r | |
104 | #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r | |
105 | \r | |
106 | //\r | |
107 | // PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
108 | // \r | |
109 | #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r | |
110 | #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r | |
111 | #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r | |
112 | \r | |
113 | //\r | |
114 | // Detail the characteristics of a given processor controlled\r | |
115 | // cache in the cache hierarchy.\r | |
116 | // \r | |
117 | typedef struct {\r | |
118 | UINT64 IsUnified : 1;\r | |
119 | UINT64 Attributes : 2;\r | |
120 | UINT64 Associativity:8;\r | |
121 | UINT64 LineSize:8;\r | |
122 | UINT64 Stride:8;\r | |
123 | UINT64 StoreLatency:8;\r | |
124 | UINT64 StoreHint:8;\r | |
125 | UINT64 LoadHint:8;\r | |
126 | } PAL_CACHE_INFO_RETURN1;\r | |
127 | \r | |
128 | //\r | |
129 | // Detail the characteristics of a given processor controlled\r | |
130 | // cache in the cache hierarchy.\r | |
131 | // \r | |
132 | typedef struct {\r | |
133 | UINT64 CacheSize:32;\r | |
134 | UINT64 AliasBoundary:8;\r | |
135 | UINT64 TagLsBits:8;\r | |
136 | UINT64 TagMsBits:8;\r | |
137 | } PAL_CACHE_INFO_RETURN2;\r | |
138 | \r | |
139 | /**\r | |
140 | \r | |
141 | PAL Procedure - PAL_CACHE_INFO.\r | |
142 | \r | |
143 | Return detailed instruction or data cache information. It is\r | |
144 | required by IPF. The PAL procedure supports the Static\r | |
145 | Registers calling convention. It could be called at virtual\r | |
146 | mode and physical mode.\r | |
147 | \r | |
148 | @param Index Index of PAL_CACHE_INFO within the list of\r | |
149 | PAL procedures.\r | |
150 | \r | |
151 | @param CacheLevel Unsigned 64-bit integer specifying the\r | |
152 | level in the cache hierarchy for which\r | |
153 | information is requested. This value must\r | |
154 | be between 0 and one less than the value\r | |
155 | returned in the cache_levels return value\r | |
156 | from PAL_CACHE_SUMMARY.\r | |
157 | \r | |
158 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
159 | for instruction cache and 2 for data or\r | |
160 | unified cache. All other values are\r | |
161 | reserved.\r | |
162 | \r | |
163 | @param Reserved Should be 0.\r | |
164 | \r | |
165 | \r | |
166 | @return R9 Detail the characteristics of a given\r | |
167 | processor controlled cache in the cache\r | |
168 | hierarchy. See PAL_CACHE_INFO_RETURN1.\r | |
169 | \r | |
170 | @return R10 Detail the characteristics of a given\r | |
171 | processor controlled cache in the cache\r | |
172 | hierarchy. See PAL_CACHE_INFO_RETURN2.\r | |
173 | \r | |
174 | @return R11 Reserved with 0.\r | |
175 | \r | |
176 | \r | |
177 | @return Status 0 - Call completed without error\r | |
178 | \r | |
179 | @return Status -2 - Invalid argument\r | |
180 | \r | |
181 | @return Status -3 - Call completed with error\r | |
182 | \r | |
183 | **/\r | |
184 | #define PAL_CACHE_INFO 2\r | |
185 | \r | |
186 | \r | |
187 | \r | |
188 | //\r | |
189 | // Level of PAL_CACHE_INIT.\r | |
190 | // \r | |
191 | #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r | |
192 | \r | |
2b5f1d9f | 193 | //\r |
194 | // CacheType \r | |
195 | //\r | |
196 | #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1\r | |
197 | #define PAL_CACHE_INIT_TYPE_DATA 0x2\r | |
198 | #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3\r | |
199 | \r | |
de4eb1da | 200 | //\r |
201 | // Restrict of PAL_CACHE_INIT.\r | |
202 | // \r | |
203 | #define PAL_CACHE_INIT_NO_RESTRICT 0\r | |
204 | #define PAL_CACHE_INIT_RESTRICTED 1\r | |
205 | \r | |
206 | /**\r | |
207 | \r | |
208 | PAL Procedure - PAL_CACHE_INIT.\r | |
209 | \r | |
210 | Initialize the instruction or data caches. It is required by\r | |
211 | IPF. The PAL procedure supports the Static Registers calling\r | |
212 | convention. It could be called at physical mode.\r | |
213 | \r | |
214 | @param Index Index of PAL_CACHE_INIT within the list of PAL\r | |
215 | procedures.\r | |
216 | \r | |
217 | @param Level Unsigned 64-bit integer containing the level of\r | |
218 | cache to initialize. If the cache level can be\r | |
219 | initialized independently, only that level will\r | |
220 | be initialized. Otherwise\r | |
221 | implementation-dependent side-effects will\r | |
222 | occur.\r | |
223 | \r | |
224 | @param CacheType Unsigned 64-bit integer with a value of 1 to\r | |
225 | initialize the instruction cache, 2 to\r | |
226 | initialize the data cache, or 3 to\r | |
227 | initialize both. All other values are\r | |
228 | reserved.\r | |
229 | \r | |
230 | @param Restrict Unsigned 64-bit integer with a value of 0 or\r | |
231 | 1. All other values are reserved. If\r | |
232 | restrict is 1 and initializing the specified\r | |
233 | level and cache_type of the cache would\r | |
234 | cause side-effects, PAL_CACHE_INIT will\r | |
235 | return -4 instead of initializing the cache.\r | |
236 | \r | |
237 | \r | |
238 | @return Status 0 - Call completed without error\r | |
239 | \r | |
240 | @return Status -2 - Invalid argument\r | |
241 | \r | |
242 | @return Status -3 - Call completed with error.\r | |
243 | \r | |
244 | @return Status -4 - Call could not initialize the specified\r | |
245 | level and cache_type of the cache without\r | |
246 | side-effects and restrict was 1. \r | |
247 | \r | |
248 | **/\r | |
249 | #define PAL_CACHE_INIT 3 \r | |
250 | \r | |
251 | \r | |
252 | //\r | |
253 | // PAL_CACHE_PROTECTION.Method.\r | |
254 | // \r | |
255 | #define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r | |
256 | #define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r | |
257 | #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r | |
258 | #define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r | |
259 | \r | |
260 | \r | |
261 | \r | |
262 | //\r | |
263 | // PAL_CACHE_PROTECTION.TagOrData.\r | |
264 | // \r | |
265 | #define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r | |
266 | #define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r | |
267 | #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r | |
268 | #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r | |
269 | \r | |
270 | //\r | |
271 | // 32-bit protection information structures.\r | |
272 | // \r | |
273 | typedef struct {\r | |
274 | UINT32 DataBits:8;\r | |
275 | UINT32 TagProtLsb:6;\r | |
276 | UINT32 TagProtMsb:6;\r | |
277 | UINT32 ProtBits:6;\r | |
278 | UINT32 Method:4;\r | |
279 | UINT32 TagOrData:2;\r | |
280 | } PAL_CACHE_PROTECTION;\r | |
281 | \r | |
282 | /**\r | |
283 | \r | |
284 | PAL Procedure - PAL_CACHE_PROT_INFO.\r | |
285 | \r | |
286 | Return instruction or data cache protection information. It is\r | |
287 | required by IPF. The PAL procedure supports the Static\r | |
288 | Registers calling convention. It could be called at physical\r | |
289 | mode and Virtual mode.\r | |
290 | \r | |
291 | @param Index Index of PAL_CACHE_PROT_INFO within the list of\r | |
292 | PAL procedures.\r | |
293 | \r | |
294 | @param CacheLevel Unsigned 64-bit integer specifying the level\r | |
295 | in the cache hierarchy for which information\r | |
296 | is requested. This value must be between 0\r | |
297 | and one less than the value returned in the\r | |
298 | cache_levels return value from\r | |
299 | PAL_CACHE_SUMMARY.\r | |
300 | \r | |
301 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
302 | for instruction cache and 2 for data or\r | |
303 | unified cache. All other values are\r | |
304 | reserved.\r | |
305 | \r | |
306 | @return R9 Detail the characteristics of a given\r | |
307 | processor controlled cache in the cache\r | |
308 | hierarchy. See PAL_CACHE_PROTECTION[0..1].\r | |
309 | \r | |
310 | @return R10 Detail the characteristics of a given\r | |
311 | processor controlled cache in the cache\r | |
312 | hierarchy. See PAL_CACHE_PROTECTION[2..3].\r | |
313 | \r | |
314 | @return R11 Detail the characteristics of a given\r | |
315 | processor controlled cache in the cache\r | |
316 | hierarchy. See PAL_CACHE_PROTECTION[4..5].\r | |
317 | \r | |
318 | \r | |
319 | @return Status 0 - Call completed without error\r | |
320 | \r | |
321 | @return Status -2 - Invalid argument\r | |
322 | \r | |
323 | @return Status -3 - Call completed with error.\r | |
324 | \r | |
325 | **/\r | |
326 | #define PAL_CACHE_PROT_INFO 38\r | |
327 | \r | |
328 | /**\r | |
329 | \r | |
330 | @param ThreadId The thread identifier of the logical\r | |
331 | processor for which information is being\r | |
332 | returned. This value will be unique on a per\r | |
333 | core basis.\r | |
334 | \r | |
335 | @param CoreId The core identifier of the logical processor\r | |
336 | for which information is being returned.\r | |
337 | This value will be unique on a per physical\r | |
338 | processor package basis.\r | |
339 | \r | |
340 | **/\r | |
341 | typedef struct {\r | |
342 | UINT64 ThreadId : 16;\r | |
343 | UINT64 Reserved1: 16;\r | |
344 | UINT64 CoreId: 16;\r | |
345 | UINT64 Reserved2: 16;\r | |
346 | } PAL_PCOC_N_CACHE_INFO1;\r | |
347 | \r | |
348 | /**\r | |
349 | \r | |
350 | @param LogicalAddress Logical address: geographical address\r | |
351 | of the logical processor for which\r | |
352 | information is being returned. This is\r | |
353 | the same value that is returned by the\r | |
354 | PAL_FIXED_ADDR procedure when it is\r | |
355 | called on the logical processor.\r | |
356 | \r | |
357 | **/\r | |
358 | typedef struct {\r | |
359 | UINT64 LogicalAddress : 16;\r | |
360 | UINT64 Reserved1: 16;\r | |
361 | UINT64 Reserved2: 32;\r | |
362 | } PAL_PCOC_N_CACHE_INFO2;\r | |
363 | \r | |
364 | /**\r | |
365 | \r | |
366 | PAL Procedure - PAL_CACHE_SHARED_INFO.\r | |
367 | \r | |
368 | Returns information on which logical processors share caches.\r | |
369 | It is optional. The PAL procedure supports the Static\r | |
370 | Registers calling convention. It could be called at physical\r | |
371 | mode and Virtual mode.\r | |
372 | \r | |
373 | @param Index Index of PAL_CACHE_SHARED_INFO within the list\r | |
374 | of PAL procedures.\r | |
375 | \r | |
376 | @param CacheLevel Unsigned 64-bit integer specifying the\r | |
377 | level in the cache hierarchy for which\r | |
378 | information is requested. This value must\r | |
379 | be between 0 and one less than the value\r | |
380 | returned in the cache_levels return value\r | |
381 | from PAL_CACHE_SUMMARY.\r | |
382 | \r | |
383 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
384 | for instruction cache and 2 for data or\r | |
385 | unified cache. All other values are\r | |
386 | reserved.\r | |
387 | \r | |
388 | @param ProcNumber Unsigned 64-bit integer that specifies for\r | |
389 | which logical processor information is\r | |
390 | being requested. This input argument must\r | |
391 | be zero for the first call to this\r | |
392 | procedure and can be a maximum value of\r | |
393 | one less than the number of logical\r | |
394 | processors sharing this cache, which is\r | |
395 | returned by the num_shared return value.\r | |
396 | \r | |
397 | @return R9 Unsigned integer that returns the number of\r | |
398 | logical processors that share the processor\r | |
399 | cache level and type, for which information was\r | |
400 | requested.\r | |
401 | \r | |
402 | @return R10 The format of PAL_PCOC_N_CACHE_INFO1.\r | |
403 | \r | |
404 | @return R11 The format of PAL_PCOC_N_CACHE_INFO2.\r | |
405 | \r | |
406 | @return Status 0 - Call completed without error\r | |
407 | \r | |
408 | @return Status -1 - Unimplemented procedure\r | |
409 | \r | |
410 | @return Status -2 - Invalid argument\r | |
411 | \r | |
412 | @return Status -3 - Call completed with error.\r | |
413 | \r | |
414 | **/\r | |
415 | #define PAL_CACHE_SHARED_INFO 43\r | |
416 | \r | |
417 | \r | |
418 | /**\r | |
419 | \r | |
420 | PAL Procedure - PAL_CACHE_SUMMARY.\r | |
421 | \r | |
422 | Return a summary of the cache hierarchy. It is required by\r | |
423 | IPF. The PAL procedure supports the Static Registers calling\r | |
424 | convention. It could be called at physical mode and Virtual\r | |
425 | mode.\r | |
426 | \r | |
427 | @param Index Index of PAL_CACHE_SUMMARY within the list of\r | |
428 | PAL procedures.\r | |
429 | \r | |
430 | \r | |
431 | @return R9 CacheLevels Unsigned 64-bit integer denoting the\r | |
432 | number of levels of cache\r | |
433 | implemented by the processor.\r | |
434 | Strictly, this is the number of\r | |
435 | levels for which the cache\r | |
436 | controller is integrated into the\r | |
437 | processor (the cache SRAMs may be\r | |
438 | external to the processor).\r | |
439 | \r | |
440 | @return R10 UniqueCaches Unsigned 64-bit integer denoting the\r | |
441 | number of unique caches implemented\r | |
442 | by the processor. This has a maximum\r | |
443 | of 2*cache_levels, but may be less\r | |
444 | if any of the levels in the cache\r | |
445 | hierarchy are unified caches or do\r | |
446 | not have both instruction and data\r | |
447 | caches.\r | |
448 | \r | |
449 | @return Status 0 - Call completed without error\r | |
450 | \r | |
451 | @return Status -2 - Invalid argument\r | |
452 | \r | |
453 | @return Status -3 - Call completed with error.\r | |
454 | \r | |
455 | **/\r | |
456 | #define PAL_CACHE_SUMMARY 4\r | |
457 | \r | |
458 | \r | |
459 | //\r | |
460 | // Virtual Memory Attributes implemented by processor. \r | |
461 | // \r | |
462 | #define PAL_MEMORY_ATTR_WB 0\r | |
463 | #define PAL_MEMORY_ATTR_WC 6\r | |
464 | #define PAL_MEMORY_ATTR_UC 4\r | |
465 | #define PAL_MEMORY_ATTR_UCE 5\r | |
466 | #define PAL_MEMORY_ATTR_NATPAGE 7\r | |
467 | \r | |
468 | /**\r | |
469 | \r | |
470 | PAL Procedure - PAL_MEM_ATTRIB.\r | |
471 | \r | |
472 | Return a list of supported memory attributes.. It is required\r | |
473 | by IPF. The PAL procedure supports the Static Registers calling\r | |
474 | convention. It could be called at physical mode and Virtual\r | |
475 | mode.\r | |
476 | \r | |
477 | @param Index Index of PAL_MEM_ATTRIB within the list of PAL\r | |
478 | procedures.\r | |
479 | \r | |
480 | \r | |
481 | @return R9 Attributes 8-bit vector of memory attributes\r | |
482 | implemented by processor. See Virtual\r | |
483 | Memory Attributes above.\r | |
484 | \r | |
485 | @return Status 0 - Call completed without error\r | |
486 | \r | |
487 | @return Status -2 - Invalid argument\r | |
488 | \r | |
489 | @return Status -3 - Call completed with error.\r | |
490 | \r | |
491 | **/\r | |
492 | \r | |
493 | #define PAL_MEM_ATTRIB 5\r | |
494 | \r | |
495 | /**\r | |
496 | \r | |
497 | PAL Procedure - PAL_PREFETCH_VISIBILITY.\r | |
498 | \r | |
499 | Used in architected sequence to transition pages from a\r | |
500 | cacheable, speculative attribute to an uncacheable attribute.\r | |
501 | It is required by IPF. The PAL procedure supports the Static\r | |
502 | Registers calling convention. It could be called at physical\r | |
503 | mode and Virtual mode.\r | |
504 | \r | |
505 | @param Index Index of PAL_PREFETCH_VISIBILITY within the list\r | |
506 | of PAL procedures.\r | |
507 | \r | |
508 | @param TransitionType Unsigned integer specifying the type\r | |
509 | of memory attribute transition that is\r | |
510 | being performed.\r | |
511 | \r | |
512 | @return Status 1 Call completed without error; this\r | |
513 | call is not necessary on remote\r | |
514 | processors.\r | |
515 | \r | |
516 | @return Status 0 - Call completed without error\r | |
517 | \r | |
518 | @return Status -2 - Invalid argument\r | |
519 | \r | |
520 | @return Status -3 - Call completed with error.\r | |
521 | \r | |
522 | **/\r | |
523 | #define PAL_PREFETCH_VISIBILITY 41\r | |
524 | \r | |
525 | /**\r | |
526 | \r | |
527 | PAL Procedure - PAL_PTCE_INFO.\r | |
528 | \r | |
529 | Return information needed for ptc.e instruction to purge\r | |
530 | entire TC. It is required by IPF. The PAL procedure supports\r | |
531 | the Static Registers calling convention. It could be called at\r | |
532 | physical mode and Virtual mode.\r | |
533 | \r | |
534 | @param Index Index of PAL_PTCE_INFO within the list\r | |
535 | of PAL procedures.\r | |
536 | \r | |
537 | @return R9 Unsigned 64-bit integer denoting the beginning\r | |
538 | address to be used by the first PTCE instruction\r | |
539 | in the purge loop.\r | |
540 | \r | |
541 | @return R10 Two unsigned 32-bit integers denoting the loop\r | |
542 | counts of the outer (loop 1) and inner (loop 2)\r | |
543 | purge loops. count1 (loop 1) is contained in bits\r | |
544 | 63:32 of the parameter, and count2 (loop 2) is\r | |
545 | contained in bits 31:0 of the parameter.\r | |
546 | \r | |
547 | @return R11 Two unsigned 32-bit integers denoting the loop\r | |
548 | strides of the outer (loop 1) and inner (loop 2)\r | |
549 | purge loops. stride1 (loop 1) is contained in bits\r | |
550 | 63:32 of the parameter, and stride2 (loop 2) is\r | |
551 | contained in bits 31:0 of the parameter.\r | |
552 | \r | |
553 | @return Status 0 - Call completed without error\r | |
554 | \r | |
555 | @return Status -2 - Invalid argument\r | |
556 | \r | |
557 | @return Status -3 - Call completed with error.\r | |
558 | \r | |
559 | **/\r | |
560 | #define PAL_PTCE_INFO 6\r | |
561 | \r | |
562 | \r | |
563 | \r | |
564 | /**\r | |
565 | \r | |
566 | @param NumberSets Unsigned 8-bit integer denoting the number\r | |
567 | of hash sets for the specified level\r | |
568 | (1=fully associative)\r | |
569 | \r | |
570 | @param NumberWays Unsigned 8-bit integer denoting the\r | |
571 | associativity of the specified level\r | |
572 | (1=direct).\r | |
573 | \r | |
574 | @param NumberEntries Unsigned 16-bit integer denoting the\r | |
575 | number of entries in the specified TC.\r | |
576 | \r | |
577 | \r | |
578 | @param PageSizeIsOptimized Flag denoting whether the\r | |
579 | specified level is optimized for\r | |
580 | the region's preferred page size\r | |
581 | (1=optimized) tc_pages indicates\r | |
582 | which page sizes are usable by\r | |
583 | this translation cache.\r | |
584 | \r | |
585 | @param TcIsUnified Flag denoting whether the specified TC is\r | |
586 | unified (1=unified).\r | |
587 | \r | |
588 | @param EntriesReduction Flag denoting whether installed\r | |
589 | translation registers will reduce\r | |
590 | the number of entries within the\r | |
591 | specified TC.\r | |
592 | \r | |
593 | **/\r | |
594 | typedef struct {\r | |
595 | UINT64 NumberSets:8;\r | |
596 | UINT64 NumberWays:8;\r | |
597 | UINT64 NumberEntries:16;\r | |
598 | UINT64 PageSizeIsOptimized:1;\r | |
599 | UINT64 TcIsUnified:1;\r | |
600 | UINT64 EntriesReduction:1;\r | |
601 | } PAL_TC_INFO;\r | |
602 | \r | |
603 | /**\r | |
604 | \r | |
605 | PAL Procedure - PAL_VM_INFO.\r | |
606 | \r | |
607 | Return detailed information about virtual memory features\r | |
608 | supported in the processor. It is required by IPF. The PAL\r | |
609 | procedure supports the Static Registers calling convention. It\r | |
610 | could be called at physical mode and Virtual mode.\r | |
611 | \r | |
612 | @param Index Index of PAL_VM_INFO within the list\r | |
613 | of PAL procedures.\r | |
614 | \r | |
615 | @param TcLevel Unsigned 64-bit integer specifying the level\r | |
616 | in the TLB hierarchy for which information is\r | |
617 | required. This value must be between 0 and one\r | |
618 | less than the value returned in the\r | |
619 | vm_info_1.num_tc_levels return value from\r | |
620 | PAL_VM_SUMMARY.\r | |
621 | \r | |
622 | @param TcType Unsigned 64-bit integer with a value of 1 for\r | |
623 | instruction translation cache and 2 for data\r | |
624 | or unified translation cache. All other values\r | |
625 | are reserved.\r | |
626 | \r | |
627 | @return R9 8-byte formatted value returning information\r | |
628 | about the specified TC. See PAL_TC_INFO above.\r | |
629 | \r | |
630 | @return R10 64-bit vector containing a bit for each page\r | |
631 | size supported in the specified TC, where bit\r | |
632 | position n indicates a page size of 2**n.\r | |
633 | \r | |
634 | @return Status 0 - Call completed without error\r | |
635 | \r | |
636 | @return Status -2 - Invalid argument\r | |
637 | \r | |
638 | @return Status -3 - Call completed with error.\r | |
639 | \r | |
640 | **/\r | |
641 | #define PAL_VM_INFO 7\r | |
642 | \r | |
643 | \r | |
644 | /**\r | |
645 | \r | |
646 | PAL Procedure - PAL_VM_PAGE_SIZE.\r | |
647 | \r | |
648 | Return virtual memory TC and hardware walker page sizes\r | |
649 | supported in the processor. It is required by IPF. The PAL\r | |
650 | procedure supports the Static Registers calling convention. It\r | |
651 | could be called at physical mode and Virtual mode.\r | |
652 | \r | |
653 | @param Index Index of PAL_VM_PAGE_SIZE within the list\r | |
654 | of PAL procedures.\r | |
655 | \r | |
656 | \r | |
657 | @return R9 64-bit vector containing a bit for each\r | |
658 | architected page size that is supported for\r | |
659 | TLB insertions and region registers.\r | |
660 | \r | |
661 | @return R10 64-bit vector containing a bit for each\r | |
662 | architected page size supported for TLB purge\r | |
663 | operations.\r | |
664 | \r | |
665 | @return Status 0 - Call completed without error\r | |
666 | \r | |
667 | @return Status -2 - Invalid argument\r | |
668 | \r | |
669 | @return Status -3 - Call completed with error.\r | |
670 | \r | |
671 | **/\r | |
672 | #define PAL_VM_PAGE_SIZE 34\r | |
673 | \r | |
674 | /**\r | |
675 | \r | |
676 | @param WalkerPresent 1-bit flag indicating whether a hardware\r | |
677 | TLB walker is implemented (1 = walker\r | |
678 | present).\r | |
679 | \r | |
680 | @param WidthOfPhysicalAddress Unsigned 7-bit integer\r | |
681 | denoting the number of bits of\r | |
682 | physical address implemented.\r | |
683 | \r | |
684 | @param WidthOfKey Unsigned 8-bit integer denoting the number\r | |
685 | of bits mplemented in the PKR.key field.\r | |
686 | \r | |
687 | @param MaxPkrIndex Unsigned 8-bit integer denoting the\r | |
688 | maximum PKR index (number of PKRs-1).\r | |
689 | \r | |
690 | @param HashTagId Unsigned 8-bit integer which uniquely\r | |
691 | identifies the processor hash and tag\r | |
692 | algorithm.\r | |
693 | \r | |
694 | @param MaxDtrIndex Unsigned 8 bit integer denoting the\r | |
695 | maximum data translation register index\r | |
696 | (number of dtr entries - 1).\r | |
697 | \r | |
698 | @param MaxItrIndex Unsigned 8 bit integer denoting the\r | |
699 | maximum instruction translation register\r | |
700 | index (number of itr entries - 1).\r | |
701 | \r | |
702 | @param NumberOfUniqueTc Unsigned 8-bit integer denoting the\r | |
703 | number of unique TCs implemented.\r | |
704 | This is a maximum of\r | |
705 | 2*num_tc_levels.\r | |
706 | \r | |
707 | @param NumberOfTcLevels Unsigned 8-bit integer denoting the\r | |
708 | number of TC levels.\r | |
709 | \r | |
710 | **/\r | |
711 | typedef struct {\r | |
712 | UINT64 WalkerPresent:1;\r | |
713 | UINT64 WidthOfPhysicalAddress: 7;\r | |
714 | UINT64 WidthOfKey:8;\r | |
715 | UINT64 MaxPkrIndex:8;\r | |
716 | UINT64 HashTagId:8;\r | |
717 | UINT64 MaxDtrIndex:8;\r | |
718 | UINT64 MaxItrIndex:8;\r | |
719 | UINT64 NumberOfUniqueTc:8;\r | |
720 | UINT64 NumberOfTcLevels:8;\r | |
721 | } PAL_VM_INFO1;\r | |
722 | \r | |
723 | /**\r | |
724 | \r | |
725 | @param WidthOfVirtualAddress Unsigned 8-bit integer denoting\r | |
726 | is the total number of virtual\r | |
727 | address bits - 1.\r | |
728 | \r | |
729 | @param WidthOfRid Unsigned 8-bit integer denoting the number\r | |
730 | of bits implemented in the RR.rid field.\r | |
731 | \r | |
732 | @param MaxPurgedTlbs Unsigned 16 bit integer denoting the\r | |
733 | maximum number of concurrent outstanding\r | |
734 | TLB purges allowed by the processor. A\r | |
735 | value of 0 indicates one outstanding\r | |
736 | purge allowed. A value of 216-1\r | |
737 | indicates no limit on outstanding\r | |
738 | purges. All other values indicate the\r | |
739 | actual number of concurrent outstanding\r | |
740 | purges allowed.\r | |
741 | \r | |
742 | **/\r | |
743 | typedef struct {\r | |
744 | UINT64 WidthOfVirtualAddress:8;\r | |
745 | UINT64 WidthOfRid:8;\r | |
746 | UINT64 MaxPurgedTlbs:16;\r | |
747 | UINT64 Reserved:32;\r | |
748 | } PAL_VM_INFO2;\r | |
749 | \r | |
750 | /**\r | |
751 | \r | |
752 | PAL Procedure - PAL_VM_SUMMARY.\r | |
753 | \r | |
754 | Return summary information about virtual memory features\r | |
755 | supported in the processor. It is required by IPF. The PAL\r | |
756 | procedure supports the Static Registers calling convention. It\r | |
757 | could be called at physical mode and Virtual mode.\r | |
758 | \r | |
759 | @param Index Index of PAL_VM_SUMMARY within the list\r | |
760 | of PAL procedures.\r | |
761 | \r | |
762 | \r | |
763 | @return R9 8-byte formatted value returning global virtual\r | |
764 | memory information. See PAL_VM_INFO1 above.\r | |
765 | \r | |
766 | @return R10 8-byte formatted value returning global virtual\r | |
767 | memory information. See PAL_VM_INFO2 above.\r | |
768 | \r | |
769 | @return Status 0 - Call completed without error\r | |
770 | \r | |
771 | @return Status -2 - Invalid argument\r | |
772 | \r | |
773 | @return Status -3 - Call completed with error.\r | |
774 | \r | |
775 | **/\r | |
776 | #define PAL_VM_SUMMARY 8\r | |
777 | \r | |
778 | \r | |
779 | //\r | |
780 | // Bit mask of TR_valid flag.\r | |
781 | // \r | |
782 | #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r | |
783 | #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r | |
784 | #define PAL_TR_DIRTY_IS_VALID BIT2\r | |
785 | #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3\r | |
786 | \r | |
787 | \r | |
788 | /**\r | |
789 | \r | |
790 | PAL Procedure - PAL_VM_TR_READ.\r | |
791 | \r | |
792 | Read contents of a translation register. It is required by\r | |
793 | IPF. The PAL procedure supports the Stacked Register calling\r | |
794 | convention. It could be called at physical mode.\r | |
795 | \r | |
796 | @param Index Index of PAL_VM_TR_READ within the list\r | |
797 | of PAL procedures.\r | |
798 | \r | |
799 | @param RegNumber Unsigned 64-bit number denoting which TR to\r | |
800 | read.\r | |
801 | \r | |
802 | @param TrType Unsigned 64-bit number denoting whether to\r | |
803 | read an ITR (0) or DTR (1). All other values\r | |
804 | are reserved.\r | |
805 | \r | |
806 | @param TrBuffer 64-bit pointer to the 32-byte memory buffer in\r | |
807 | which translation data is returned.\r | |
808 | \r | |
809 | @return R9 Formatted bit vector denoting which fields are\r | |
810 | valid. See TR_valid above.\r | |
811 | \r | |
812 | @return Status 0 - Call completed without error\r | |
813 | \r | |
814 | @return Status -2 - Invalid argument\r | |
815 | \r | |
816 | @return Status -3 - Call completed with error.\r | |
817 | \r | |
818 | **/\r | |
819 | #define PAL_VM_TR_READ 261 \r | |
820 | \r | |
821 | \r | |
822 | \r | |
823 | \r | |
824 | //\r | |
825 | // Bit Mask of Processor Bus Fesatures .\r | |
826 | // \r | |
827 | \r | |
828 | /**\r | |
829 | \r | |
830 | When 0, bus data errors are detected and single bit errors are\r | |
831 | corrected. When 1, no error detection or correction is done.\r | |
832 | \r | |
833 | **/\r | |
834 | #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63\r | |
835 | \r | |
836 | \r | |
837 | /**\r | |
838 | \r | |
839 | When 0, bus address errors are signalled on the bus. When 1,\r | |
840 | no bus errors are signalled on the bus. If Disable Bus Address\r | |
841 | Error Checking is 1, this bit is ignored.\r | |
842 | \r | |
843 | **/\r | |
844 | #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62\r | |
845 | \r | |
846 | \r | |
847 | \r | |
848 | \r | |
849 | /**\r | |
850 | \r | |
851 | When 0, bus errors are detected, single bit errors are\r | |
852 | corrected., and a CMCI or MCA is generated internally to the\r | |
853 | processor. When 1, no bus address errors are detected or\r | |
854 | corrected.\r | |
855 | \r | |
856 | **/\r | |
857 | #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61\r | |
858 | \r | |
859 | \r | |
860 | /**\r | |
861 | \r | |
862 | When 0, bus protocol errors (BINIT#) are signaled by the\r | |
863 | processor on the bus. When 1, bus protocol errors (BINIT#) are\r | |
864 | not signaled on the bus. If Disable Bus Initialization Event\r | |
865 | Checking is 1, this bit is ignored.\r | |
866 | \r | |
867 | **/\r | |
868 | #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60\r | |
869 | \r | |
870 | \r | |
871 | /**\r | |
872 | \r | |
873 | When 0, bus protocol errors (BINIT#) are detected and sampled\r | |
874 | and an MCA is generated internally to the processor. When 1,\r | |
875 | the processor will ignore bus protocol error conditions\r | |
876 | (BINIT#).\r | |
877 | \r | |
878 | **/\r | |
879 | #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59\r | |
880 | \r | |
881 | \r | |
882 | \r | |
883 | /**\r | |
884 | \r | |
885 | When 0, BERR# is signalled if a bus error is detected. When 1,\r | |
886 | bus errors are not signalled on the bus.\r | |
887 | \r | |
888 | **/\r | |
889 | #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58\r | |
890 | \r | |
891 | \r | |
892 | \r | |
893 | \r | |
894 | /**\r | |
895 | \r | |
896 | When 0, BERR# is signalled when internal processor requestor\r | |
897 | initiated bus errors are detected. When 1, internal requester\r | |
898 | bus errors are not signalled on the bus.\r | |
899 | \r | |
900 | **/\r | |
901 | #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r | |
902 | \r | |
903 | \r | |
904 | /**\r | |
905 | \r | |
906 | When 0, the processor takes an MCA if BERR# is asserted. When\r | |
907 | 1, the processor ignores the BERR# signal.\r | |
908 | \r | |
909 | **/\r | |
910 | #define PAL_BUS_DISABLE_ERROR_CHECK BIT56\r | |
911 | \r | |
912 | \r | |
913 | /**\r | |
914 | \r | |
915 | When 0, the processor asserts BINIT# if it detects a parity\r | |
916 | error on the signals which identify the transactions to which\r | |
917 | this is a response. When 1, the processor ignores parity on\r | |
918 | these signals.\r | |
919 | \r | |
920 | **/\r | |
921 | #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r | |
922 | \r | |
923 | \r | |
924 | /**\r | |
925 | \r | |
926 | When 0, the in-order transaction queue is limited only by the\r | |
927 | number of hardware entries. When 1, the processor's in-order\r | |
928 | transactions queue is limited to one entry.\r | |
929 | \r | |
930 | **/\r | |
931 | #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r | |
932 | \r | |
933 | /**\r | |
934 | \r | |
935 | Enable a bus cache line replacement transaction when a cache\r | |
936 | line in the exclusive state is replaced from the highest level\r | |
937 | processor cache and is not present in the lower level processor\r | |
938 | caches. When 0, no bus cache line replacement transaction will\r | |
939 | be seen on the bus. When 1, bus cache line replacement\r | |
940 | transactions will be seen on the bus when the above condition is\r | |
941 | detected.\r | |
942 | \r | |
943 | **/\r | |
944 | #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53\r | |
945 | \r | |
946 | \r | |
947 | /**\r | |
948 | \r | |
949 | Enable a bus cache line replacement transaction when a cache\r | |
950 | line in the shared or exclusive state is replaced from the\r | |
951 | highest level processor cache and is not present in the lower\r | |
952 | level processor caches.\r | |
953 | When 0, no bus cache line replacement transaction will be seen\r | |
954 | on the bus. When 1, bus cache line replacement transactions\r | |
955 | will be seen on the bus when the above condition is detected.\r | |
956 | \r | |
957 | **/\r | |
958 | #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r | |
959 | \r | |
960 | \r | |
961 | \r | |
962 | /**\r | |
963 | \r | |
964 | When 0, the data bus is configured at the 2x data transfer\r | |
965 | rate.When 1, the data bus is configured at the 1x data\r | |
966 | transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r | |
967 | processor executes locked transactions atomically. When 1, the\r | |
968 | processor masks the bus lock signal and executes locked\r | |
969 | transactions as a non-atomic series of transactions.\r | |
970 | \r | |
971 | **/\r | |
972 | #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r | |
973 | \r | |
974 | /**\r | |
975 | \r | |
976 | When 0, the processor will deassert bus request when finished\r | |
977 | with each transaction. When 1, the processor will continue to\r | |
978 | assert bus request after it has finished, if it was the last\r | |
979 | agent to own the bus and if there are no other pending\r | |
980 | requests.\r | |
981 | \r | |
982 | **/\r | |
983 | #define PAL_BUS_REQUEST_BUS_PARKING BIT29\r | |
984 | \r | |
985 | \r | |
986 | /**\r | |
987 | \r | |
988 | PAL Procedure - PAL_BUS_GET_FEATURES.\r | |
989 | \r | |
990 | Return configurable processor bus interface features and their\r | |
991 | current settings. It is required by IPF. The PAL procedure\r | |
992 | supports the Stacked Register calling convention. It could be\r | |
993 | called at physical mode.\r | |
994 | \r | |
995 | @param Index Index of PAL_BUS_GET_FEATURES within the list\r | |
996 | of PAL procedures.\r | |
997 | \r | |
998 | @return R9 64-bit vector of features implemented.\r | |
999 | (1=implemented, 0=not implemented)\r | |
1000 | \r | |
1001 | @return R10 64-bit vector of current feature settings.\r | |
1002 | \r | |
1003 | @return R11 64-bit vector of features controllable by\r | |
1004 | software. (1=controllable, 0= not controllable)\r | |
1005 | \r | |
1006 | @return Status 0 - Call completed without error\r | |
1007 | \r | |
1008 | @return Status -2 - Invalid argument\r | |
1009 | \r | |
1010 | @return Status -3 - Call completed with error.\r | |
1011 | \r | |
1012 | **/\r | |
1013 | #define PAL_BUS_GET_FEATURES 9\r | |
1014 | \r | |
1015 | /**\r | |
1016 | \r | |
1017 | PAL Procedure - PAL_BUS_SET_FEATURES.\r | |
1018 | \r | |
1019 | Enable or disable configurable features in processor bus\r | |
1020 | interface. It is required by IPF. It is required by IPF. The PAL procedure\r | |
1021 | supports the Static Registers calling convention. It could be\r | |
1022 | called at physical mode.\r | |
1023 | \r | |
1024 | @param Index Index of PAL_BUS_SET_FEATURES within the list\r | |
1025 | of PAL procedures.\r | |
1026 | \r | |
1027 | @param FeatureSelect 64-bit vector denoting desired state of\r | |
1028 | each feature (1=select, 0=non-select).\r | |
1029 | \r | |
1030 | @return Status 0 - Call completed without error\r | |
1031 | \r | |
1032 | @return Status -2 - Invalid argument\r | |
1033 | \r | |
1034 | @return Status -3 - Call completed with error.\r | |
1035 | \r | |
1036 | **/\r | |
1037 | #define PAL_BUS_SET_FEATURES 10\r | |
1038 | \r | |
1039 | \r | |
1040 | /**\r | |
1041 | \r | |
1042 | PAL Procedure - PAL_DEBUG_INFO.\r | |
1043 | \r | |
1044 | Return the number of instruction and data breakpoint\r | |
1045 | registers. It is required by IPF. It is required by IPF. The\r | |
1046 | PAL procedure supports the Static Registers calling\r | |
1047 | convention. It could be called at physical mode and virtual\r | |
1048 | mode.\r | |
1049 | \r | |
1050 | @param Index Index of PAL_DEBUG_INFO within the list of PAL\r | |
1051 | procedures.\r | |
1052 | \r | |
1053 | @return R9 Unsigned 64-bit integer denoting the number of\r | |
1054 | pairs of instruction debug registers implemented\r | |
1055 | by the processor. \r | |
1056 | \r | |
1057 | @return R10 Unsigned 64-bit integer denoting the number of\r | |
1058 | pairs of data debug registers implemented by the\r | |
1059 | processor.\r | |
1060 | \r | |
1061 | @return Status 0 - Call completed without error\r | |
1062 | \r | |
1063 | @return Status -2 - Invalid argument\r | |
1064 | \r | |
1065 | @return Status -3 - Call completed with error.\r | |
1066 | \r | |
1067 | **/\r | |
1068 | #define PAL_DEBUG_INFO 11\r | |
1069 | \r | |
1070 | /**\r | |
1071 | \r | |
1072 | PAL Procedure - PAL_FIXED_ADDR.\r | |
1073 | \r | |
1074 |