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878ddf1f | 1 | /** @file\r |
2 | Cache Maintenance Functions.\r | |
3 | \r | |
4 | Copyright (c) 2006, Intel Corporation<BR>\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
878ddf1f | 15 | \r |
9f84a609 | 16 | /**\r |
17 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
18 | calling CPU.\r | |
19 | \r | |
20 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
21 | calling CPU.\r | |
22 | \r | |
23 | **/\r | |
878ddf1f | 24 | VOID\r |
25 | EFIAPI\r | |
26 | InvalidateInstructionCache (\r | |
27 | VOID\r | |
28 | )\r | |
29 | {\r | |
e65e8d10 | 30 | PalCallStatic (NULL, 1, 1, 1, 0);\r |
9f84a609 | 31 | }\r |
32 | \r | |
cd4903c4 | 33 | /**\r |
34 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
35 | of the calling CPU.\r | |
36 | \r | |
37 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
38 | Address is not aligned on a cache line boundary, then entire instruction\r | |
39 | cache line containing Address is invalidated. If Address + Length is not\r | |
40 | aligned on a cache line boundary, then the entire instruction cache line\r | |
41 | containing Address + Length -1 is invalidated. This function may choose to\r | |
42 | invalidate the entire instruction cache if that is more efficient than\r | |
43 | invalidating the specified range. If Length is 0, the no instruction cache\r | |
44 | lines are invalidated. Address is returned.\r | |
45 | \r | |
46 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
47 | \r | |
48 | @param Address The base address of the instruction cache lines to\r | |
49 | invalidate. If the CPU is in a physical addressing mode, then\r | |
50 | Address is a physical address. If the CPU is in a virtual\r | |
51 | addressing mode, then Address is a virtual address.\r | |
52 | \r | |
53 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
54 | \r | |
55 | @return Address\r | |
56 | \r | |
57 | **/\r | |
58 | VOID *\r | |
59 | EFIAPI\r | |
60 | InvalidateInstructionCacheRange (\r | |
61 | IN VOID *Address,\r | |
62 | IN UINTN Length\r | |
63 | )\r | |
64 | {\r | |
92ea7f23 | 65 | return IpfFlushCacheRange (Address, Length);\r |
cd4903c4 | 66 | }\r |
67 | \r | |
9f84a609 | 68 | /**\r |
69 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
70 | of the calling CPU.\r | |
71 | \r | |
72 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
73 | of the calling CPU. This function guarantees that all dirty cache lines are\r | |
74 | written back to system memory, and also invalidates all the data cache lines\r | |
75 | in the cache coherency domain of the calling CPU.\r | |
76 | \r | |
77 | **/\r | |
878ddf1f | 78 | VOID\r |
79 | EFIAPI\r | |
80 | WriteBackInvalidateDataCache (\r | |
81 | VOID\r | |
82 | )\r | |
83 | {\r | |
e65e8d10 | 84 | PalCallStatic (NULL, 1, 2, 1, 0);\r |
878ddf1f | 85 | }\r |
86 | \r | |
9f84a609 | 87 | /**\r |
88 | Writes Back and Invalidates a range of data cache lines in the cache\r | |
89 | coherency domain of the calling CPU.\r | |
90 | \r | |
91 | Writes Back and Invalidate the data cache lines specified by Address and\r | |
92 | Length. If Address is not aligned on a cache line boundary, then entire data\r | |
93 | cache line containing Address is written back and invalidated. If Address +\r | |
94 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
95 | line containing Address + Length -1 is written back and invalidated. This\r | |
96 | function may choose to write back and invalidate the entire data cache if\r | |
97 | that is more efficient than writing back and invalidating the specified\r | |
98 | range. If Length is 0, the no data cache lines are written back and\r | |
99 | invalidated. Address is returned.\r | |
100 | \r | |
101 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
102 | \r | |
103 | @param Address The base address of the data cache lines to write back and\r | |
104 | invalidate. If the CPU is in a physical addressing mode, then\r | |
105 | Address is a physical address. If the CPU is in a virtual\r | |
106 | addressing mode, then Address is a virtual address.\r | |
107 | @param Length The number of bytes to write back and invalidate from the\r | |
108 | data cache.\r | |
109 | \r | |
110 | @return Address\r | |
111 | \r | |
112 | **/\r | |
878ddf1f | 113 | VOID *\r |
114 | EFIAPI\r | |
115 | WriteBackInvalidateDataCacheRange (\r | |
116 | IN VOID *Address,\r | |
117 | IN UINTN Length\r | |
118 | )\r | |
119 | {\r | |
9f84a609 | 120 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
121 | \r | |
92ea7f23 | 122 | return IpfFlushCacheRange (Address, Length);\r |
878ddf1f | 123 | }\r |
124 | \r | |
9f84a609 | 125 | /**\r |
126 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
127 | CPU.\r | |
128 | \r | |
129 | Writes Back the entire data cache in cache coherency domain of the calling\r | |
130 | CPU. This function guarantees that all dirty cache lines are written back to\r | |
131 | system memory. This function may also invalidate all the data cache lines in\r | |
132 | the cache coherency domain of the calling CPU.\r | |
133 | \r | |
134 | **/\r | |
878ddf1f | 135 | VOID\r |
136 | EFIAPI\r | |
137 | WriteBackDataCache (\r | |
138 | VOID\r | |
139 | )\r | |
140 | {\r | |
e65e8d10 | 141 | PalCallStatic (NULL, 1, 2, 0, 0);\r |
878ddf1f | 142 | }\r |
143 | \r | |
9f84a609 | 144 | /**\r |
145 | Writes Back a range of data cache lines in the cache coherency domain of the\r | |
146 | calling CPU.\r | |
147 | \r | |
148 | Writes Back the data cache lines specified by Address and Length. If Address\r | |
149 | is not aligned on a cache line boundary, then entire data cache line\r | |
150 | containing Address is written back. If Address + Length is not aligned on a\r | |
151 | cache line boundary, then the entire data cache line containing Address +\r | |
152 | Length -1 is written back. This function may choose to write back the entire\r | |
153 | data cache if that is more efficient than writing back the specified range.\r | |
154 | If Length is 0, the no data cache lines are written back. This function may\r | |
155 | also invalidate all the data cache lines in the specified range of the cache\r | |
156 | coherency domain of the calling CPU. Address is returned.\r | |
157 | \r | |
158 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
159 | \r | |
160 | @param Address The base address of the data cache lines to write back. If\r | |
161 | the CPU is in a physical addressing mode, then Address is a\r | |
162 | physical address. If the CPU is in a virtual addressing\r | |
163 | mode, then Address is a virtual address.\r | |
164 | @param Length The number of bytes to write back from the data cache.\r | |
165 | \r | |
166 | @return Address\r | |
167 | \r | |
168 | **/\r | |
878ddf1f | 169 | VOID *\r |
170 | EFIAPI\r | |
171 | WriteBackDataCacheRange (\r | |
172 | IN VOID *Address,\r | |
173 | IN UINTN Length\r | |
174 | )\r | |
175 | {\r | |
9f84a609 | 176 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
177 | \r | |
92ea7f23 | 178 | return IpfFlushCacheRange (Address, Length);\r |
878ddf1f | 179 | }\r |
180 | \r | |
9f84a609 | 181 | /**\r |
182 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
183 | CPU.\r | |
184 | \r | |
185 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
186 | CPU. This function must be used with care because dirty cache lines are not\r | |
187 | written back to system memory. It is typically used for cache diagnostics. If\r | |
188 | the CPU does not support invalidation of the entire data cache, then a write\r | |
189 | back and invalidate operation should be performed on the entire data cache.\r | |
190 | \r | |
191 | **/\r | |
878ddf1f | 192 | VOID\r |
193 | EFIAPI\r | |
194 | InvalidateDataCache (\r | |
195 | VOID\r | |
196 | )\r | |
197 | {\r | |
9f84a609 | 198 | WriteBackInvalidateDataCache ();\r |
878ddf1f | 199 | }\r |
200 | \r | |
9f84a609 | 201 | /**\r |
202 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
203 | calling CPU.\r | |
204 | \r | |
205 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
206 | is not aligned on a cache line boundary, then entire data cache line\r | |
207 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
208 | cache line boundary, then the entire data cache line containing Address +\r | |
209 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
210 | outside the specified range. If Length is 0, the no data cache lines are\r | |
211 | invalidated. Address is returned. This function must be used with care\r | |
212 | because dirty cache lines are not written back to system memory. It is\r | |
213 | typically used for cache diagnostics. If the CPU does not support\r | |
214 | invalidation of a data cache range, then a write back and invalidate\r | |
215 | operation should be performed on the data cache range.\r | |
216 | \r | |
217 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
218 | \r | |
219 | @param Address The base address of the data cache lines to invalidate. If\r | |
220 | the CPU is in a physical addressing mode, then Address is a\r | |
221 | physical address. If the CPU is in a virtual addressing mode,\r | |
222 | then Address is a virtual address.\r | |
223 | @param Length The number of bytes to invalidate from the data cache.\r | |
224 | \r | |
225 | @return Address\r | |
226 | \r | |
227 | **/\r | |
878ddf1f | 228 | VOID *\r |
229 | EFIAPI\r | |
230 | InvalidateDataCacheRange (\r | |
231 | IN VOID *Address,\r | |
232 | IN UINTN Length\r | |
233 | )\r | |
234 | {\r | |
92ea7f23 | 235 | return IpfFlushCacheRange (Address, Length);\r |
878ddf1f | 236 | }\r |