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1e57a462 | 1 | /** @file\r |
2 | \r | |
3402aac7 RC |
3 | Abstractions for simple OMAP DMA.\r |
4 | OMAP_DMA4 structure elements are described in the OMAP35xx TRM.\r | |
1e57a462 | 5 | \r |
6 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r | |
7 | \r | |
8 | This program and the accompanying materials\r | |
9 | are licensed and made available under the terms and conditions of the BSD License\r | |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #ifndef __OMAP_DMA_LIB_H__\r | |
19 | #define __OMAP_DMA_LIB_H__\r | |
20 | \r | |
21 | \r | |
22 | // Example from DMA chapter of the OMAP35xx spec\r | |
7f814ffd | 23 | typedef struct {\r |
24 | UINT8 DataType; // DMA4_CSDPi[1:0]\r | |
25 | UINT8 ReadPortAccessType; // DMA4_CSDPi[8:7]\r | |
26 | UINT8 WritePortAccessType; // DMA4_CSDPi[15:14]\r | |
27 | UINT8 SourceEndiansim; // DMA4_CSDPi[21]\r | |
28 | UINT8 DestinationEndianism; // DMA4_CSDPi[19]\r | |
29 | UINT8 WriteMode; // DMA4_CSDPi[17:16]\r | |
30 | UINT8 SourcePacked; // DMA4_CSDPi[6]\r | |
31 | UINT8 DestinationPacked; // DMA4_CSDPi[13]\r | |
32 | UINT32 NumberOfElementPerFrame; // DMA4_CENi\r | |
33 | UINT32 NumberOfFramePerTransferBlock; // DMA4_CFNi\r | |
34 | UINT32 SourceStartAddress; // DMA4_CSSAi\r | |
35 | UINT32 DestinationStartAddress; // DMA4_CDSAi\r | |
36 | UINT32 SourceElementIndex; // DMA4_CSEi\r | |
37 | UINT32 SourceFrameIndex; // DMA4_CSFi\r | |
38 | UINT32 DestinationElementIndex; // DMA4_CDEi\r | |
39 | UINT32 DestinationFrameIndex; // DMA4_CDFi\r | |
40 | UINT8 ReadPortAccessMode; // DMA4_CCRi[13:12]\r | |
41 | UINT8 WritePortAccessMode; // DMA4_CCRi[15:14]\r | |
42 | UINT8 ReadPriority; // DMA4_CCRi[6]\r | |
43 | UINT8 WritePriority; // DMA4_CCRi[23]\r | |
44 | UINT8 ReadRequestNumber; // DMA4_CCRi[4:0]\r | |
1e57a462 | 45 | UINT8 WriteRequestNumber; // DMA4_CCRi[20:19]\r |
46 | } OMAP_DMA4;\r | |
47 | \r | |
48 | \r | |
3402aac7 | 49 | /**\r |
7f814ffd | 50 | Configure OMAP DMA Channel\r |
3402aac7 | 51 | \r |
7f814ffd | 52 | @param Channel DMA Channel to configure\r |
3402aac7 RC |
53 | @param Dma4 Pointer to structure used to initialize DMA registers for the Channel\r |
54 | \r | |
7f814ffd | 55 | @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r |
56 | @retval EFI_INVALID_PARAMETER Channel is not valid\r | |
57 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.\r | |
3402aac7 | 58 | \r |
1e57a462 | 59 | **/\r |
60 | EFI_STATUS\r | |
61 | EFIAPI\r | |
62 | EnableDmaChannel (\r | |
63 | IN UINTN Channel,\r | |
64 | IN OMAP_DMA4 *Dma4\r | |
65 | );\r | |
66 | \r | |
3402aac7 | 67 | /**\r |
7f814ffd | 68 | Turn of DMA channel configured by EnableDma().\r |
3402aac7 | 69 | \r |
7f814ffd | 70 | @param Channel DMA Channel to configure\r |
9f6b977f | 71 | @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS\r |
72 | @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR\r | |
3402aac7 | 73 | \r |
7f814ffd | 74 | @retval EFI_SUCCESS DMA hardware disabled\r |
75 | @retval EFI_INVALID_PARAMETER Channel is not valid\r | |
76 | @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.\r | |
3402aac7 | 77 | \r |
1e57a462 | 78 | **/\r |
79 | EFI_STATUS\r | |
80 | EFIAPI\r | |
81 | DisableDmaChannel (\r | |
82 | IN UINTN Channel,\r | |
83 | IN UINT32 SuccessMask,\r | |
84 | IN UINT32 ErrorMask\r | |
85 | );\r | |
86 | \r | |
87 | \r | |
88 | \r | |
3402aac7 | 89 | #endif\r |
1e57a462 | 90 | \r |