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ef0f565c | 1 | /** @file |
2 | ||
3 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> | |
4 | ||
5 | This program and the accompanying materials | |
6 | are licensed and made available under the terms and conditions of the BSD License | |
7 | which accompanies this distribution. The full text of the license may be found at | |
8 | http://opensource.org/licenses/bsd-license.php | |
9 | ||
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
12 | ||
13 | **/ | |
14 | ||
15 | #ifndef __OMAP3530DMA_H__ | |
16 | #define __OMAP3530DMA_H__ | |
17 | ||
7f814ffd | 18 | |
19 | #define DMA4_MAX_CHANNEL 31 | |
20 | ||
21 | #define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(_i))) | |
22 | ||
23 | #define DMA4_CCR(_i) (0x48056080 + (0x60*(_i))) | |
24 | #define DMA4_CICR(_i) (0x48056088 + (0x60*(_i))) | |
9f6b977f | 25 | #define DMA4_CSR(_i) (0x4805608c + (0x60*(_i))) |
7f814ffd | 26 | #define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i))) |
27 | #define DMA4_CEN(_i) (0x48056094 + (0x60*(_i))) | |
28 | #define DMA4_CFN(_i) (0x48056098 + (0x60*(_i))) | |
29 | #define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i))) | |
30 | #define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i))) | |
31 | #define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i))) | |
32 | #define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i))) | |
33 | #define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i))) | |
34 | #define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i))) | |
35 | ||
36 | #define DMA4_GCR (0x48056078) | |
ef0f565c | 37 | |
20f461ce | 38 | // Channel Source Destination parameters |
39 | #define DMA4_CSDP_DATA_TYPE8 0 | |
40 | #define DMA4_CSDP_DATA_TYPE16 1 | |
41 | #define DMA4_CSDP_DATA_TYPE32 2 | |
42 | ||
43 | #define DMA4_CSDP_SRC_PACKED BIT6 | |
44 | #define DMA4_CSDP_SRC_NONPACKED 0 | |
45 | ||
46 | #define DMA4_CSDP_SRC_BURST_EN (0x0 << 7) | |
47 | #define DMA4_CSDP_SRC_BURST_EN16 (0x1 << 7) | |
48 | #define DMA4_CSDP_SRC_BURST_EN32 (0x2 << 7) | |
49 | #define DMA4_CSDP_SRC_BURST_EN64 (0x3 << 7) | |
50 | ||
51 | #define DMA4_CSDP_DST_PACKED BIT13 | |
52 | #define DMA4_CSDP_DST_NONPACKED 0 | |
53 | ||
54 | #define DMA4_CSDP_BURST_EN (0x0 << 14) | |
55 | #define DMA4_CSDP_BURST_EN16 (0x1 << 14) | |
56 | #define DMA4_CSDP_BURST_EN32 (0x2 << 14) | |
57 | #define DMA4_CSDP_BURST_EN64 (0x3 << 14) | |
58 | ||
59 | #define DMA4_CSDP_WRITE_MODE_NONE_POSTED (0x0 << 16) | |
60 | #define DMA4_CSDP_WRITE_MODE_POSTED (0x1 << 16) | |
61 | #define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED (0x2 << 16) | |
62 | ||
63 | #define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18 | |
64 | #define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT 0 | |
65 | ||
66 | #define DMA4_CSDP_DST_ENDIAN_BIG BIT19 | |
67 | #define DMA4_CSDP_DST_ENDIAN_LITTLE 0 | |
68 | ||
69 | #define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20 | |
70 | #define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT 0 | |
71 | ||
72 | #define DMA4_CSDP_SRC_ENDIAN_BIG BIT21 | |
73 | #define DMA4_CSDP_SRC_ENDIAN_LITTLE 0 | |
74 | ||
75 | // Channel Control | |
76 | #define DMA4_CCR_SYNCHRO_CONTROL_MASK 0x1f | |
77 | ||
78 | #define DMA4_CCR_FS_ELEMENT (0 | 0) | |
79 | #define DMA4_CCR_FS_BLOCK (0 | BIT18) | |
80 | #define DMA4_CCR_FS_FRAME (BIT5 | 0) | |
81 | #define DMA4_CCR_FS_PACKET (BIT5 | BIT18) | |
82 | ||
83 | #define DMA4_CCR_READ_PRIORITY_HIGH BIT6 | |
84 | #define DMA4_CCR_READ_PRIORITY_LOW 0 | |
85 | ||
86 | #define DMA4_CCR_ENABLE BIT7 | |
87 | #define DMA4_CCR_DISABLE 0 | |
88 | ||
89 | #define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8 | |
90 | #define DMA4_CCR_SUSPEND_SENSITIVE 0 | |
91 | ||
92 | #define DMA4_CCR_RD_ACTIVE BIT9 | |
93 | #define DMA4_CCR_WR_ACTIVE BIT10 | |
94 | ||
95 | #define DMA4_CCR_SRC_AMODE (0 | 0) | |
96 | #define DMA4_CCR_SRC_AMODE_POST_INC (0 | BIT12) | |
97 | #define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0) | |
98 | #define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12) | |
99 | ||
100 | #define DMA4_CCR_DST_AMODE (0 | 0) | |
101 | #define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14) | |
102 | #define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0) | |
103 | #define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14) | |
104 | ||
105 | #define DMA4_CCR_CONST_FILL_ENABLE BIT16 | |
106 | #define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17 | |
2b649f74 | 107 | |
7f814ffd | 108 | #define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24 |
109 | ||
9f6b977f | 110 | #define DMA4_CSR_DROP BIT1 |
111 | #define DMA4_CSR_HALF BIT2 | |
112 | #define DMA4_CSR_FRAME BIT3 | |
113 | #define DMA4_CSR_LAST BIT4 | |
114 | #define DMA4_CSR_BLOCK BIT5 | |
115 | #define DMA4_CSR_SYNC BIT6 | |
116 | #define DMA4_CSR_PKT BIT7 | |
117 | #define DMA4_CSR_TRANS_ERR BIT8 | |
118 | #define DMA4_CSR_SECURE_ERR BIT9 | |
119 | #define DMA4_CSR_SUPERVISOR_ERR BIT10 | |
120 | #define DMA4_CSR_MISALIGNED_ADRS_ERR BIT11 | |
121 | #define DMA4_CSR_DRAIN_END BIT12 | |
122 | #define DMA4_CSR_RESET 0x1FE | |
123 | #define DMA4_CSR_ERR (DMA4_CSR_TRANS_ERR | DMA4_CSR_SECURE_ERR | DMA4_CSR_SUPERVISOR_ERR | DMA4_CSR_MISALIGNED_ADRS_ERR) | |
124 | ||
125 | // same mapping as CSR except for SYNC. Enable all since we are polling | |
126 | #define DMA4_CICR_ENABLE_ALL 0x1FBE | |
127 | ||
128 | ||
ef0f565c | 129 | #endif |
130 |