[mirror_edk2.git] / Omap35xxPkg / InterruptDxe / HardwareInterrupt.c

/** @file\r
  Handle OMAP35xx interrupt controller\r
\r
  Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
#include <PiDxe.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/UefiLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/ArmLib.h>\r
\r
#include <Protocol/Cpu.h>\r
#include <Protocol/HardwareInterrupt.h>\r
\r
#include <Omap3530/Omap3530.h>\r
\r
//\r
// Notifications\r
//\r
EFI_EVENT EfiExitBootServicesEvent      = (EFI_EVENT)NULL;\r
\r
\r
HARDWARE_INTERRUPT_HANDLER  gRegisteredInterruptHandlers[INT_NROF_VECTORS];\r
\r
/**\r
  Shutdown our hardware\r
\r
  DXE Core will disable interrupts and turn off the timer and disable interrupts\r
  after all the event handlers have run.\r
\r
  @param[in]  Event   The Event that is being processed\r
  @param[in]  Context Event Context\r
**/\r
VOID\r
EFIAPI\r
ExitBootServicesEvent (\r
  IN EFI_EVENT  Event,\r
  IN VOID       *Context\r
  )\r
{\r
  // Disable all interrupts\r
  MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
  MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
  MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
\r
  // Add code here to disable all FIQs as debugger may have turned one on\r
}\r
\r
/**\r
  Register Handler for the specified interrupt source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
  @param Handler  Callback for interrupt. NULL to unregister\r
\r
  @retval EFI_SUCCESS Source was updated to support Handler.\r
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RegisterInterruptSource (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source,\r
  IN HARDWARE_INTERRUPT_HANDLER         Handler\r
  )\r
{\r
  if (Source > MAX_VECTOR) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  if ((MmioRead32 (INTCPS_ILR(Source)) & INTCPS_ILR_FIQ) == INTCPS_ILR_FIQ) {\r
    // This vector has been programmed as FIQ so we can't use it for IRQ\r
    // EFI does not use FIQ, but the debugger can use it to check for\r
    // ctrl-c. So this ASSERT means you have a conflict with the debug agent\r
    ASSERT (FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {\r
    return EFI_ALREADY_STARTED;\r
  }\r
\r
  gRegisteredInterruptHandlers[Source] = Handler;\r
  return This->EnableInterruptSource(This, Source);\r
}\r
\r
\r
/**\r
  Enable interrupt source Source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
\r
  @retval EFI_SUCCESS       Source interrupt enabled.\r
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EnableInterruptSource (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source\r
  )\r
{\r
  UINTN Bank;\r
  UINTN Bit;\r
\r
  if (Source > MAX_VECTOR) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  Bank = Source / 32;\r
  Bit  = 1UL << (Source % 32);\r
\r
  MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  Disable interrupt source Source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
\r
  @retval EFI_SUCCESS       Source interrupt disabled.\r
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DisableInterruptSource (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source\r
  )\r
{\r
  UINTN Bank;\r
  UINTN Bit;\r
\r
  if (Source > MAX_VECTOR) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  Bank = Source / 32;\r
  Bit  = 1UL << (Source % 32);\r
\r
  MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
\r
\r
/**\r
  Return current state of interrupt source Source.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
  @param InterruptState  TRUE: source enabled, FALSE: source disabled.\r
\r
  @retval EFI_SUCCESS       InterruptState is valid\r
  @retval EFI_DEVICE_ERROR  InterruptState is not valid\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
GetInterruptSourceState (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source,\r
  IN BOOLEAN                            *InterruptState\r
  )\r
{\r
  UINTN Bank;\r
  UINTN Bit;\r
\r
  if (InterruptState == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Source > MAX_VECTOR) {\r
    ASSERT(FALSE);\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  Bank = Source / 32;\r
  Bit  = 1UL << (Source % 32);\r
\r
  if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {\r
    *InterruptState = FALSE;\r
  } else {\r
    *InterruptState = TRUE;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Signal to the hardware that the End Of Intrrupt state\r
  has been reached.\r
\r
  @param This     Instance pointer for this protocol\r
  @param Source   Hardware source of the interrupt\r
\r
  @retval EFI_SUCCESS       Source interrupt EOI'ed.\r
  @retval EFI_DEVICE_ERROR  Hardware could not be programmed.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
EndOfInterrupt (\r
  IN EFI_HARDWARE_INTERRUPT_PROTOCOL    *This,\r
  IN HARDWARE_INTERRUPT_SOURCE          Source\r
  )\r
{\r
  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
  ArmDataSynchronizationBarrier ();\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
\r
  @param  InterruptType    Defines the type of interrupt or exception that\r
                           occurred on the processor.This parameter is processor architecture specific.\r
  @param  SystemContext    A pointer to the processor context when\r
                           the interrupt occurred on the processor.\r
\r
  @return None\r
\r
**/\r
VOID\r
EFIAPI\r
IrqInterruptHandler (\r
  IN EFI_EXCEPTION_TYPE           InterruptType,\r
  IN EFI_SYSTEM_CONTEXT           SystemContext\r
  )\r
{\r
  UINT32                     Vector;\r
  HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
\r
  Vector = MmioRead32 (INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;\r
\r
  // Needed to prevent infinite nesting when Time Driver lowers TPL\r
  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
  ArmDataSynchronizationBarrier ();\r
\r
  InterruptHandler = gRegisteredInterruptHandlers[Vector];\r
  if (InterruptHandler != NULL) {\r
    // Call the registered interrupt handler.\r
    InterruptHandler (Vector, SystemContext);\r
  }\r
\r
  // Needed to clear after running the handler\r
  MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
  ArmDataSynchronizationBarrier ();\r
}\r
\r
//\r
// Making this global saves a few bytes in image size\r
//\r
EFI_HANDLE  gHardwareInterruptHandle = NULL;\r
\r
//\r
// The protocol instance produced by this driver\r
//\r
EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {\r
  RegisterInterruptSource,\r
  EnableInterruptSource,\r
  DisableInterruptSource,\r
  GetInterruptSourceState,\r
  EndOfInterrupt\r
};\r
\r
/**\r
  Initialize the state information for the CPU Architectural Protocol\r
\r
  @param  ImageHandle   of the loaded driver\r
  @param  SystemTable   Pointer to the System Table\r
\r
  @retval EFI_SUCCESS           Protocol registered\r
  @retval EFI_OUT_OF_RESOURCES  Cannot allocate protocol data structure\r
  @retval EFI_DEVICE_ERROR      Hardware problems\r
\r
**/\r
EFI_STATUS\r
InterruptDxeInitialize (\r
  IN EFI_HANDLE         ImageHandle,\r
  IN EFI_SYSTEM_TABLE   *SystemTable\r
  )\r
{\r
  EFI_STATUS  Status;\r
  EFI_CPU_ARCH_PROTOCOL   *Cpu;\r
\r
  // Make sure the Interrupt Controller Protocol is not already installed in the system.\r
  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
\r
  // Make sure all interrupts are disabled by default.\r
  MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
  MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
  MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
  MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
\r
  Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,\r
                                                  &gHardwareInterruptProtocolGuid,   &gHardwareInterruptProtocol,\r
                                                  NULL);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  //\r
  // Get the CPU protocol that this driver requires.\r
  //\r
  Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  //\r
  // Unregister the default exception handler.\r
  //\r
  Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  //\r
  // Register to receive interrupts\r
  //\r
  Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  // Register for an ExitBootServicesEvent\r
  Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  return Status;\r
}\r
\r
Commit	Line	Data
a3f98646	1	/** @file\r
3402aac7	2	Handle OMAP35xx interrupt controller\r
a3f98646	3	\r
3d70643b	4	Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
3402aac7	5	\r
3d70643b	6	This program and the accompanying materials\r
a3f98646	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	#include <PiDxe.h>\r
	16	\r
	17	#include <Library/BaseLib.h>\r
	18	#include <Library/DebugLib.h>\r
	19	#include <Library/BaseMemoryLib.h>\r
	20	#include <Library/UefiBootServicesTableLib.h>\r
	21	#include <Library/UefiLib.h>\r
	22	#include <Library/PcdLib.h>\r
	23	#include <Library/IoLib.h>\r
026c3d34	24	#include <Library/ArmLib.h>\r
a3f98646	25	\r
	26	#include <Protocol/Cpu.h>\r
	27	#include <Protocol/HardwareInterrupt.h>\r
	28	\r
	29	#include <Omap3530/Omap3530.h>\r
	30	\r
	31	//\r
	32	// Notifications\r
	33	//\r
a3f98646	34	EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;\r
	35	\r
	36	\r
	37	HARDWARE_INTERRUPT_HANDLER gRegisteredInterruptHandlers[INT_NROF_VECTORS];\r
	38	\r
	39	/**\r
	40	Shutdown our hardware\r
3402aac7	41	\r
a3f98646	42	DXE Core will disable interrupts and turn off the timer and disable interrupts\r
	43	after all the event handlers have run.\r
	44	\r
	45	@param[in] Event The Event that is being processed\r
	46	@param[in] Context Event Context\r
	47	**/\r
	48	VOID\r
	49	EFIAPI\r
	50	ExitBootServicesEvent (\r
	51	IN EFI_EVENT Event,\r
	52	IN VOID *Context\r
	53	)\r
	54	{\r
	55	// Disable all interrupts\r
026e30c4	56	MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
	57	MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
	58	MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
	59	MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
43263288	60	\r
43263288	61	// Add code here to disable all FIQs as debugger may have turned one on\r
a3f98646	62	}\r
	63	\r
	64	/**\r
	65	Register Handler for the specified interrupt source.\r
	66	\r
	67	@param This Instance pointer for this protocol\r
	68	@param Source Hardware source of the interrupt\r
	69	@param Handler Callback for interrupt. NULL to unregister\r
	70	\r
	71	@retval EFI_SUCCESS Source was updated to support Handler.\r
	72	@retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
	73	\r
	74	**/\r
	75	EFI_STATUS\r
	76	EFIAPI\r
	77	RegisterInterruptSource (\r
	78	IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
	79	IN HARDWARE_INTERRUPT_SOURCE Source,\r
	80	IN HARDWARE_INTERRUPT_HANDLER Handler\r
	81	)\r
	82	{\r
	83	if (Source > MAX_VECTOR) {\r
	84	ASSERT(FALSE);\r
	85	return EFI_UNSUPPORTED;\r
3402aac7 RC	86	}\r
3402aac7 RC	87	\r
e9fc14b6	88	if ((MmioRead32 (INTCPS_ILR(Source)) & INTCPS_ILR_FIQ) == INTCPS_ILR_FIQ) {\r
e9fc14b6	89	// This vector has been programmed as FIQ so we can't use it for IRQ\r
3402aac7	90	// EFI does not use FIQ, but the debugger can use it to check for\r
e9fc14b6	91	// ctrl-c. So this ASSERT means you have a conflict with the debug agent\r
	92	ASSERT (FALSE);\r
	93	return EFI_UNSUPPORTED;\r
	94	}\r
3402aac7	95	\r
a3f98646	96	if ((Handler == NULL) && (gRegisteredInterruptHandlers[Source] == NULL)) {\r
	97	return EFI_INVALID_PARAMETER;\r
	98	}\r
	99	\r
	100	if ((Handler != NULL) && (gRegisteredInterruptHandlers[Source] != NULL)) {\r
	101	return EFI_ALREADY_STARTED;\r
	102	}\r
	103	\r
	104	gRegisteredInterruptHandlers[Source] = Handler;\r
	105	return This->EnableInterruptSource(This, Source);\r
	106	}\r
	107	\r
	108	\r
	109	/**\r
	110	Enable interrupt source Source.\r
	111	\r
	112	@param This Instance pointer for this protocol\r
	113	@param Source Hardware source of the interrupt\r
	114	\r
	115	@retval EFI_SUCCESS Source interrupt enabled.\r
	116	@retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
	117	\r
	118	**/\r
	119	EFI_STATUS\r
	120	EFIAPI\r
	121	EnableInterruptSource (\r
	122	IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
	123	IN HARDWARE_INTERRUPT_SOURCE Source\r
	124	)\r
	125	{\r
	126	UINTN Bank;\r
	127	UINTN Bit;\r
3402aac7	128	\r
a3f98646	129	if (Source > MAX_VECTOR) {\r
	130	ASSERT(FALSE);\r
	131	return EFI_UNSUPPORTED;\r
	132	}\r
3402aac7	133	\r
a3f98646	134	Bank = Source / 32;\r
a3f98646	135	Bit = 1UL << (Source % 32);\r
3402aac7	136	\r
026e30c4	137	MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);\r
3402aac7	138	\r
a3f98646	139	return EFI_SUCCESS;\r
	140	}\r
	141	\r
	142	\r
	143	/**\r
	144	Disable interrupt source Source.\r
	145	\r
	146	@param This Instance pointer for this protocol\r
	147	@param Source Hardware source of the interrupt\r
	148	\r
	149	@retval EFI_SUCCESS Source interrupt disabled.\r
	150	@retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
	151	\r
	152	**/\r
	153	EFI_STATUS\r
	154	EFIAPI\r
026c3d34	155	DisableInterruptSource (\r
a3f98646	156	IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
	157	IN HARDWARE_INTERRUPT_SOURCE Source\r
	158	)\r
	159	{\r
	160	UINTN Bank;\r
	161	UINTN Bit;\r
3402aac7	162	\r
a3f98646	163	if (Source > MAX_VECTOR) {\r
	164	ASSERT(FALSE);\r
	165	return EFI_UNSUPPORTED;\r
	166	}\r
3402aac7	167	\r
a3f98646	168	Bank = Source / 32;\r
a3f98646	169	Bit = 1UL << (Source % 32);\r
3402aac7	170	\r
026e30c4	171	MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);\r
3402aac7	172	\r
a3f98646	173	return EFI_SUCCESS;\r
	174	}\r
	175	\r
	176	\r
	177	\r
	178	/**\r
	179	Return current state of interrupt source Source.\r
	180	\r
	181	@param This Instance pointer for this protocol\r
	182	@param Source Hardware source of the interrupt\r
	183	@param InterruptState TRUE: source enabled, FALSE: source disabled.\r
	184	\r
	185	@retval EFI_SUCCESS InterruptState is valid\r
	186	@retval EFI_DEVICE_ERROR InterruptState is not valid\r
	187	\r
	188	**/\r
	189	EFI_STATUS\r
	190	EFIAPI\r
	191	GetInterruptSourceState (\r
	192	IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
	193	IN HARDWARE_INTERRUPT_SOURCE Source,\r
	194	IN BOOLEAN *InterruptState\r
	195	)\r
	196	{\r
	197	UINTN Bank;\r
	198	UINTN Bit;\r
3402aac7	199	\r
a3f98646	200	if (InterruptState == NULL) {\r
	201	return EFI_INVALID_PARAMETER;\r
	202	}\r
3402aac7	203	\r
a3f98646	204	if (Source > MAX_VECTOR) {\r
	205	ASSERT(FALSE);\r
	206	return EFI_UNSUPPORTED;\r
	207	}\r
	208	\r
	209	Bank = Source / 32;\r
	210	Bit = 1UL << (Source % 32);\r
3402aac7	211	\r
e9fc14b6	212	if ((MmioRead32(INTCPS_MIR(Bank)) & Bit) == Bit) {\r
a3f98646	213	*InterruptState = FALSE;\r
	214	} else {\r
	215	*InterruptState = TRUE;\r
	216	}\r
3402aac7	217	\r
a3f98646	218	return EFI_SUCCESS;\r
	219	}\r
	220	\r
026c3d34	221	/**\r
3402aac7	222	Signal to the hardware that the End Of Intrrupt state\r
026c3d34	223	has been reached.\r
	224	\r
	225	@param This Instance pointer for this protocol\r
	226	@param Source Hardware source of the interrupt\r
	227	\r
	228	@retval EFI_SUCCESS Source interrupt EOI'ed.\r
	229	@retval EFI_DEVICE_ERROR Hardware could not be programmed.\r
	230	\r
	231	**/\r
	232	EFI_STATUS\r
	233	EFIAPI\r
	234	EndOfInterrupt (\r
	235	IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,\r
	236	IN HARDWARE_INTERRUPT_SOURCE Source\r
	237	)\r
	238	{\r
	239	MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
cf93a378	240	ArmDataSynchronizationBarrier ();\r
026c3d34	241	return EFI_SUCCESS;\r
026c3d34	242	}\r
a3f98646	243	\r
	244	\r
	245	/**\r
	246	EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
	247	\r
	248	@param InterruptType Defines the type of interrupt or exception that\r
	249	occurred on the processor.This parameter is processor architecture specific.\r
	250	@param SystemContext A pointer to the processor context when\r
	251	the interrupt occurred on the processor.\r
	252	\r
	253	@return None\r
	254	\r
	255	**/\r
	256	VOID\r
	257	EFIAPI\r
	258	IrqInterruptHandler (\r
	259	IN EFI_EXCEPTION_TYPE InterruptType,\r
	260	IN EFI_SYSTEM_CONTEXT SystemContext\r
	261	)\r
	262	{\r
	263	UINT32 Vector;\r
	264	HARDWARE_INTERRUPT_HANDLER InterruptHandler;\r
3402aac7	265	\r
026c3d34	266	Vector = MmioRead32 (INTCPS_SIR_IRQ) & INTCPS_SIR_IRQ_MASK;\r
a3f98646	267	\r
a3f98646	268	// Needed to prevent infinite nesting when Time Driver lowers TPL\r
026e30c4	269	MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
cf93a378	270	ArmDataSynchronizationBarrier ();\r
3402aac7	271	\r
a3f98646	272	InterruptHandler = gRegisteredInterruptHandlers[Vector];\r
	273	if (InterruptHandler != NULL) {\r
	274	// Call the registered interrupt handler.\r
026c3d34	275	InterruptHandler (Vector, SystemContext);\r
a3f98646	276	}\r
3402aac7	277	\r
a3f98646	278	// Needed to clear after running the handler\r
026e30c4	279	MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
cf93a378	280	ArmDataSynchronizationBarrier ();\r
a3f98646	281	}\r
	282	\r
	283	//\r
	284	// Making this global saves a few bytes in image size\r
	285	//\r
	286	EFI_HANDLE gHardwareInterruptHandle = NULL;\r
	287	\r
	288	//\r
	289	// The protocol instance produced by this driver\r
	290	//\r
	291	EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = {\r
	292	RegisterInterruptSource,\r
	293	EnableInterruptSource,\r
	294	DisableInterruptSource,\r
026c3d34	295	GetInterruptSourceState,\r
026c3d34	296	EndOfInterrupt\r
a3f98646	297	};\r
a3f98646	298	\r
a3f98646	299	/**\r
	300	Initialize the state information for the CPU Architectural Protocol\r
	301	\r
	302	@param ImageHandle of the loaded driver\r
	303	@param SystemTable Pointer to the System Table\r
	304	\r
	305	@retval EFI_SUCCESS Protocol registered\r
	306	@retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure\r
	307	@retval EFI_DEVICE_ERROR Hardware problems\r
	308	\r
	309	**/\r
	310	EFI_STATUS\r
	311	InterruptDxeInitialize (\r
	312	IN EFI_HANDLE ImageHandle,\r
	313	IN EFI_SYSTEM_TABLE *SystemTable\r
	314	)\r
	315	{\r
	316	EFI_STATUS Status;\r
d326412c	317	EFI_CPU_ARCH_PROTOCOL *Cpu;\r
a3f98646	318	\r
	319	// Make sure the Interrupt Controller Protocol is not already installed in the system.\r
	320	ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);\r
	321	\r
	322	// Make sure all interrupts are disabled by default.\r
026e30c4	323	MmioWrite32 (INTCPS_MIR(0), 0xFFFFFFFF);\r
	324	MmioWrite32 (INTCPS_MIR(1), 0xFFFFFFFF);\r
	325	MmioWrite32 (INTCPS_MIR(2), 0xFFFFFFFF);\r
41d47802	326	MmioOr32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWIRQAGR);\r
3402aac7	327	\r
a3f98646	328	Status = gBS->InstallMultipleProtocolInterfaces(&gHardwareInterruptHandle,\r
	329	&gHardwareInterruptProtocolGuid, &gHardwareInterruptProtocol,\r
	330	NULL);\r
	331	ASSERT_EFI_ERROR(Status);\r
3402aac7	332	\r
d326412c	333	//\r
	334	// Get the CPU protocol that this driver requires.\r
	335	//\r
	336	Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
a3f98646	337	ASSERT_EFI_ERROR(Status);\r
a3f98646	338	\r
d326412c	339	//\r
	340	// Unregister the default exception handler.\r
	341	//\r
	342	Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, NULL);\r
	343	ASSERT_EFI_ERROR(Status);\r
	344	\r
	345	//\r
	346	// Register to receive interrupts\r
	347	//\r
	348	Status = Cpu->RegisterInterruptHandler(Cpu, EXCEPT_ARM_IRQ, IrqInterruptHandler);\r
a3f98646	349	ASSERT_EFI_ERROR(Status);\r
	350	\r
	351	// Register for an ExitBootServicesEvent\r
	352	Status = gBS->CreateEvent(EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, ExitBootServicesEvent, NULL, &EfiExitBootServicesEvent);\r
	353	ASSERT_EFI_ERROR(Status);\r
	354	\r
	355	return Status;\r
	356	}\r
	357	\r