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51ebae6b | 1 | /** @file\r |
2 | Definitions for network adapter card.\r | |
3 | \r | |
ac1ca104 HT |
4 | Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>\r |
5 | This program and the accompanying materials\r | |
51ebae6b | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef _E100B_H_\r | |
16 | #define _E100B_H_\r | |
17 | \r | |
18 | // pci config offsets:\r | |
19 | \r | |
20 | #define RX_BUFFER_COUNT 32\r | |
21 | #define TX_BUFFER_COUNT 32\r | |
22 | \r | |
23 | #define PCI_VENDOR_ID_INTEL 0x8086\r | |
24 | #define PCI_DEVICE_ID_INTEL_82557 0x1229\r | |
25 | #define D100_VENDOR_ID 0x8086\r | |
26 | #define D100_DEVICE_ID 0x1229\r | |
27 | #define D102_DEVICE_ID 0x2449\r | |
28 | \r | |
29 | #define ICH3_DEVICE_ID_1 0x1031\r | |
30 | #define ICH3_DEVICE_ID_2 0x1032\r | |
31 | #define ICH3_DEVICE_ID_3 0x1033\r | |
32 | #define ICH3_DEVICE_ID_4 0x1034\r | |
33 | #define ICH3_DEVICE_ID_5 0x1035\r | |
34 | #define ICH3_DEVICE_ID_6 0x1036\r | |
35 | #define ICH3_DEVICE_ID_7 0x1037\r | |
36 | #define ICH3_DEVICE_ID_8 0x1038\r | |
37 | \r | |
38 | #define SPEEDO_DEVICE_ID 0x1227\r | |
39 | #define SPLASH1_DEVICE_ID 0x1226\r | |
40 | \r | |
41 | \r | |
42 | // bit fields for the command\r | |
43 | #define PCI_COMMAND_MASTER 0x04 // bit 2\r | |
44 | #define PCI_COMMAND_IO 0x01 // bit 0\r | |
45 | #define PCI_COMMAND 0x04\r | |
46 | #define PCI_LATENCY_TIMER 0x0D\r | |
47 | \r | |
48 | #define ETHER_MAC_ADDR_LEN 6\r | |
49 | #ifdef AVL_XXX\r | |
50 | #define ETHER_HEADER_LEN 14\r | |
51 | // media interface type\r | |
52 | // #define INTERFACE_TYPE "\r | |
53 | \r | |
54 | // Hardware type values\r | |
55 | #define HW_ETHER_TYPE 1\r | |
56 | #define HW_EXPERIMENTAL_ETHER_TYPE 2\r | |
57 | #define HW_IEEE_TYPE 6\r | |
58 | #define HW_ARCNET_TYPE 7\r | |
59 | \r | |
60 | #endif // AVL_XXX\r | |
61 | \r | |
62 | #define MAX_ETHERNET_PKT_SIZE 1514 // including eth header\r | |
63 | #define RX_BUFFER_SIZE 1536 // including crc and padding\r | |
64 | #define TX_BUFFER_SIZE 64\r | |
65 | #define ETH_MTU 1500 // does not include ethernet header length\r | |
66 | \r | |
67 | #define SPEEDO3_TOTAL_SIZE 0x20\r | |
68 | \r | |
69 | #pragma pack(1)\r | |
70 | \r | |
71 | typedef struct eth {\r | |
72 | UINT8 dest_addr[PXE_HWADDR_LEN_ETHER];\r | |
73 | UINT8 src_addr[PXE_HWADDR_LEN_ETHER];\r | |
74 | UINT16 type;\r | |
75 | } EtherHeader;\r | |
76 | \r | |
77 | #pragma pack(1)\r | |
78 | typedef struct CONFIG_HEADER {\r | |
79 | UINT16 VendorID;\r | |
80 | UINT16 DeviceID;\r | |
81 | UINT16 Command;\r | |
82 | UINT16 Status;\r | |
83 | UINT16 RevID;\r | |
84 | UINT16 ClassID;\r | |
85 | UINT8 CacheLineSize;\r | |
86 | UINT8 LatencyTimer;\r | |
87 | UINT8 HeaderType; // must be zero to impose this structure...\r | |
88 | UINT8 BIST; // built-in self test\r | |
89 | UINT32 BaseAddressReg_0; // memory mapped address\r | |
90 | UINT32 BaseAddressReg_1; //io mapped address, Base IO address\r | |
91 | UINT32 BaseAddressReg_2; // option rom address\r | |
92 | UINT32 BaseAddressReg_3;\r | |
93 | UINT32 BaseAddressReg_4;\r | |
94 | UINT32 BaseAddressReg_5;\r | |
95 | UINT32 CardBusCISPtr;\r | |
96 | UINT16 SubVendorID;\r | |
97 | UINT16 SubSystemID;\r | |
98 | UINT32 ExpansionROMBaseAddr;\r | |
99 | UINT8 CapabilitiesPtr;\r | |
100 | UINT8 reserved1;\r | |
101 | UINT16 Reserved2;\r | |
102 | UINT32 Reserved3;\r | |
103 | UINT8 int_line;\r | |
104 | UINT8 int_pin;\r | |
105 | UINT8 Min_gnt;\r | |
106 | UINT8 Max_lat;\r | |
107 | } PCI_CONFIG_HEADER;\r | |
108 | #pragma pack()\r | |
109 | \r | |
110 | //-------------------------------------------------------------------------\r | |
111 | // Offsets to the various registers.\r | |
112 | // All accesses need not be longword aligned.\r | |
113 | //-------------------------------------------------------------------------\r | |
114 | enum speedo_offsets {\r | |
115 | SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status.\r | |
116 | SCBPointer = 4, // General purpose pointer.\r | |
117 | SCBPort = 8, // Misc. commands and operands.\r | |
118 | SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.\r | |
119 | SCBCtrlMDI = 16, // MDI interface control.\r | |
120 | SCBEarlyRx = 20, // Early receive byte count.\r | |
121 | SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,\r | |
122 | // offsets for general control registers (GCRs)\r | |
123 | SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31\r | |
124 | };\r | |
125 | \r | |
126 | #define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2\r | |
127 | \r | |
128 | //-------------------------------------------------------------------------\r | |
129 | // Action commands - Commands that can be put in a command list entry.\r | |
130 | //-------------------------------------------------------------------------\r | |
131 | enum commands {\r | |
132 | CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,\r | |
133 | CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7,\r | |
134 | CmdSuspend = 0x4000, /* Suspend after completion. */\r | |
135 | CmdIntr = 0x2000, /* Interrupt after completion. */\r | |
136 | CmdTxFlex = 0x0008 /* Use "Flexible mode" for CmdTx command. */\r | |
137 | };\r | |
138 | \r | |
139 | //-------------------------------------------------------------------------\r | |
140 | // port commands\r | |
141 | //-------------------------------------------------------------------------\r | |
142 | #define PORT_RESET 0\r | |
143 | #define PORT_SELF_TEST 1\r | |
144 | #define POR_SELECTIVE_RESET 2\r | |
145 | #define PORT_DUMP_POINTER 2\r | |
146 | \r | |
147 | //-------------------------------------------------------------------------\r | |
148 | // SCB Command Word bit definitions\r | |
149 | //-------------------------------------------------------------------------\r | |
150 | //- CUC fields\r | |
151 | #define CU_START 0x0010\r | |
152 | #define CU_RESUME 0x0020\r | |
153 | #define CU_STATSADDR 0x0040\r | |
154 | #define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */\r | |
155 | #define CU_CMD_BASE 0x0060 /* Base address to add to add CU commands. */\r | |
156 | #define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */\r | |
157 | \r | |
158 | //- RUC fields\r | |
159 | #define RX_START 0x0001\r | |
160 | #define RX_RESUME 0x0002\r | |
161 | #define RX_ABORT 0x0004\r | |
162 | #define RX_ADDR_LOAD 0x0006 /* load ru_base_reg */\r | |
163 | #define RX_RESUMENR 0x0007\r | |
164 | \r | |
165 | // Interrupt fields (assuming byte addressing)\r | |
166 | #define INT_MASK 0x0100\r | |
167 | #define DRVR_INT 0x0200 /* Driver generated interrupt. */\r | |
168 | \r | |
169 | //- CB Status Word\r | |
170 | #define CMD_STATUS_COMPLETE 0x8000\r | |
171 | #define RX_STATUS_COMPLETE 0x8000\r | |
172 | #define CMD_STATUS_MASK 0xF000\r | |
173 | \r | |
174 | //-------------------------------------------------------------------------\r | |
175 | //- SCB Status bits:\r | |
176 | // Interrupts are ACKed by writing to the upper 6 interrupt bits\r | |
177 | //-------------------------------------------------------------------------\r | |
178 | #define SCB_STATUS_MASK 0xFC00 // bits 2-7 - STATUS/ACK Mask\r | |
179 | #define SCB_STATUS_CX_TNO 0x8000 // BIT_15 - CX or TNO Interrupt\r | |
180 | #define SCB_STATUS_FR 0x4000 // BIT_14 - FR Interrupt\r | |
181 | #define SCB_STATUS_CNA 0x2000 // BIT_13 - CNA Interrupt\r | |
182 | #define SCB_STATUS_RNR 0x1000 // BIT_12 - RNR Interrupt\r | |
183 | #define SCB_STATUS_MDI 0x0800 // BIT_11 - MDI R/W Done Interrupt\r | |
184 | #define SCB_STATUS_SWI 0x0400 // BIT_10 - SWI Interrupt\r | |
185 | \r | |
186 | // CU STATUS: bits 6 & 7\r | |
187 | #define SCB_STATUS_CU_MASK 0x00C0 // bits 6 & 7\r | |
188 | #define SCB_STATUS_CU_IDLE 0x0000 // 00\r | |
189 | #define SCB_STATUS_CU_SUSPEND 0x0040 // 01\r | |
190 | #define SCB_STATUS_CU_ACTIVE 0x0080 // 10\r | |
191 | \r | |
192 | // RU STATUS: bits 2-5\r | |
193 | #define SCB_RUS_IDLE 0x0000\r | |
194 | #define SCB_RUS_SUSPENDED 0x0004 // bit 2\r | |
195 | #define SCB_RUS_NO_RESOURCES 0x0008 // bit 3\r | |
196 | #define SCB_RUS_READY 0x0010 // bit 4\r | |
197 | \r | |
198 | //-------------------------------------------------------------------------\r | |
199 | // Bit Mask definitions\r | |
200 | //-------------------------------------------------------------------------\r | |
201 | #define BIT_0 0x0001\r | |
202 | #define BIT_1 0x0002\r | |
203 | #define BIT_2 0x0004\r | |
204 | #define BIT_3 0x0008\r | |
205 | #define BIT_4 0x0010\r | |
206 | #define BIT_5 0x0020\r | |
207 | #define BIT_6 0x0040\r | |
208 | #define BIT_7 0x0080\r | |
209 | #define BIT_8 0x0100\r | |
210 | #define BIT_9 0x0200\r | |
211 | #define BIT_10 0x0400\r | |
212 | #define BIT_11 0x0800\r | |
213 | #define BIT_12 0x1000\r | |
214 | #define BIT_13 0x2000\r | |
215 | #define BIT_14 0x4000\r | |
216 | #define BIT_15 0x8000\r | |
217 | #define BIT_24 0x01000000\r | |
218 | #define BIT_28 0x10000000\r | |
219 | \r | |
220 | \r | |
221 | //-------------------------------------------------------------------------\r | |
222 | // MDI Control register bit definitions\r | |
223 | //-------------------------------------------------------------------------\r | |
224 | #define MDI_DATA_MASK BIT_0_15 // MDI Data port\r | |
225 | #define MDI_REG_ADDR BIT_16_20 // which MDI register to read/write\r | |
226 | #define MDI_PHY_ADDR BIT_21_25 // which PHY to read/write\r | |
227 | #define MDI_PHY_OPCODE BIT_26_27 // which PHY to read/write\r | |
228 | #define MDI_PHY_READY BIT_28 // PHY is ready for another MDI cycle\r | |
229 | #define MDI_PHY_INT_ENABLE BIT_29 // Assert INT at MDI cycle completion\r | |
230 | \r | |
231 | #define BIT_0_2 0x0007\r | |
232 | #define BIT_0_3 0x000F\r | |
233 | #define BIT_0_4 0x001F\r | |
234 | #define BIT_0_5 0x003F\r | |
235 | #define BIT_0_6 0x007F\r | |
236 | #define BIT_0_7 0x00FF\r | |
237 | #define BIT_0_8 0x01FF\r | |
238 | #define BIT_0_13 0x3FFF\r | |
239 | #define BIT_0_15 0xFFFF\r | |
240 | #define BIT_1_2 0x0006\r | |
241 | #define BIT_1_3 0x000E\r | |
242 | #define BIT_2_5 0x003C\r | |
243 | #define BIT_3_4 0x0018\r | |
244 | #define BIT_4_5 0x0030\r | |
245 | #define BIT_4_6 0x0070\r | |
246 | #define BIT_4_7 0x00F0\r | |
247 | #define BIT_5_7 0x00E0\r | |
248 | #define BIT_5_9 0x03E0\r | |
249 | #define BIT_5_12 0x1FE0\r | |
250 | #define BIT_5_15 0xFFE0\r | |
251 | #define BIT_6_7 0x00c0\r | |
252 | #define BIT_7_11 0x0F80\r | |
253 | #define BIT_8_10 0x0700\r | |
254 | #define BIT_9_13 0x3E00\r | |
255 | #define BIT_12_15 0xF000\r | |
256 | \r | |
257 | #define BIT_16_20 0x001F0000\r | |
258 | #define BIT_21_25 0x03E00000\r | |
259 | #define BIT_26_27 0x0C000000\r | |
260 | \r | |
261 | //-------------------------------------------------------------------------\r | |
262 | // MDI Control register opcode definitions\r | |
263 | //-------------------------------------------------------------------------\r | |
264 | #define MDI_WRITE 1 // Phy Write\r | |
265 | #define MDI_READ 2 // Phy read\r | |
266 | \r | |
267 | //-------------------------------------------------------------------------\r | |
268 | // PHY 100 MDI Register/Bit Definitions\r | |
269 | //-------------------------------------------------------------------------\r | |
270 | // MDI register set\r | |
271 | #define MDI_CONTROL_REG 0x00 // MDI control register\r | |
272 | #define MDI_STATUS_REG 0x01 // MDI Status regiser\r | |
273 | #define PHY_ID_REG_1 0x02 // Phy indentification reg (word 1)\r | |
274 | #define PHY_ID_REG_2 0x03 // Phy indentification reg (word 2)\r | |
275 | #define AUTO_NEG_ADVERTISE_REG 0x04 // Auto-negotiation advertisement\r | |
276 | #define AUTO_NEG_LINK_PARTNER_REG 0x05 // Auto-negotiation link partner ability\r | |
277 | #define AUTO_NEG_EXPANSION_REG 0x06 // Auto-negotiation expansion\r | |
278 | #define AUTO_NEG_NEXT_PAGE_REG 0x07 // Auto-negotiation next page transmit\r | |
279 | #define EXTENDED_REG_0 0x10 // Extended reg 0 (Phy 100 modes)\r | |
280 | #define EXTENDED_REG_1 0x14 // Extended reg 1 (Phy 100 error indications)\r | |
281 | #define NSC_CONG_CONTROL_REG 0x17 // National (TX) congestion control\r | |
282 | #define NSC_SPEED_IND_REG 0x19 // National (TX) speed indication\r | |
283 | \r | |
284 | // MDI Control register bit definitions\r | |
285 | #define MDI_CR_COLL_TEST_ENABLE BIT_7 // Collision test enable\r | |
286 | #define MDI_CR_FULL_HALF BIT_8 // FDX =1, half duplex =0\r | |
287 | #define MDI_CR_RESTART_AUTO_NEG BIT_9 // Restart auto negotiation\r | |
288 | #define MDI_CR_ISOLATE BIT_10 // Isolate PHY from MII\r | |
289 | #define MDI_CR_POWER_DOWN BIT_11 // Power down\r | |
290 | #define MDI_CR_AUTO_SELECT BIT_12 // Auto speed select enable\r | |
291 | #define MDI_CR_10_100 BIT_13 // 0 = 10Mbs, 1 = 100Mbs\r | |
292 | #define MDI_CR_LOOPBACK BIT_14 // 0 = normal, 1 = loopback\r | |
293 | #define MDI_CR_RESET BIT_15 // 0 = normal, 1 = PHY reset\r | |
294 | \r | |
295 | // MDI Status register bit definitions\r | |
296 | #define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities\r | |
297 | #define MDI_SR_JABBER_DETECT BIT_1 // Jabber detected\r | |
298 | #define MDI_SR_LINK_STATUS BIT_2 // Link Status -- 1 = link\r | |
299 | #define MDI_SR_AUTO_SELECT_CAPABLE BIT_3 // Auto speed select capable\r | |
300 | #define MDI_SR_REMOTE_FAULT_DETECT BIT_4 // Remote fault detect\r | |
301 | #define MDI_SR_AUTO_NEG_COMPLETE BIT_5 // Auto negotiation complete\r | |
302 | #define MDI_SR_10T_HALF_DPX BIT_11 // 10BaseT Half Duplex capable\r | |
303 | #define MDI_SR_10T_FULL_DPX BIT_12 // 10BaseT full duplex capable\r | |
304 | #define MDI_SR_TX_HALF_DPX BIT_13 // TX Half Duplex capable\r | |
305 | #define MDI_SR_TX_FULL_DPX BIT_14 // TX full duplex capable\r | |
306 | #define MDI_SR_T4_CAPABLE BIT_15 // T4 capable\r | |
307 | \r | |
308 | // Auto-Negotiation advertisement register bit definitions\r | |
309 | #define NWAY_AD_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r | |
310 | #define NWAY_AD_ABILITY BIT_5_12 // technologies that are supported\r | |
311 | #define NWAY_AD_10T_HALF_DPX BIT_5 // 10BaseT Half Duplex capable\r | |
312 | #define NWAY_AD_10T_FULL_DPX BIT_6 // 10BaseT full duplex capable\r | |
313 | #define NWAY_AD_TX_HALF_DPX BIT_7 // TX Half Duplex capable\r | |
314 | #define NWAY_AD_TX_FULL_DPX BIT_8 // TX full duplex capable\r | |
315 | #define NWAY_AD_T4_CAPABLE BIT_9 // T4 capable\r | |
316 | #define NWAY_AD_REMOTE_FAULT BIT_13 // indicates local remote fault\r | |
317 | #define NWAY_AD_RESERVED BIT_14 // reserved\r | |
318 | #define NWAY_AD_NEXT_PAGE BIT_15 // Next page (not supported)\r | |
319 | \r | |
320 | // Auto-Negotiation link partner ability register bit definitions\r | |
321 | #define NWAY_LP_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r | |
322 | #define NWAY_LP_ABILITY BIT_5_9 // technologies that are supported\r | |
323 | #define NWAY_LP_REMOTE_FAULT BIT_13 // indicates partner remote fault\r | |
324 | #define NWAY_LP_ACKNOWLEDGE BIT_14 // acknowledge\r | |
325 | #define NWAY_LP_NEXT_PAGE BIT_15 // Next page (not supported)\r | |
326 | \r | |
327 | // Auto-Negotiation expansion register bit definitions\r | |
328 | #define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY\r | |
329 | #define NWAY_EX_PAGE_RECEIVED BIT_1 // link code word received\r | |
330 | #define NWAY_EX_NEXT_PAGE_ABLE BIT_2 // local is next page able\r | |
331 | #define NWAY_EX_LP_NEXT_PAGE_ABLE BIT_3 // partner is next page able\r | |
332 | #define NWAY_EX_PARALLEL_DET_FLT BIT_4 // parallel detection fault\r | |
333 | #define NWAY_EX_RESERVED BIT_5_15 // reserved\r | |
334 | \r | |
335 | \r | |
336 | // PHY 100 Extended Register 0 bit definitions\r | |
337 | #define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex\r | |
338 | #define PHY_100_ER0_SPEED_INDIC BIT_1 // 1 = 100mbs, 0= 10mbs\r | |
339 | #define PHY_100_ER0_WAKE_UP BIT_2 // Wake up DAC\r | |
340 | #define PHY_100_ER0_RESERVED BIT_3_4 // Reserved\r | |
341 | #define PHY_100_ER0_REV_CNTRL BIT_5_7 // Revsion control (A step = 000)\r | |
342 | #define PHY_100_ER0_FORCE_FAIL BIT_8 // Force Fail is enabled\r | |
343 | #define PHY_100_ER0_TEST BIT_9_13 // Revsion control (A step = 000)\r | |
344 | #define PHY_100_ER0_LINKDIS BIT_14 // Link integrity test is disabled\r | |
345 | #define PHY_100_ER0_JABDIS BIT_15 // Jabber function is disabled\r | |
346 | \r | |
347 | \r | |
348 | // PHY 100 Extended Register 1 bit definitions\r | |
349 | #define PHY_100_ER1_RESERVED BIT_0_8 // Reserved\r | |
350 | #define PHY_100_ER1_CH2_DET_ERR BIT_9 // Channel 2 EOF detection error\r | |
351 | #define PHY_100_ER1_MANCH_CODE_ERR BIT_10 // Manchester code error\r | |
352 | #define PHY_100_ER1_EOP_ERR BIT_11 // EOP error\r | |
353 | #define PHY_100_ER1_BAD_CODE_ERR BIT_12 // bad code error\r | |
354 | #define PHY_100_ER1_INV_CODE_ERR BIT_13 // invalid code error\r | |
355 | #define PHY_100_ER1_DC_BAL_ERR BIT_14 // DC balance error\r | |
356 | #define PHY_100_ER1_PAIR_SKEW_ERR BIT_15 // Pair skew error\r | |
357 | \r | |
358 | // National Semiconductor TX phy congestion control register bit definitions\r | |
359 | #define NSC_TX_CONG_TXREADY BIT_10 // Makes TxReady an input\r | |
360 | #define NSC_TX_CONG_ENABLE BIT_8 // Enables congestion control\r | |
361 | #define NSC_TX_CONG_F_CONNECT BIT_5 // Enables congestion control\r | |
362 | \r | |
363 | // National Semiconductor TX phy speed indication register bit definitions\r | |
364 | #define NSC_TX_SPD_INDC_SPEED BIT_6 // 0 = 100mb, 1=10mb\r | |
365 | \r | |
366 | //-------------------------------------------------------------------------\r | |
367 | // Phy related constants\r | |
368 | //-------------------------------------------------------------------------\r | |
369 | #define PHY_503 0\r | |
370 | #define PHY_100_A 0x000003E0\r | |
371 | #define PHY_100_C 0x035002A8\r | |
372 | #define PHY_TX_ID 0x015002A8\r | |
373 | #define PHY_NSC_TX 0x5c002000\r | |
374 | #define PHY_OTHER 0xFFFF\r | |
375 | \r | |
376 | #define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF\r | |
377 | #define PARALLEL_DETECT 0\r | |
378 | #define N_WAY 1\r | |
379 | \r | |
380 | #define RENEGOTIATE_TIME 35 // (3.5 Seconds)\r | |
381 | \r | |
382 | #define CONNECTOR_AUTO 0\r | |
383 | #define CONNECTOR_TPE 1\r | |
384 | #define CONNECTOR_MII 2\r | |
385 | \r | |
386 | //-------------------------------------------------------------------------\r | |
387 | \r | |
388 | /* The Speedo3 Rx and Tx frame/buffer descriptors. */\r | |
389 | #pragma pack(1)\r | |
390 | struct CB_Header { /* A generic descriptor. */\r | |
391 | UINT16 status; /* Offset 0. */\r | |
392 | UINT16 command; /* Offset 2. */\r | |
393 | UINT32 link; /* struct descriptor * */\r | |
394 | };\r | |
395 | \r | |
396 | /* transmit command block structure */\r | |
397 | #pragma pack(1)\r | |
398 | typedef struct s_TxCB {\r | |
399 | struct CB_Header cb_header;\r | |
400 | UINT32 PhysTBDArrayAddres; /* address of an array that contains\r | |
401 | physical TBD pointers */\r | |
402 | UINT16 ByteCount; /* immediate data count = 0 always */\r | |
403 | UINT8 Threshold;\r | |
404 | UINT8 TBDCount;\r | |
405 | UINT8 ImmediateData[TX_BUFFER_SIZE];\r | |
406 | /* following fields are not seen by the 82557 */\r | |
407 | struct TBD {\r | |
408 | UINT32 phys_buf_addr;\r | |
409 | UINT32 buf_len;\r | |
410 | } TBDArray[MAX_XMIT_FRAGMENTS];\r | |
411 | UINT32 PhysArrayAddr; /* in case the one in the header is lost */\r | |
412 | UINT32 PhysTCBAddress; /* for this TCB */\r | |
413 | struct s_TxCB *NextTCBVirtualLinkPtr;\r | |
414 | struct s_TxCB *PrevTCBVirtualLinkPtr;\r | |
415 | UINT64 free_data_ptr; // to be given to the upper layer when this xmit completes1\r | |
416 | }TxCB;\r | |
417 | \r | |
418 | /* The Speedo3 Rx and Tx buffer descriptors. */\r | |
419 | #pragma pack(1)\r | |
420 | typedef struct s_RxFD { /* Receive frame descriptor. */\r | |
421 | struct CB_Header cb_header;\r | |
422 | UINT32 rx_buf_addr; /* VOID * */\r | |
423 | UINT16 ActualCount;\r | |
424 | UINT16 RFDSize;\r | |
425 | UINT8 RFDBuffer[RX_BUFFER_SIZE];\r | |
426 | UINT8 forwarded;\r | |
427 | UINT8 junk[3];\r | |
428 | }RxFD;\r | |
429 | \r | |
430 | /* Elements of the RxFD.status word. */\r | |
431 | #define RX_COMPLETE 0x8000\r | |
432 | #define RX_FRAME_OK 0x2000\r | |
433 | \r | |
434 | /* Elements of the dump_statistics block. This block must be lword aligned. */\r | |
435 | #pragma pack(1)\r | |
436 | struct speedo_stats {\r | |
437 | UINT32 tx_good_frames;\r | |
438 | UINT32 tx_coll16_errs;\r | |
439 | UINT32 tx_late_colls;\r | |
440 | UINT32 tx_underruns;\r | |
441 | UINT32 tx_lost_carrier;\r | |
442 | UINT32 tx_deferred;\r | |
443 | UINT32 tx_one_colls;\r | |
444 | UINT32 tx_multi_colls;\r | |
445 | UINT32 tx_total_colls;\r | |
446 | UINT32 rx_good_frames;\r | |
447 | UINT32 rx_crc_errs;\r | |
448 | UINT32 rx_align_errs;\r | |
449 | UINT32 rx_resource_errs;\r | |
450 | UINT32 rx_overrun_errs;\r | |
451 | UINT32 rx_colls_errs;\r | |
452 | UINT32 rx_runt_errs;\r | |
453 | UINT32 done_marker;\r | |
454 | };\r | |
455 | #pragma pack()\r | |
456 | \r | |
457 | \r | |
458 | struct Krn_Mem{\r | |
459 | RxFD rx_ring[RX_BUFFER_COUNT];\r | |
460 | TxCB tx_ring[TX_BUFFER_COUNT];\r | |
461 | struct speedo_stats statistics;\r | |
462 | };\r | |
463 | #define MEMORY_NEEDED sizeof(struct Krn_Mem)\r | |
464 | \r | |
465 | /* The parameters for a CmdConfigure operation.\r | |
466 | There are so many options that it would be difficult to document each bit.\r | |
467 | We mostly use the default or recommended settings.\r | |
468 | */\r | |
469 | \r | |
470 | /*\r | |
471 | *--------------------------------------------------------------------------\r | |
472 | * Configuration CB Parameter Bit Definitions\r | |
473 | *--------------------------------------------------------------------------\r | |
474 | */\r | |
475 | // - Byte 0 (Default Value = 16h)\r | |
476 | #define CFIG_BYTE_COUNT 0x16 // 22 Configuration Bytes\r | |
477 | \r | |
478 | //- Byte 1 (Default Value = 88h)\r | |
479 | #define CFIG_TXRX_FIFO_LIMIT 0x88\r | |
480 | \r | |
481 | //- Byte 2 (Default Value = 0)\r | |
482 | #define CFIG_ADAPTIVE_IFS 0\r | |
483 | \r | |
484 | //- Byte 3 (Default Value = 0, ALWAYS. This byte is RESERVED)\r | |
485 | #define CFIG_RESERVED 0\r | |
486 | \r | |
487 | //- Byte 4 (Default Value = 0. Default implies that Rx DMA cannot be\r | |
488 | //- preempted).\r | |
489 | #define CFIG_RXDMA_BYTE_COUNT 0\r | |
490 | \r | |
491 | //- Byte 5 (Default Value = 80h. Default implies that Tx DMA cannot be\r | |
492 | //- preempted. However, setting these counters is enabled.)\r | |
493 | #define CFIG_DMBC_ENABLE 0x80\r | |
494 | \r | |
495 | //- Byte 6 (Default Value = 33h. Late SCB enabled, No TNO interrupts,\r | |
496 | //- CNA interrupts and do not save bad frames.)\r | |
497 | #define CFIG_LATE_SCB 1 // BIT 0\r | |
498 | #define CFIG_TNO_INTERRUPT 0x4 // BIT 2\r | |
499 | #define CFIG_CI_INTERRUPT 0x8 // BIT 3\r | |
500 | #define CFIG_SAVE_BAD_FRAMES 0x80 // BIT_7\r | |
501 | \r | |
502 | //- Byte 7 (Default Value = 7h. Discard short frames automatically and\r | |
503 | //- attempt upto 3 retries on transmit.)\r | |
504 | #define CFIG_DISCARD_SHORTRX 0x00001\r | |
505 | #define CFIG_URUN_RETRY BIT_1 OR BIT_2\r | |
506 | \r | |
507 | //- Byte 8 (Default Value = 1. Enable MII mode.)\r | |
508 | #define CFIG_503_MII BIT_0\r | |
509 | \r | |
510 | //- Byte 9 (Default Value = 0, ALWAYS)\r | |
511 | \r | |
512 | //- Byte 10 (Default Value = 2Eh)\r | |
513 | #define CFIG_NSAI BIT_3\r | |
514 | #define CFIG_PREAMBLE_LENGTH BIT_5 ;- Bit 5-4 = 1-0\r | |
515 | #define CFIG_NO_LOOPBACK 0\r | |
516 | #define CFIG_INTERNAL_LOOPBACK BIT_6\r | |
517 | #define CFIG_EXT_LOOPBACK BIT_7\r | |
518 | #define CFIG_EXT_PIN_LOOPBACK BIT_6 OR BIT_7\r | |
519 | \r | |
520 | //- Byte 11 (Default Value = 0)\r | |
521 | #define CFIG_LINEAR_PRIORITY 0\r | |
522 | \r | |
523 | //- Byte 12 (Default Value = 60h)\r | |
524 | #define CFIG_LPRIORITY_MODE 0\r | |
525 | #define CFIG_IFS 6 ;- 6 * 16 = 96\r | |
526 | \r | |
527 | //- Byte 13 (Default Value = 0, ALWAYS)\r | |
528 | \r | |
529 | //- Byte 14 (Default Value = 0F2h, ALWAYS)\r | |
530 | \r | |
531 | //- Byte 15 (Default Value = E8h)\r | |
532 | #define CFIG_PROMISCUOUS_MODE BIT_0\r | |
533 | #define CFIG_BROADCAST_DISABLE BIT_1\r | |
534 | #define CFIG_CRS_CDT BIT_7\r | |
535 | \r | |
536 | //- Byte 16 (Default Value = 0, ALWAYS)\r | |
537 | \r | |
538 | //- Byte 17 (Default Value = 40h, ALWAYS)\r | |
539 | \r | |
540 | //- Byte 18 (Default Value = F2h)\r | |
541 | #define CFIG_STRIPPING BIT_0\r | |
542 | #define CFIG_PADDING BIT_1\r | |
543 | #define CFIG_RX_CRC_TRANSFER BIT_2\r | |
544 | \r | |
545 | //- Byte 19 (Default Value = 80h)\r | |
546 | #define CFIG_FORCE_FDX BIT_6\r | |
547 | #define CFIG_FDX_PIN_ENABLE BIT_7\r | |
548 | \r | |
549 | //- Byte 20 (Default Value = 3Fh)\r | |
550 | #define CFIG_MULTI_IA BIT_6\r | |
551 | \r | |
552 | //- Byte 21 (Default Value = 05)\r | |
553 | #define CFIG_MC_ALL BIT_3\r | |
554 | \r | |
555 | /*-----------------------------------------------------------------------*/\r | |
556 | #define D102_REVID 0x0b\r | |
557 | \r | |
558 | #define HALF_DUPLEX 1\r | |
559 | #define FULL_DUPLEX 2\r | |
560 | \r | |
561 | typedef struct s_data_instance {\r | |
562 | \r | |
563 | UINT16 State; // stopped, started or initialized\r | |
564 | UINT16 Bus;\r | |
565 | UINT8 Device;\r | |
566 | UINT8 Function;\r | |
567 | UINT16 VendorID;\r | |
568 | UINT16 DeviceID;\r | |
569 | UINT16 RevID;\r | |
570 | UINT16 SubVendorID;\r | |
571 | UINT16 SubSystemID;\r | |
572 | \r | |
573 | UINT8 PermNodeAddress[PXE_MAC_LENGTH];\r | |
574 | UINT8 CurrentNodeAddress[PXE_MAC_LENGTH];\r | |
575 | UINT8 BroadcastNodeAddress[PXE_MAC_LENGTH];\r | |
576 | UINT32 Config[MAX_PCI_CONFIG_LEN];\r | |
577 | UINT32 NVData[MAX_EEPROM_LEN];\r | |
578 | \r | |
579 | UINT32 ioaddr;\r | |
580 | UINT32 flash_addr;\r | |
581 | \r | |
582 | UINT16 LinkSpeed; // actual link speed setting\r | |
583 | UINT16 LinkSpeedReq; // requested (forced) link speed\r | |
584 | UINT8 DuplexReq; // requested duplex\r | |
585 | UINT8 Duplex; // Duplex set\r | |
586 | UINT8 CableDetect; // 1 to detect and 0 not to detect the cable\r | |
587 | UINT8 LoopBack;\r | |
588 | \r | |
589 | UINT16 TxBufCnt;\r | |
590 | UINT16 TxBufSize;\r | |
591 | UINT16 RxBufCnt;\r | |
592 | UINT16 RxBufSize;\r | |
593 | UINT32 RxTotals;\r | |
594 | UINT32 TxTotals;\r | |
595 | \r | |
596 | UINT16 int_mask;\r | |
597 | UINT16 Int_Status;\r | |
598 | UINT16 PhyRecord[2]; // primary and secondary PHY record registers from eeprom\r | |
599 | UINT8 PhyAddress;\r | |
600 | UINT8 int_num;\r | |
601 | UINT16 NVData_Len;\r | |
602 | UINT32 MemoryLength;\r | |
603 | \r | |
604 | RxFD *rx_ring; // array of rx buffers\r | |
605 | TxCB *tx_ring; // array of tx buffers\r | |
606 | struct speedo_stats *statistics;\r | |
607 | TxCB *FreeTxHeadPtr;\r | |
608 | TxCB *FreeTxTailPtr;\r | |
609 | RxFD *RFDTailPtr;\r | |
610 | \r | |
611 | UINT64 rx_phy_addr; // physical addresses\r | |
612 | UINT64 tx_phy_addr;\r | |
613 | UINT64 stat_phy_addr;\r | |
614 | UINT64 MemoryPtr;\r | |
615 | UINT64 Mapped_MemoryPtr;\r | |
616 | \r | |
617 | UINT64 xmit_done[TX_BUFFER_COUNT << 1]; // circular buffer\r | |
618 | UINT16 xmit_done_head; // index into the xmit_done array\r | |
619 | UINT16 xmit_done_tail; // where are we filling now (index into xmit_done)\r | |
620 | UINT16 cur_rx_ind; // current RX Q head index\r | |
621 | UINT16 FreeCBCount;\r | |
622 | \r | |
623 | BOOLEAN in_interrupt;\r | |
624 | BOOLEAN in_transmit;\r | |
625 | BOOLEAN Receive_Started;\r | |
626 | UINT8 Rx_Filter;\r | |
627 | UINT8 VersionFlag; // UNDI30 or UNDI31??\r | |
628 | UINT8 rsvd[3];\r | |
629 | \r | |
630 | struct mc{\r | |
631 | UINT16 reserved [3]; // padding for this structure to make it 8 byte aligned\r | |
632 | UINT16 list_len;\r | |
633 | UINT8 mc_list[MAX_MCAST_ADDRESS_CNT][PXE_MAC_LENGTH]; // 8*32 is the size\r | |
634 | } mcast_list;\r | |
635 | \r | |
636 | UINT64 Unique_ID;\r | |
637 | \r | |
638 | EFI_PCI_IO_PROTOCOL *Io_Function;\r | |
639 | //\r | |
640 | // Original PCI attributes\r | |
641 | //\r | |
642 | UINT64 OriginalPciAttributes;\r | |
643 | \r | |
644 | VOID (*Delay_30)(UINTN); // call back routine\r | |
645 | VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r | |
646 | VOID (*Block_30)(UINT32 enable); // call back routine\r | |
647 | VOID (*Mem_Io_30)(UINT8 read_write, UINT8 len, UINT64 port, UINT64 buf_addr);\r | |
648 | VOID (*Delay)(UINT64, UINTN); // call back routine\r | |
649 | VOID (*Virt2Phys)(UINT64 unq_id, UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r | |
650 | VOID (*Block)(UINT64 unq_id, UINT32 enable); // call back routine\r | |
651 | VOID (*Mem_Io)(UINT64 unq_id, UINT8 read_write, UINT8 len, UINT64 port,\r | |
652 | UINT64 buf_addr);\r | |
653 | VOID (*Map_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r | |
654 | UINT32 Direction, UINT64 mapped_addr);\r | |
655 | VOID (*UnMap_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r | |
656 | UINT32 Direction, UINT64 mapped_addr);\r | |
657 | VOID (*Sync_Mem)(UINT64 unq_id, UINT64 virtual_addr,\r | |
658 | UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r | |
659 | } NIC_DATA_INSTANCE;\r | |
660 | \r | |
661 | #pragma pack(1)\r | |
662 | struct MC_CB_STRUCT{\r | |
663 | UINT16 count;\r | |
664 | UINT8 m_list[MAX_MCAST_ADDRESS_CNT][ETHER_MAC_ADDR_LEN];\r | |
665 | };\r | |
666 | #pragma pack()\r | |
667 | \r | |
668 | #define FOUR_GIGABYTE (UINT64)0x100000000ULL\r | |
669 | \r | |
670 | #endif\r | |
671 | \r |