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1 | /** @file\r |
2 | \r | |
3 | AMD Sev Dxe driver. This driver is dispatched early in DXE, due to being list\r | |
c16d4e35 LE |
4 | in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when SEV\r |
5 | is enabled.\r | |
24e4ad75 | 6 | \r |
84cddd70 | 7 | Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>\r |
24e4ad75 | 8 | \r |
b26f0cf9 | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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10 | \r |
11 | **/\r | |
12 | \r | |
84cddd70 | 13 | #include <IndustryStandard/Q35MchIch9.h>\r |
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14 | #include <Library/BaseLib.h>\r |
15 | #include <Library/BaseMemoryLib.h>\r | |
c6073a0e | 16 | #include <Library/DebugLib.h>\r |
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17 | #include <Library/DxeServicesTableLib.h>\r |
18 | #include <Library/MemEncryptSevLib.h>\r | |
c6073a0e | 19 | #include <Library/MemoryAllocationLib.h>\r |
5e2e5647 | 20 | #include <Library/PcdLib.h>\r |
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21 | \r |
22 | EFI_STATUS\r | |
23 | EFIAPI\r | |
24 | AmdSevDxeEntryPoint (\r | |
25 | IN EFI_HANDLE ImageHandle,\r | |
26 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
27 | )\r | |
28 | {\r | |
29 | EFI_STATUS Status;\r | |
30 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR *AllDescMap;\r | |
31 | UINTN NumEntries;\r | |
32 | UINTN Index;\r | |
33 | \r | |
34 | //\r | |
35 | // Do nothing when SEV is not enabled\r | |
36 | //\r | |
37 | if (!MemEncryptSevIsEnabled ()) {\r | |
38 | return EFI_UNSUPPORTED;\r | |
39 | }\r | |
40 | \r | |
41 | //\r | |
42 | // Iterate through the GCD map and clear the C-bit from MMIO and NonExistent\r | |
c16d4e35 LE |
43 | // memory space. The NonExistent memory space will be used for mapping the\r |
44 | // MMIO space added later (eg PciRootBridge). By clearing both known MMIO and\r | |
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45 | // NonExistent memory space can gurantee that current and furture MMIO adds\r |
46 | // will have C-bit cleared.\r | |
47 | //\r | |
48 | Status = gDS->GetMemorySpaceMap (&NumEntries, &AllDescMap);\r | |
49 | if (!EFI_ERROR (Status)) {\r | |
50 | for (Index = 0; Index < NumEntries; Index++) {\r | |
51 | CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Desc;\r | |
52 | \r | |
53 | Desc = &AllDescMap[Index];\r | |
54 | if (Desc->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo ||\r | |
55 | Desc->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r | |
c394fa4c | 56 | Status = MemEncryptSevClearMmioPageEncMask (\r |
c16d4e35 LE |
57 | 0,\r |
58 | Desc->BaseAddress,\r | |
c394fa4c | 59 | EFI_SIZE_TO_PAGES (Desc->Length)\r |
c16d4e35 | 60 | );\r |
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61 | ASSERT_EFI_ERROR (Status);\r |
62 | }\r | |
63 | }\r | |
64 | \r | |
65 | FreePool (AllDescMap);\r | |
66 | }\r | |
67 | \r | |
84cddd70 TL |
68 | //\r |
69 | // If PCI Express is enabled, the MMCONFIG area has been reserved, rather\r | |
70 | // than marked as MMIO, and so the C-bit won't be cleared by the above walk\r | |
71 | // through the GCD map. Check for the MMCONFIG area and clear the C-bit for\r | |
72 | // the range.\r | |
73 | //\r | |
74 | if (PcdGet16 (PcdOvmfHostBridgePciDevId) == INTEL_Q35_MCH_DEVICE_ID) {\r | |
c394fa4c | 75 | Status = MemEncryptSevClearMmioPageEncMask (\r |
84cddd70 TL |
76 | 0,\r |
77 | FixedPcdGet64 (PcdPciExpressBaseAddress),\r | |
c394fa4c | 78 | EFI_SIZE_TO_PAGES (SIZE_256MB)\r |
84cddd70 TL |
79 | );\r |
80 | \r | |
81 | ASSERT_EFI_ERROR (Status);\r | |
82 | }\r | |
83 | \r | |
5e2e5647 LE |
84 | //\r |
85 | // When SMM is enabled, clear the C-bit from SMM Saved State Area\r | |
86 | //\r | |
87 | // NOTES: The SavedStateArea address cleared here is before SMBASE\r | |
88 | // relocation. Currently, we do not clear the SavedStateArea address after\r | |
89 | // SMBASE is relocated due to the following reasons:\r | |
90 | //\r | |
91 | // 1) Guest BIOS never access the relocated SavedStateArea.\r | |
92 | //\r | |
93 | // 2) The C-bit works on page-aligned address, but the SavedStateArea\r | |
94 | // address is not a page-aligned. Theoretically, we could roundup the address\r | |
95 | // and clear the C-bit of aligned address but looking carefully we found\r | |
96 | // that some portion of the page contains code -- which will causes a bigger\r | |
97 | // issues for SEV guest. When SEV is enabled, all the code must be encrypted\r | |
98 | // otherwise hardware will cause trap.\r | |
99 | //\r | |
100 | // We restore the C-bit for this SMM Saved State Area after SMBASE relocation\r | |
101 | // is completed (See OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c).\r | |
102 | //\r | |
103 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
104 | UINTN MapPagesBase;\r | |
105 | UINTN MapPagesCount;\r | |
106 | \r | |
107 | Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r | |
108 | &MapPagesBase,\r | |
109 | &MapPagesCount\r | |
110 | );\r | |
111 | ASSERT_EFI_ERROR (Status);\r | |
112 | \r | |
113 | //\r | |
114 | // Although these pages were set aside (i.e., allocated) by PlatformPei, we\r | |
115 | // could be after a warm reboot from the OS. Don't leak any stale OS data\r | |
116 | // to the hypervisor.\r | |
117 | //\r | |
118 | ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));\r | |
119 | \r | |
120 | Status = MemEncryptSevClearPageEncMask (\r | |
121 | 0, // Cr3BaseAddress -- use current CR3\r | |
122 | MapPagesBase, // BaseAddress\r | |
123 | MapPagesCount, // NumPages\r | |
124 | TRUE // Flush\r | |
125 | );\r | |
126 | if (EFI_ERROR (Status)) {\r | |
127 | DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevClearPageEncMask(): %r\n",\r | |
128 | __FUNCTION__, Status));\r | |
129 | ASSERT (FALSE);\r | |
130 | CpuDeadLoop ();\r | |
131 | }\r | |
132 | }\r | |
133 | \r | |
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134 | return EFI_SUCCESS;\r |
135 | }\r |