| 8016da21 |
1 | /** @file\r |
| 2 | Legacy Region Support\r |
| 3 | \r |
| 4 | Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r |
| 5 | \r |
| 6 | This program and the accompanying materials are\r |
| 7 | licensed and made available under the terms and conditions of the BSD License\r |
| 8 | which accompanies this distribution. The full text of the license may be found at\r |
| 9 | http://opensource.org/licenses/bsd-license.php\r |
| 10 | \r |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | \r |
| 14 | **/\r |
| 15 | \r |
| 16 | #ifndef _LEGACY_INTERRUPT_H_\r |
| 17 | #define _LEGACY_INTERRUPT_H_\r |
| 18 | \r |
| 19 | #include <PiDxe.h>\r |
| 20 | \r |
| 21 | #include <Protocol/LegacyInterrupt.h>\r |
| 22 | \r |
| 23 | #include <Library/PciLib.h>\r |
| 24 | #include <Library/DebugLib.h>\r |
| 25 | #include <Library/UefiBootServicesTableLib.h>\r |
| 26 | \r |
| 27 | #define LEGACY_INT_BUS 0\r |
| 28 | #define LEGACY_INT_DEV 1\r |
| 29 | #define LEGACY_INT_FUNC 0\r |
| 30 | \r |
| 31 | #define PIRQN 0x00 // PIRQ Null\r |
| 32 | #define PIRQA 0x60\r |
| 33 | #define PIRQB 0x61\r |
| 34 | #define PIRQC 0x62\r |
| 35 | #define PIRQD 0x63\r |
| 36 | #define PIRQE 0x68\r |
| 37 | #define PIRQF 0x69\r |
| 38 | #define PIRQG 0x6A\r |
| 39 | #define PIRQH 0x6B\r |
| 40 | \r |
| 41 | #define MAX_PIRQ_NUMBER 8\r |
| 42 | \r |
| 43 | /**\r |
| 44 | Return the number of PIRQs supported by this chipset.\r |
| 45 | \r |
| 46 | @param[in] This Pointer to LegacyInterrupt Protocol\r |
| 47 | @param[out] NumberPirqs The pointer to return the max IRQ number supported\r |
| 48 | \r |
| 49 | @retval EFI_SUCCESS Max PIRQs successfully returned\r |
| 50 | \r |
| 51 | **/\r |
| 52 | EFI_STATUS\r |
| 53 | EFIAPI\r |
| 54 | GetNumberPirqs (\r |
| 55 | IN EFI_LEGACY_INTERRUPT_PROTOCOL *This,\r |
| 56 | OUT UINT8 *NumberPirqs\r |
| 57 | );\r |
| 58 | \r |
| 59 | /**\r |
| 60 | Return PCI location of this device.\r |
| 61 | $PIR table requires this info.\r |
| 62 | \r |
| 63 | @param[in] This - Protocol instance pointer.\r |
| 64 | @param[out] Bus - PCI Bus\r |
| 65 | @param[out] Device - PCI Device\r |
| 66 | @param[out] Function - PCI Function\r |
| 67 | \r |
| 68 | @retval EFI_SUCCESS Bus/Device/Function returned\r |
| 69 | \r |
| 70 | **/\r |
| 71 | EFI_STATUS\r |
| 72 | EFIAPI\r |
| 73 | GetLocation (\r |
| 74 | IN EFI_LEGACY_INTERRUPT_PROTOCOL *This,\r |
| 75 | OUT UINT8 *Bus,\r |
| 76 | OUT UINT8 *Device,\r |
| 77 | OUT UINT8 *Function\r |
| 78 | );\r |
| 79 | \r |
| 80 | /**\r |
| 81 | Read the given PIRQ register\r |
| 82 | \r |
| 83 | @param[in] This Protocol instance pointer\r |
| 84 | @param[in] PirqNumber The Pirq register 0 = A, 1 = B etc\r |
| 85 | @param[out] PirqData Value read\r |
| 86 | \r |
| 87 | @retval EFI_SUCCESS Decoding change affected.\r |
| 88 | @retval EFI_INVALID_PARAMETER Invalid PIRQ number\r |
| 89 | \r |
| 90 | **/\r |
| 91 | EFI_STATUS\r |
| 92 | EFIAPI\r |
| 93 | ReadPirq (\r |
| 94 | IN EFI_LEGACY_INTERRUPT_PROTOCOL *This,\r |
| 95 | IN UINT8 PirqNumber,\r |
| 96 | OUT UINT8 *PirqData\r |
| 97 | );\r |
| 98 | \r |
| 99 | /**\r |
| 100 | Write the given PIRQ register\r |
| 101 | \r |
| 102 | @param[in] This Protocol instance pointer\r |
| 103 | @param[in] PirqNumber The Pirq register 0 = A, 1 = B etc\r |
| 104 | @param[out] PirqData Value to write\r |
| 105 | \r |
| 106 | @retval EFI_SUCCESS Decoding change affected.\r |
| 107 | @retval EFI_INVALID_PARAMETER Invalid PIRQ number\r |
| 108 | \r |
| 109 | **/\r |
| 110 | EFI_STATUS\r |
| 111 | EFIAPI\r |
| 112 | WritePirq (\r |
| 113 | IN EFI_LEGACY_INTERRUPT_PROTOCOL *This,\r |
| 114 | IN UINT8 PirqNumber,\r |
| 115 | IN UINT8 PirqData\r |
| 116 | );\r |
| 117 | \r |
| 118 | #endif\r |
| 119 | \r |
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