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8016da21 | 1 | /** @file\r |
2 | Legacy Region Support\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r | |
5 | \r | |
6 | This program and the accompanying materials are\r | |
7 | licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _LEGACY_INTERRUPT_H_\r | |
17 | #define _LEGACY_INTERRUPT_H_\r | |
18 | \r | |
19 | #include <PiDxe.h>\r | |
20 | \r | |
21 | #include <Protocol/LegacyInterrupt.h>\r | |
22 | \r | |
72a11001 | 23 | #include <Library/PcdLib.h>\r |
8016da21 | 24 | #include <Library/PciLib.h>\r |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/UefiBootServicesTableLib.h>\r | |
72a11001 GS |
27 | #include <OvmfPlatforms.h>\r |
28 | \r | |
8016da21 | 29 | \r |
30 | #define LEGACY_INT_BUS 0\r | |
72a11001 GS |
31 | #define LEGACY_INT_DEV_PIIX4 0x01\r |
32 | #define LEGACY_INT_DEV_Q35 0x1f\r | |
8016da21 | 33 | #define LEGACY_INT_FUNC 0\r |
34 | \r | |
35 | #define PIRQN 0x00 // PIRQ Null\r | |
36 | #define PIRQA 0x60\r | |
37 | #define PIRQB 0x61\r | |
38 | #define PIRQC 0x62\r | |
39 | #define PIRQD 0x63\r | |
40 | #define PIRQE 0x68\r | |
41 | #define PIRQF 0x69\r | |
42 | #define PIRQG 0x6A\r | |
43 | #define PIRQH 0x6B\r | |
44 | \r | |
45 | #define MAX_PIRQ_NUMBER 8\r | |
46 | \r | |
47 | /**\r | |
48 | Return the number of PIRQs supported by this chipset.\r | |
49 | \r | |
50 | @param[in] This Pointer to LegacyInterrupt Protocol\r | |
51 | @param[out] NumberPirqs The pointer to return the max IRQ number supported\r | |
52 | \r | |
53 | @retval EFI_SUCCESS Max PIRQs successfully returned\r | |
54 | \r | |
55 | **/\r | |
56 | EFI_STATUS\r | |
57 | EFIAPI\r | |
58 | GetNumberPirqs (\r | |
59 | IN EFI_LEGACY_INTERRUPT_PROTOCOL *This,\r | |
60 | OUT UINT8 *NumberPirqs\r | |
61 | );\r | |
62 | \r | |
63 | /**\r | |
64 | Return PCI location of this device.\r | |
65 | $PIR table requires this info.\r | |
66 | \r | |
67 | @param[in] This - Protocol instance pointer.\r | |
68 | @param[out] Bus - PCI Bus\r | |
69 | @param[out] Device - PCI Device\r | |
70 | @param[out] Function - PCI Function\r | |
71 | \r | |
72 | @retval EFI_SUCCESS Bus/Device/Function returned\r | |
73 | \r | |
74 | **/\r | |
75 | EFI_STATUS\r | |
76 | EFIAPI\r | |
77 | GetLocation (\r | |
78 | IN EFI_LEGACY_INTERRUPT_PROTOCOL *This,\r | |
79 | OUT UINT8 *Bus,\r | |
80 | OUT UINT8 *Device,\r | |
81 | OUT UINT8 *Function\r | |
82 | );\r | |
83 | \r | |
84 | /**\r | |
85 | Read the given PIRQ register\r | |
86 | \r | |
87 | @param[in] This Protocol instance pointer\r | |
88 | @param[in] PirqNumber The Pirq register 0 = A, 1 = B etc\r | |
89 | @param[out] PirqData Value read\r | |
90 | \r | |
91 | @retval EFI_SUCCESS Decoding change affected.\r | |
92 | @retval EFI_INVALID_PARAMETER Invalid PIRQ number\r | |
93 | \r | |
94 | **/\r | |
95 | EFI_STATUS\r | |
96 | EFIAPI\r | |
97 | ReadPirq (\r | |
98 | IN EFI_LEGACY_INTERRUPT_PROTOCOL *This,\r | |
99 | IN UINT8 PirqNumber,\r | |
100 | OUT UINT8 *PirqData\r | |
101 | );\r | |
102 | \r | |
103 | /**\r | |
104 | Write the given PIRQ register\r | |
105 | \r | |
106 | @param[in] This Protocol instance pointer\r | |
107 | @param[in] PirqNumber The Pirq register 0 = A, 1 = B etc\r | |
108 | @param[out] PirqData Value to write\r | |
109 | \r | |
110 | @retval EFI_SUCCESS Decoding change affected.\r | |
111 | @retval EFI_INVALID_PARAMETER Invalid PIRQ number\r | |
112 | \r | |
113 | **/\r | |
114 | EFI_STATUS\r | |
115 | EFIAPI\r | |
116 | WritePirq (\r | |
117 | IN EFI_LEGACY_INTERRUPT_PROTOCOL *This,\r | |
118 | IN UINT8 PirqNumber,\r | |
119 | IN UINT8 PirqData\r | |
120 | );\r | |
121 | \r | |
122 | #endif\r | |
123 | \r |