OvmfPkg: Apply uncrustify changes

[mirror_edk2.git] / OvmfPkg / Include / IndustryStandard / Xen / hvm / params.h

/*\r
 * SPDX-License-Identifier: MIT\r
 */\r
\r
#ifndef __XEN_PUBLIC_HVM_PARAMS_H__\r
#define __XEN_PUBLIC_HVM_PARAMS_H__\r
\r
#include "hvm_op.h"\r
\r
/*\r
 * Parameter space for HVMOP_{set,get}_param.\r
 */\r
\r
/*\r
 * How should CPU0 event-channel notifications be delivered?\r
 * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).\r
 * val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows:\r
 *                  Domain = val[47:32], Bus  = val[31:16],\r
 *                  DevFn  = val[15: 8], IntX = val[ 1: 0]\r
 * val[63:56] == 2: val[7:0] is a vector number, check for\r
 *                  XENFEAT_hvm_callback_vector to know if this delivery\r
 *                  method is available.\r
 * If val == 0 then CPU0 event-channel notifications are not delivered.\r
 */\r
#define HVM_PARAM_CALLBACK_IRQ  0\r
\r
/*\r
 * These are not used by Xen. They are here for convenience of HVM-guest\r
 * xenbus implementations.\r
 */\r
#define HVM_PARAM_STORE_PFN     1\r
#define HVM_PARAM_STORE_EVTCHN  2\r
\r
#define HVM_PARAM_PAE_ENABLED  4\r
\r
#define HVM_PARAM_IOREQ_PFN  5\r
\r
#define HVM_PARAM_BUFIOREQ_PFN     6\r
#define HVM_PARAM_BUFIOREQ_EVTCHN  26\r
\r
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)\r
\r
/* Expose Viridian interfaces to this HVM guest? */\r
#define HVM_PARAM_VIRIDIAN  9\r
\r
#endif\r
\r
/*\r
 * Set mode for virtual timers (currently x86 only):\r
 *  delay_for_missed_ticks (default):\r
 *   Do not advance a vcpu's time beyond the correct delivery time for\r
 *   interrupts that have been missed due to preemption. Deliver missed\r
 *   interrupts when the vcpu is rescheduled and advance the vcpu's virtual\r
 *   time stepwise for each one.\r
 *  no_delay_for_missed_ticks:\r
 *   As above, missed interrupts are delivered, but guest time always tracks\r
 *   wallclock (i.e., real) time while doing so.\r
 *  no_missed_ticks_pending:\r
 *   No missed interrupts are held pending. Instead, to ensure ticks are\r
 *   delivered at some non-zero rate, if we detect missed ticks then the\r
 *   internal tick alarm is not disabled if the VCPU is preempted during the\r
 *   next tick period.\r
 *  one_missed_tick_pending:\r
 *   Missed interrupts are collapsed together and delivered as one 'late tick'.\r
 *   Guest time always tracks wallclock (i.e., real) time.\r
 */\r
#define HVM_PARAM_TIMER_MODE              10\r
#define HVMPTM_delay_for_missed_ticks     0\r
#define HVMPTM_no_delay_for_missed_ticks  1\r
#define HVMPTM_no_missed_ticks_pending    2\r
#define HVMPTM_one_missed_tick_pending    3\r
\r
/* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */\r
#define HVM_PARAM_HPET_ENABLED  11\r
\r
/* Identity-map page directory used by Intel EPT when CR0.PG=0. */\r
#define HVM_PARAM_IDENT_PT  12\r
\r
/* Device Model domain, defaults to 0. */\r
#define HVM_PARAM_DM_DOMAIN  13\r
\r
/* ACPI S state: currently support S0 and S3 on x86. */\r
#define HVM_PARAM_ACPI_S_STATE  14\r
\r
/* TSS used on Intel when CR0.PE=0. */\r
#define HVM_PARAM_VM86_TSS  15\r
\r
/* Boolean: Enable aligning all periodic vpts to reduce interrupts */\r
#define HVM_PARAM_VPT_ALIGN  16\r
\r
/* Console debug shared memory ring and event channel */\r
#define HVM_PARAM_CONSOLE_PFN     17\r
#define HVM_PARAM_CONSOLE_EVTCHN  18\r
\r
/*\r
 * Select location of ACPI PM1a and TMR control blocks. Currently two locations\r
 * are supported, specified by version 0 or 1 in this parameter:\r
 *   - 0: default, use the old addresses\r
 *        PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48\r
 *   - 1: use the new default qemu addresses\r
 *        PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008\r
 * You can find these address definitions in <hvm/ioreq.h>\r
 */\r
#define HVM_PARAM_ACPI_IOPORTS_LOCATION  19\r
\r
/* Enable blocking memory events, async or sync (pause vcpu until response)\r
 * onchangeonly indicates messages only on a change of value */\r
#define HVM_PARAM_MEMORY_EVENT_CR0          20\r
#define HVM_PARAM_MEMORY_EVENT_CR3          21\r
#define HVM_PARAM_MEMORY_EVENT_CR4          22\r
#define HVM_PARAM_MEMORY_EVENT_INT3         23\r
#define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP  25\r
#define HVM_PARAM_MEMORY_EVENT_MSR          30\r
\r
#define HVMPME_MODE_MASK      (3 << 0)\r
#define HVMPME_mode_disabled  0\r
#define HVMPME_mode_async     1\r
#define HVMPME_mode_sync      2\r
#define HVMPME_onchangeonly   (1 << 2)\r
\r
/* Boolean: Enable nestedhvm (hvm only) */\r
#define HVM_PARAM_NESTEDHVM  24\r
\r
/* Params for the mem event rings */\r
#define HVM_PARAM_PAGING_RING_PFN   27\r
#define HVM_PARAM_ACCESS_RING_PFN   28\r
#define HVM_PARAM_SHARING_RING_PFN  29\r
\r
/* SHUTDOWN_* action in case of a triple fault */\r
#define HVM_PARAM_TRIPLE_FAULT_REASON  31\r
\r
#define HVM_NR_PARAMS  32\r
\r
#endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */\r