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1 | /** @file\r |
2 | Provide constructor and GetTick for BaseRom instance of ACPI Timer Library\r | |
3 | \r | |
4 | Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.\r | |
5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r | |
6 | \r | |
7 | This program and the accompanying materials are licensed and made\r | |
8 | available under the terms and conditions of the BSD License which\r | |
9 | accompanies this distribution. The full text of the license may\r | |
10 | be found at http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | **/\r | |
15 | \r | |
16 | #include <Library/DebugLib.h>\r | |
17 | #include <Library/IoLib.h>\r | |
18 | #include <Library/PciLib.h>\r | |
19 | #include <Library/PcdLib.h>\r | |
20 | #include <OvmfPlatforms.h>\r | |
21 | \r | |
22 | //\r | |
23 | // Power Management PCI Configuration Register fields\r | |
24 | //\r | |
25 | #define PMBA_RTE BIT0\r | |
26 | #define PMIOSE BIT0\r | |
27 | \r | |
28 | //\r | |
29 | // Offset in the Power Management Base Address to the ACPI Timer\r | |
30 | //\r | |
31 | #define ACPI_TIMER_OFFSET 0x8\r | |
32 | \r | |
33 | /**\r | |
34 | The constructor function enables ACPI IO space.\r | |
35 | \r | |
36 | If ACPI I/O space not enabled, this function will enable it.\r | |
37 | It will always return RETURN_SUCCESS.\r | |
38 | \r | |
39 | @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.\r | |
40 | \r | |
41 | **/\r | |
42 | RETURN_STATUS\r | |
43 | EFIAPI\r | |
44 | AcpiTimerLibConstructor (\r | |
45 | VOID\r | |
46 | )\r | |
47 | {\r | |
48 | UINT16 HostBridgeDevId;\r | |
49 | UINTN Pmba;\r | |
50 | UINTN PmRegMisc;\r | |
51 | \r | |
52 | //\r | |
53 | // Query Host Bridge DID to determine platform type\r | |
54 | //\r | |
55 | HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
56 | switch (HostBridgeDevId) {\r | |
57 | case INTEL_82441_DEVICE_ID:\r | |
58 | Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r | |
59 | PmRegMisc = POWER_MGMT_REGISTER_PIIX4 (0x80);\r | |
60 | break;\r | |
61 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
62 | Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r | |
63 | PmRegMisc = POWER_MGMT_REGISTER_Q35 (0x80);\r | |
64 | break;\r | |
65 | default:\r | |
66 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
67 | __FUNCTION__, HostBridgeDevId));\r | |
68 | ASSERT (FALSE);\r | |
69 | return RETURN_UNSUPPORTED;\r | |
70 | }\r | |
71 | \r | |
72 | //\r | |
73 | // Check to see if the Power Management Base Address is already enabled\r | |
74 | //\r | |
75 | if ((PciRead8 (PmRegMisc) & PMIOSE) == 0) {\r | |
76 | //\r | |
77 | // If the Power Management Base Address is not programmed,\r | |
78 | // then program the Power Management Base Address from a PCD.\r | |
79 | //\r | |
80 | PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r | |
81 | \r | |
82 | //\r | |
83 | // Enable PMBA I/O port decodes in PMREGMISC\r | |
84 | //\r | |
85 | PciOr8 (PmRegMisc, PMIOSE);\r | |
86 | }\r | |
87 | \r | |
88 | return RETURN_SUCCESS;\r | |
89 | }\r | |
90 | \r | |
91 | /**\r | |
92 | Internal function to read the current tick counter of ACPI.\r | |
93 | \r | |
94 | Dynamically compute the address of the ACPI tick counter based on the\r | |
95 | properties of the underlying platform, to avoid relying on global variables.\r | |
96 | \r | |
97 | @return The tick counter read.\r | |
98 | \r | |
99 | **/\r | |
100 | UINT32\r | |
101 | InternalAcpiGetTimerTick (\r | |
102 | VOID\r | |
103 | )\r | |
104 | {\r | |
105 | UINT16 HostBridgeDevId;\r | |
106 | UINTN Pmba;\r | |
107 | \r | |
108 | //\r | |
109 | // Query Host Bridge DID to determine platform type\r | |
110 | //\r | |
111 | HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
112 | switch (HostBridgeDevId) {\r | |
113 | case INTEL_82441_DEVICE_ID:\r | |
114 | Pmba = POWER_MGMT_REGISTER_PIIX4 (0x40);\r | |
115 | break;\r | |
116 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
117 | Pmba = POWER_MGMT_REGISTER_Q35 (0x40);\r | |
118 | break;\r | |
119 | default:\r | |
120 | DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r | |
121 | __FUNCTION__, HostBridgeDevId));\r | |
122 | ASSERT (FALSE);\r | |
123 | return 0;\r | |
124 | }\r | |
125 | \r | |
126 | //\r | |
127 | // Read PMBA to read and return the current ACPI timer value.\r | |
128 | //\r | |
129 | return IoRead32 ((PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET);\r | |
130 | }\r |