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1 | /** @file\r |
2 | \r | |
3 | Virtual Memory Management Services to set or clear the memory encryption bit\r | |
4 | \r | |
5 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
6 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r | |
7 | \r | |
8 | This program and the accompanying materials\r | |
9 | are licensed and made available under the terms and conditions of the BSD License\r | |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r | |
17 | \r | |
18 | **/\r | |
19 | \r | |
20 | #ifndef __VIRTUAL_MEMORY__\r | |
21 | #define __VIRTUAL_MEMORY__\r | |
22 | \r | |
23 | #include <Uefi.h>\r | |
24 | #include <Library/BaseLib.h>\r | |
25 | #include <Library/BaseMemoryLib.h>\r | |
26 | #include <Library/DebugLib.h>\r | |
27 | #include <Library/MemoryAllocationLib.h>\r | |
28 | \r | |
29 | #include <Library/CacheMaintenanceLib.h>\r | |
30 | #define SYS_CODE64_SEL 0x38\r | |
31 | \r | |
32 | #pragma pack(1)\r | |
33 | \r | |
34 | //\r | |
35 | // Page-Map Level-4 Offset (PML4) and\r | |
36 | // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r | |
37 | //\r | |
38 | \r | |
39 | typedef union {\r | |
40 | struct {\r | |
41 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
42 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
43 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
44 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
45 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
46 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
47 | UINT64 Reserved:1; // Reserved\r | |
48 | UINT64 MustBeZero:2; // Must Be Zero\r | |
49 | UINT64 Available:3; // Available for use by system software\r | |
50 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
51 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
52 | UINT64 Nx:1; // No Execute bit\r | |
53 | } Bits;\r | |
54 | UINT64 Uint64;\r | |
55 | } PAGE_MAP_AND_DIRECTORY_POINTER;\r | |
56 | \r | |
57 | //\r | |
58 | // Page Table Entry 4KB\r | |
59 | //\r | |
60 | typedef union {\r | |
61 | struct {\r | |
62 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
63 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
64 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
65 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
66 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
67 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
68 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
69 | UINT64 PAT:1; //\r | |
70 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r | |
71 | UINT64 Available:3; // Available for use by system software\r | |
72 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
73 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
74 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
75 | } Bits;\r | |
76 | UINT64 Uint64;\r | |
77 | } PAGE_TABLE_4K_ENTRY;\r | |
78 | \r | |
79 | //\r | |
80 | // Page Table Entry 2MB\r | |
81 | //\r | |
82 | typedef union {\r | |
83 | struct {\r | |
84 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
85 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
86 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
87 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
88 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
89 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
90 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
91 | UINT64 MustBe1:1; // Must be 1\r | |
92 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r | |
93 | UINT64 Available:3; // Available for use by system software\r | |
94 | UINT64 PAT:1; //\r | |
95 | UINT64 MustBeZero:8; // Must be zero;\r | |
96 | UINT64 PageTableBaseAddress:31; // Page Table Base Address\r | |
97 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
98 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
99 | } Bits;\r | |
100 | UINT64 Uint64;\r | |
101 | } PAGE_TABLE_ENTRY;\r | |
102 | \r | |
103 | //\r | |
104 | // Page Table Entry 1GB\r | |
105 | //\r | |
106 | typedef union {\r | |
107 | struct {\r | |
108 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
109 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
110 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
111 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
112 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
113 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
114 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
115 | UINT64 MustBe1:1; // Must be 1\r | |
116 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r | |
117 | UINT64 Available:3; // Available for use by system software\r | |
118 | UINT64 PAT:1; //\r | |
119 | UINT64 MustBeZero:17; // Must be zero;\r | |
120 | UINT64 PageTableBaseAddress:22; // Page Table Base Address\r | |
121 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
122 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
123 | } Bits;\r | |
124 | UINT64 Uint64;\r | |
125 | } PAGE_TABLE_1G_ENTRY;\r | |
126 | \r | |
127 | #pragma pack()\r | |
128 | \r | |
129 | #define IA32_PG_P BIT0\r | |
130 | #define IA32_PG_RW BIT1\r | |
131 | \r | |
132 | #define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1)\r | |
133 | #define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r | |
134 | #define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r | |
135 | #define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r | |
136 | #define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r | |
137 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r | |
138 | \r | |
139 | /**\r | |
140 | This function clears memory encryption bit for the memory region specified by PhysicalAddress\r | |
141 | and length from the current page table context.\r | |
142 | \r | |
143 | @param[in] PhysicalAddress The physical address that is the start address of a memory region.\r | |
144 | @param[in] Length The length of memory region\r | |
145 | @param[in] Flush Flush the caches before applying the encryption mask\r | |
146 | \r | |
147 | @retval RETURN_SUCCESS The attributes were cleared for the memory region.\r | |
148 | @retval RETURN_INVALID_PARAMETER Number of pages is zero.\r | |
149 | @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is not supported\r | |
150 | **/\r | |
151 | RETURN_STATUS\r | |
152 | EFIAPI\r | |
153 | InternalMemEncryptSevSetMemoryDecrypted (\r | |
154 | IN PHYSICAL_ADDRESS Cr3BaseAddress,\r | |
155 | IN PHYSICAL_ADDRESS PhysicalAddress,\r | |
156 | IN UINT64 Length,\r | |
157 | IN BOOLEAN CacheFlush\r | |
158 | );\r | |
159 | \r | |
160 | /**\r | |
161 | This function sets memory encryption bit for the memory region specified by\r | |
162 | PhysicalAddress and length from the current page table context.\r | |
163 | \r | |
164 | @param[in] PhysicalAddress The physical address that is the start address\r | |
165 | of a memory region.\r | |
166 | @param[in] Length The length of memory region\r | |
167 | @param[in] Flush Flush the caches before applying the\r | |
168 | encryption mask\r | |
169 | \r | |
170 | @retval RETURN_SUCCESS The attributes were cleared for the memory region.\r | |
171 | @retval RETURN_INVALID_PARAMETER Number of pages is zero.\r | |
172 | @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute is\r | |
173 | not supported\r | |
174 | **/\r | |
175 | RETURN_STATUS\r | |
176 | EFIAPI\r | |
177 | InternalMemEncryptSevSetMemoryEncrypted (\r | |
178 | IN PHYSICAL_ADDRESS Cr3BaseAddress,\r | |
179 | IN PHYSICAL_ADDRESS PhysicalAddress,\r | |
180 | IN UINT64 Length,\r | |
181 | IN BOOLEAN CacheFlush\r | |
182 | );\r | |
183 | \r | |
184 | #endif\r |