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13b5d743 BS |
1 | /**@file\r |
2 | Initialize Secure Encrypted Virtualization (SEV) support\r | |
3 | \r | |
4 | Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r | |
5 | \r | |
b26f0cf9 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
13b5d743 BS |
7 | \r |
8 | **/\r | |
9 | //\r | |
10 | // The package level header files this module uses\r | |
11 | //\r | |
300aae11 | 12 | #include <IndustryStandard/Q35MchIch9.h>\r |
449a6e49 | 13 | #include <Library/BaseMemoryLib.h>\r |
13b5d743 | 14 | #include <Library/DebugLib.h>\r |
86defc2c | 15 | #include <Library/HobLib.h>\r |
6d576e7a | 16 | #include <Library/MemEncryptSevLib.h>\r |
449a6e49 | 17 | #include <Library/MemoryAllocationLib.h>\r |
13b5d743 | 18 | #include <Library/PcdLib.h>\r |
6d576e7a | 19 | #include <PiPei.h>\r |
13b5d743 | 20 | #include <Register/Amd/Cpuid.h>\r |
449a6e49 | 21 | #include <Register/Amd/Msr.h>\r |
6d576e7a | 22 | #include <Register/Cpuid.h>\r |
300aae11 | 23 | #include <Register/Intel/SmramSaveStateMap.h>\r |
13b5d743 | 24 | \r |
c0d221a3 LE |
25 | #include "Platform.h"\r |
26 | \r | |
cf845a74 TL |
27 | /**\r |
28 | \r | |
29 | Initialize SEV-ES support if running as an SEV-ES guest.\r | |
30 | \r | |
31 | **/\r | |
32 | STATIC\r | |
33 | VOID\r | |
34 | AmdSevEsInitialize (\r | |
35 | VOID\r | |
36 | )\r | |
37 | {\r | |
449a6e49 TL |
38 | VOID *GhcbBase;\r |
39 | PHYSICAL_ADDRESS GhcbBasePa;\r | |
40 | UINTN GhcbPageCount, PageCount;\r | |
41 | RETURN_STATUS PcdStatus, DecryptStatus;\r | |
13ed9e5f TL |
42 | IA32_DESCRIPTOR Gdtr;\r |
43 | VOID *Gdt;\r | |
cf845a74 TL |
44 | \r |
45 | if (!MemEncryptSevEsIsEnabled ()) {\r | |
46 | return;\r | |
47 | }\r | |
48 | \r | |
49 | PcdStatus = PcdSetBoolS (PcdSevEsIsEnabled, TRUE);\r | |
50 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
449a6e49 TL |
51 | \r |
52 | //\r | |
53 | // Allocate GHCB and per-CPU variable pages.\r | |
54 | //\r | |
55 | GhcbPageCount = mMaxCpuCount * 2;\r | |
56 | GhcbBase = AllocatePages (GhcbPageCount);\r | |
57 | ASSERT (GhcbBase != NULL);\r | |
58 | \r | |
59 | GhcbBasePa = (PHYSICAL_ADDRESS)(UINTN) GhcbBase;\r | |
60 | \r | |
61 | //\r | |
62 | // Each vCPU gets two consecutive pages, the first is the GHCB and the\r | |
63 | // second is the per-CPU variable page. Loop through the allocation and\r | |
64 | // only clear the encryption mask for the GHCB pages.\r | |
65 | //\r | |
66 | for (PageCount = 0; PageCount < GhcbPageCount; PageCount += 2) {\r | |
67 | DecryptStatus = MemEncryptSevClearPageEncMask (\r | |
68 | 0,\r | |
69 | GhcbBasePa + EFI_PAGES_TO_SIZE (PageCount),\r | |
70 | 1,\r | |
71 | TRUE\r | |
72 | );\r | |
73 | ASSERT_RETURN_ERROR (DecryptStatus);\r | |
74 | }\r | |
75 | \r | |
76 | ZeroMem (GhcbBase, EFI_PAGES_TO_SIZE (GhcbPageCount));\r | |
77 | \r | |
78 | PcdStatus = PcdSet64S (PcdGhcbBase, GhcbBasePa);\r | |
79 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
80 | PcdStatus = PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount));\r | |
81 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
82 | \r | |
83 | DEBUG ((DEBUG_INFO,\r | |
84 | "SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n",\r | |
85 | (UINT64)GhcbPageCount, GhcbBase));\r | |
86 | \r | |
87 | AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa);\r | |
13ed9e5f TL |
88 | \r |
89 | //\r | |
90 | // The SEV support will clear the C-bit from non-RAM areas. The early GDT\r | |
91 | // lives in a non-RAM area, so when an exception occurs (like a #VC) the GDT\r | |
92 | // will be read as un-encrypted even though it was created before the C-bit\r | |
93 | // was cleared (encrypted). This will result in a failure to be able to\r | |
94 | // handle the exception.\r | |
95 | //\r | |
96 | AsmReadGdtr (&Gdtr);\r | |
97 | \r | |
98 | Gdt = AllocatePages (EFI_SIZE_TO_PAGES ((UINTN) Gdtr.Limit + 1));\r | |
99 | ASSERT (Gdt != NULL);\r | |
100 | \r | |
101 | CopyMem (Gdt, (VOID *) Gdtr.Base, Gdtr.Limit + 1);\r | |
102 | Gdtr.Base = (UINTN) Gdt;\r | |
103 | AsmWriteGdtr (&Gdtr);\r | |
cf845a74 TL |
104 | }\r |
105 | \r | |
13b5d743 BS |
106 | /**\r |
107 | \r | |
108 | Function checks if SEV support is available, if present then it sets\r | |
109 | the dynamic PcdPteMemoryEncryptionAddressOrMask with memory encryption mask.\r | |
110 | \r | |
111 | **/\r | |
112 | VOID\r | |
13b5d743 BS |
113 | AmdSevInitialize (\r |
114 | VOID\r | |
115 | )\r | |
116 | {\r | |
117 | CPUID_MEMORY_ENCRYPTION_INFO_EBX Ebx;\r | |
118 | UINT64 EncryptionMask;\r | |
119 | RETURN_STATUS PcdStatus;\r | |
120 | \r | |
121 | //\r | |
122 | // Check if SEV is enabled\r | |
123 | //\r | |
124 | if (!MemEncryptSevIsEnabled ()) {\r | |
125 | return;\r | |
126 | }\r | |
127 | \r | |
128 | //\r | |
129 | // CPUID Fn8000_001F[EBX] Bit 0:5 (memory encryption bit position)\r | |
130 | //\r | |
131 | AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, NULL, &Ebx.Uint32, NULL, NULL);\r | |
132 | EncryptionMask = LShiftU64 (1, Ebx.Bits.PtePosBits);\r | |
133 | \r | |
134 | //\r | |
135 | // Set Memory Encryption Mask PCD\r | |
136 | //\r | |
137 | PcdStatus = PcdSet64S (PcdPteMemoryEncryptionAddressOrMask, EncryptionMask);\r | |
138 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
139 | \r | |
140 | DEBUG ((DEBUG_INFO, "SEV is enabled (mask 0x%lx)\n", EncryptionMask));\r | |
6041ac65 BS |
141 | \r |
142 | //\r | |
143 | // Set Pcd to Deny the execution of option ROM when security\r | |
144 | // violation.\r | |
145 | //\r | |
146 | PcdStatus = PcdSet32S (PcdOptionRomImageVerificationPolicy, 0x4);\r | |
147 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
86defc2c LE |
148 | \r |
149 | //\r | |
150 | // When SMM is required, cover the pages containing the initial SMRAM Save\r | |
151 | // State Map with a memory allocation HOB:\r | |
152 | //\r | |
153 | // There's going to be a time interval between our decrypting those pages for\r | |
154 | // SMBASE relocation and re-encrypting the same pages after SMBASE\r | |
155 | // relocation. We shall ensure that the DXE phase stay away from those pages\r | |
156 | // until after re-encryption, in order to prevent an information leak to the\r | |
157 | // hypervisor.\r | |
158 | //\r | |
159 | if (FeaturePcdGet (PcdSmmSmramRequire) && (mBootMode != BOOT_ON_S3_RESUME)) {\r | |
160 | RETURN_STATUS LocateMapStatus;\r | |
161 | UINTN MapPagesBase;\r | |
162 | UINTN MapPagesCount;\r | |
163 | \r | |
164 | LocateMapStatus = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r | |
165 | &MapPagesBase,\r | |
166 | &MapPagesCount\r | |
167 | );\r | |
168 | ASSERT_RETURN_ERROR (LocateMapStatus);\r | |
169 | \r | |
300aae11 LE |
170 | if (mQ35SmramAtDefaultSmbase) {\r |
171 | //\r | |
172 | // The initial SMRAM Save State Map has been covered as part of a larger\r | |
173 | // reserved memory allocation in InitializeRamRegions().\r | |
174 | //\r | |
175 | ASSERT (SMM_DEFAULT_SMBASE <= MapPagesBase);\r | |
176 | ASSERT (\r | |
177 | (MapPagesBase + EFI_PAGES_TO_SIZE (MapPagesCount) <=\r | |
178 | SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE)\r | |
179 | );\r | |
180 | } else {\r | |
181 | BuildMemoryAllocationHob (\r | |
182 | MapPagesBase, // BaseAddress\r | |
183 | EFI_PAGES_TO_SIZE (MapPagesCount), // Length\r | |
184 | EfiBootServicesData // MemoryType\r | |
185 | );\r | |
186 | }\r | |
86defc2c | 187 | }\r |
cf845a74 TL |
188 | \r |
189 | //\r | |
190 | // Check and perform SEV-ES initialization if required.\r | |
191 | //\r | |
192 | AmdSevEsInitialize ();\r | |
13b5d743 | 193 | }\r |