]>
Commit | Line | Data |
---|---|---|
13b5d743 BS |
1 | /**@file\r |
2 | Initialize Secure Encrypted Virtualization (SEV) support\r | |
3 | \r | |
45388d04 | 4 | Copyright (c) 2017 - 2020, Advanced Micro Devices. All rights reserved.<BR>\r |
13b5d743 | 5 | \r |
b26f0cf9 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
13b5d743 BS |
7 | \r |
8 | **/\r | |
9 | //\r | |
10 | // The package level header files this module uses\r | |
11 | //\r | |
300aae11 | 12 | #include <IndustryStandard/Q35MchIch9.h>\r |
449a6e49 | 13 | #include <Library/BaseMemoryLib.h>\r |
13b5d743 | 14 | #include <Library/DebugLib.h>\r |
86defc2c | 15 | #include <Library/HobLib.h>\r |
6d576e7a | 16 | #include <Library/MemEncryptSevLib.h>\r |
449a6e49 | 17 | #include <Library/MemoryAllocationLib.h>\r |
13b5d743 | 18 | #include <Library/PcdLib.h>\r |
6d576e7a | 19 | #include <PiPei.h>\r |
449a6e49 | 20 | #include <Register/Amd/Msr.h>\r |
300aae11 | 21 | #include <Register/Intel/SmramSaveStateMap.h>\r |
13b5d743 | 22 | \r |
c0d221a3 LE |
23 | #include "Platform.h"\r |
24 | \r | |
cf845a74 TL |
25 | /**\r |
26 | \r | |
27 | Initialize SEV-ES support if running as an SEV-ES guest.\r | |
28 | \r | |
29 | **/\r | |
30 | STATIC\r | |
31 | VOID\r | |
32 | AmdSevEsInitialize (\r | |
33 | VOID\r | |
34 | )\r | |
35 | {\r | |
5667dc43 TL |
36 | UINT8 *GhcbBase;\r |
37 | PHYSICAL_ADDRESS GhcbBasePa;\r | |
38 | UINTN GhcbPageCount;\r | |
39 | UINT8 *GhcbBackupBase;\r | |
40 | UINT8 *GhcbBackupPages;\r | |
41 | UINTN GhcbBackupPageCount;\r | |
42 | SEV_ES_PER_CPU_DATA *SevEsData;\r | |
43 | UINTN PageCount;\r | |
44 | RETURN_STATUS PcdStatus, DecryptStatus;\r | |
45 | IA32_DESCRIPTOR Gdtr;\r | |
46 | VOID *Gdt;\r | |
cf845a74 TL |
47 | \r |
48 | if (!MemEncryptSevEsIsEnabled ()) {\r | |
49 | return;\r | |
50 | }\r | |
51 | \r | |
52 | PcdStatus = PcdSetBoolS (PcdSevEsIsEnabled, TRUE);\r | |
53 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
449a6e49 TL |
54 | \r |
55 | //\r | |
56 | // Allocate GHCB and per-CPU variable pages.\r | |
3b49d0a5 TL |
57 | // Since the pages must survive across the UEFI to OS transition\r |
58 | // make them reserved.\r | |
449a6e49 TL |
59 | //\r |
60 | GhcbPageCount = mMaxCpuCount * 2;\r | |
3b49d0a5 | 61 | GhcbBase = AllocateReservedPages (GhcbPageCount);\r |
449a6e49 TL |
62 | ASSERT (GhcbBase != NULL);\r |
63 | \r | |
64 | GhcbBasePa = (PHYSICAL_ADDRESS)(UINTN) GhcbBase;\r | |
65 | \r | |
66 | //\r | |
67 | // Each vCPU gets two consecutive pages, the first is the GHCB and the\r | |
68 | // second is the per-CPU variable page. Loop through the allocation and\r | |
69 | // only clear the encryption mask for the GHCB pages.\r | |
70 | //\r | |
71 | for (PageCount = 0; PageCount < GhcbPageCount; PageCount += 2) {\r | |
72 | DecryptStatus = MemEncryptSevClearPageEncMask (\r | |
73 | 0,\r | |
74 | GhcbBasePa + EFI_PAGES_TO_SIZE (PageCount),\r | |
adfa3327 | 75 | 1\r |
449a6e49 TL |
76 | );\r |
77 | ASSERT_RETURN_ERROR (DecryptStatus);\r | |
78 | }\r | |
79 | \r | |
80 | ZeroMem (GhcbBase, EFI_PAGES_TO_SIZE (GhcbPageCount));\r | |
81 | \r | |
82 | PcdStatus = PcdSet64S (PcdGhcbBase, GhcbBasePa);\r | |
83 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
84 | PcdStatus = PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount));\r | |
85 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
86 | \r | |
87 | DEBUG ((DEBUG_INFO,\r | |
88 | "SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n",\r | |
89 | (UINT64)GhcbPageCount, GhcbBase));\r | |
90 | \r | |
5667dc43 TL |
91 | //\r |
92 | // Allocate #VC recursion backup pages. The number of backup pages needed is\r | |
93 | // one less than the maximum VC count.\r | |
94 | //\r | |
95 | GhcbBackupPageCount = mMaxCpuCount * (VMGEXIT_MAXIMUM_VC_COUNT - 1);\r | |
96 | GhcbBackupBase = AllocatePages (GhcbBackupPageCount);\r | |
97 | ASSERT (GhcbBackupBase != NULL);\r | |
98 | \r | |
99 | GhcbBackupPages = GhcbBackupBase;\r | |
100 | for (PageCount = 1; PageCount < GhcbPageCount; PageCount += 2) {\r | |
101 | SevEsData =\r | |
102 | (SEV_ES_PER_CPU_DATA *)(GhcbBase + EFI_PAGES_TO_SIZE (PageCount));\r | |
103 | SevEsData->GhcbBackupPages = GhcbBackupPages;\r | |
104 | \r | |
105 | GhcbBackupPages += EFI_PAGE_SIZE * (VMGEXIT_MAXIMUM_VC_COUNT - 1);\r | |
106 | }\r | |
107 | \r | |
108 | DEBUG ((DEBUG_INFO,\r | |
109 | "SEV-ES is enabled, %lu GHCB backup pages allocated starting at 0x%p\n",\r | |
110 | (UINT64)GhcbBackupPageCount, GhcbBackupBase));\r | |
111 | \r | |
449a6e49 | 112 | AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa);\r |
13ed9e5f TL |
113 | \r |
114 | //\r | |
115 | // The SEV support will clear the C-bit from non-RAM areas. The early GDT\r | |
116 | // lives in a non-RAM area, so when an exception occurs (like a #VC) the GDT\r | |
117 | // will be read as un-encrypted even though it was created before the C-bit\r | |
118 | // was cleared (encrypted). This will result in a failure to be able to\r | |
119 | // handle the exception.\r | |
120 | //\r | |
121 | AsmReadGdtr (&Gdtr);\r | |
122 | \r | |
123 | Gdt = AllocatePages (EFI_SIZE_TO_PAGES ((UINTN) Gdtr.Limit + 1));\r | |
124 | ASSERT (Gdt != NULL);\r | |
125 | \r | |
126 | CopyMem (Gdt, (VOID *) Gdtr.Base, Gdtr.Limit + 1);\r | |
127 | Gdtr.Base = (UINTN) Gdt;\r | |
128 | AsmWriteGdtr (&Gdtr);\r | |
cf845a74 TL |
129 | }\r |
130 | \r | |
13b5d743 BS |
131 | /**\r |
132 | \r | |
133 | Function checks if SEV support is available, if present then it sets\r | |
134 | the dynamic PcdPteMemoryEncryptionAddressOrMask with memory encryption mask.\r | |
135 | \r | |
136 | **/\r | |
137 | VOID\r | |
13b5d743 BS |
138 | AmdSevInitialize (\r |
139 | VOID\r | |
140 | )\r | |
141 | {\r | |
13b5d743 BS |
142 | UINT64 EncryptionMask;\r |
143 | RETURN_STATUS PcdStatus;\r | |
144 | \r | |
145 | //\r | |
146 | // Check if SEV is enabled\r | |
147 | //\r | |
148 | if (!MemEncryptSevIsEnabled ()) {\r | |
149 | return;\r | |
150 | }\r | |
151 | \r | |
13b5d743 BS |
152 | //\r |
153 | // Set Memory Encryption Mask PCD\r | |
154 | //\r | |
45388d04 | 155 | EncryptionMask = MemEncryptSevGetEncryptionMask ();\r |
13b5d743 BS |
156 | PcdStatus = PcdSet64S (PcdPteMemoryEncryptionAddressOrMask, EncryptionMask);\r |
157 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
158 | \r | |
159 | DEBUG ((DEBUG_INFO, "SEV is enabled (mask 0x%lx)\n", EncryptionMask));\r | |
6041ac65 BS |
160 | \r |
161 | //\r | |
162 | // Set Pcd to Deny the execution of option ROM when security\r | |
163 | // violation.\r | |
164 | //\r | |
165 | PcdStatus = PcdSet32S (PcdOptionRomImageVerificationPolicy, 0x4);\r | |
166 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
86defc2c LE |
167 | \r |
168 | //\r | |
169 | // When SMM is required, cover the pages containing the initial SMRAM Save\r | |
170 | // State Map with a memory allocation HOB:\r | |
171 | //\r | |
172 | // There's going to be a time interval between our decrypting those pages for\r | |
173 | // SMBASE relocation and re-encrypting the same pages after SMBASE\r | |
174 | // relocation. We shall ensure that the DXE phase stay away from those pages\r | |
175 | // until after re-encryption, in order to prevent an information leak to the\r | |
176 | // hypervisor.\r | |
177 | //\r | |
178 | if (FeaturePcdGet (PcdSmmSmramRequire) && (mBootMode != BOOT_ON_S3_RESUME)) {\r | |
179 | RETURN_STATUS LocateMapStatus;\r | |
180 | UINTN MapPagesBase;\r | |
181 | UINTN MapPagesCount;\r | |
182 | \r | |
183 | LocateMapStatus = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r | |
184 | &MapPagesBase,\r | |
185 | &MapPagesCount\r | |
186 | );\r | |
187 | ASSERT_RETURN_ERROR (LocateMapStatus);\r | |
188 | \r | |
300aae11 LE |
189 | if (mQ35SmramAtDefaultSmbase) {\r |
190 | //\r | |
191 | // The initial SMRAM Save State Map has been covered as part of a larger\r | |
192 | // reserved memory allocation in InitializeRamRegions().\r | |
193 | //\r | |
194 | ASSERT (SMM_DEFAULT_SMBASE <= MapPagesBase);\r | |
195 | ASSERT (\r | |
196 | (MapPagesBase + EFI_PAGES_TO_SIZE (MapPagesCount) <=\r | |
197 | SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE)\r | |
198 | );\r | |
199 | } else {\r | |
200 | BuildMemoryAllocationHob (\r | |
201 | MapPagesBase, // BaseAddress\r | |
202 | EFI_PAGES_TO_SIZE (MapPagesCount), // Length\r | |
203 | EfiBootServicesData // MemoryType\r | |
204 | );\r | |
205 | }\r | |
86defc2c | 206 | }\r |
cf845a74 TL |
207 | \r |
208 | //\r | |
209 | // Check and perform SEV-ES initialization if required.\r | |
210 | //\r | |
211 | AmdSevEsInitialize ();\r | |
13b5d743 | 212 | }\r |