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49ba9447 | 1 | /**@file\r |
2 | Memory Detection for Virtual Machines.\r | |
3 | \r | |
4b455f7b | 4 | Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r |
56d7640a | 5 | This program and the accompanying materials\r |
49ba9447 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | Module Name:\r | |
14 | \r | |
15 | MemDetect.c\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | //\r | |
20 | // The package level header files this module uses\r | |
21 | //\r | |
22 | #include <PiPei.h>\r | |
23 | \r | |
24 | //\r | |
25 | // The Library classes this module consumes\r | |
26 | //\r | |
6a7cba79 | 27 | #include <Library/BaseMemoryLib.h>\r |
49ba9447 | 28 | #include <Library/DebugLib.h>\r |
29 | #include <Library/HobLib.h>\r | |
30 | #include <Library/IoLib.h>\r | |
c1c2669c | 31 | #include <Library/PcdLib.h>\r |
49ba9447 | 32 | #include <Library/PeimEntryPoint.h>\r |
33 | #include <Library/ResourcePublicationLib.h>\r | |
e8e5cd4a | 34 | #include <Library/MtrrLib.h>\r |
49ba9447 | 35 | \r |
36 | #include "Platform.h"\r | |
37 | #include "Cmos.h"\r | |
38 | \r | |
bc89fe48 LE |
39 | UINT8 mPhysMemAddressWidth;\r |
40 | \r | |
4b455f7b | 41 | UINT32\r |
c0e10976 | 42 | GetSystemMemorySizeBelow4gb (\r |
4b455f7b | 43 | VOID\r |
49ba9447 | 44 | )\r |
45 | {\r | |
46 | UINT8 Cmos0x34;\r | |
47 | UINT8 Cmos0x35;\r | |
48 | \r | |
49 | //\r | |
50 | // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r | |
51 | // * CMOS(0x35) is the high byte\r | |
52 | // * CMOS(0x34) is the low byte\r | |
53 | // * The size is specified in 64kb chunks\r | |
54 | // * Since this is memory above 16MB, the 16MB must be added\r | |
55 | // into the calculation to get the total memory size.\r | |
56 | //\r | |
57 | \r | |
58 | Cmos0x34 = (UINT8) CmosRead8 (0x34);\r | |
59 | Cmos0x35 = (UINT8) CmosRead8 (0x35);\r | |
60 | \r | |
c4046161 | 61 | return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r |
49ba9447 | 62 | }\r |
63 | \r | |
64 | \r | |
c0e10976 | 65 | STATIC\r |
66 | UINT64\r | |
67 | GetSystemMemorySizeAbove4gb (\r | |
68 | )\r | |
69 | {\r | |
70 | UINT32 Size;\r | |
71 | UINTN CmosIndex;\r | |
72 | \r | |
73 | //\r | |
74 | // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r | |
75 | // * CMOS(0x5d) is the most significant size byte\r | |
76 | // * CMOS(0x5c) is the middle size byte\r | |
77 | // * CMOS(0x5b) is the least significant size byte\r | |
78 | // * The size is specified in 64kb chunks\r | |
79 | //\r | |
80 | \r | |
81 | Size = 0;\r | |
82 | for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r | |
83 | Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r | |
84 | }\r | |
85 | \r | |
86 | return LShiftU64 (Size, 16);\r | |
87 | }\r | |
88 | \r | |
bc89fe48 LE |
89 | \r |
90 | /**\r | |
91 | Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r | |
92 | **/\r | |
93 | VOID\r | |
94 | AddressWidthInitialization (\r | |
95 | VOID\r | |
96 | )\r | |
97 | {\r | |
98 | UINT64 FirstNonAddress;\r | |
99 | \r | |
100 | //\r | |
101 | // As guest-physical memory size grows, the permanent PEI RAM requirements\r | |
102 | // are dominated by the identity-mapping page tables built by the DXE IPL.\r | |
103 | // The DXL IPL keys off of the physical address bits advertized in the CPU\r | |
104 | // HOB. To conserve memory, we calculate the minimum address width here.\r | |
105 | //\r | |
106 | FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r | |
107 | mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r | |
108 | \r | |
109 | //\r | |
110 | // If FirstNonAddress is not an integral power of two, then we need an\r | |
111 | // additional bit.\r | |
112 | //\r | |
113 | if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r | |
114 | ++mPhysMemAddressWidth;\r | |
115 | }\r | |
116 | \r | |
117 | //\r | |
118 | // The minimum address width is 36 (covers up to and excluding 64 GB, which\r | |
119 | // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r | |
120 | // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r | |
121 | // can simply assert that here, since 48 bits are good enough for 256 TB.\r | |
122 | //\r | |
123 | if (mPhysMemAddressWidth <= 36) {\r | |
124 | mPhysMemAddressWidth = 36;\r | |
125 | }\r | |
126 | ASSERT (mPhysMemAddressWidth <= 48);\r | |
127 | }\r | |
128 | \r | |
129 | \r | |
130 | /**\r | |
131 | Calculate the cap for the permanent PEI memory.\r | |
132 | **/\r | |
133 | STATIC\r | |
134 | UINT32\r | |
135 | GetPeiMemoryCap (\r | |
136 | VOID\r | |
137 | )\r | |
138 | {\r | |
139 | BOOLEAN Page1GSupport;\r | |
140 | UINT32 RegEax;\r | |
141 | UINT32 RegEdx;\r | |
142 | UINT32 Pml4Entries;\r | |
143 | UINT32 PdpEntries;\r | |
144 | UINTN TotalPages;\r | |
145 | \r | |
146 | //\r | |
147 | // If DXE is 32-bit, then just return the traditional 64 MB cap.\r | |
148 | //\r | |
149 | #ifdef MDE_CPU_IA32\r | |
150 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r | |
151 | return SIZE_64MB;\r | |
152 | }\r | |
153 | #endif\r | |
154 | \r | |
155 | //\r | |
156 | // Dependent on physical address width, PEI memory allocations can be\r | |
157 | // dominated by the page tables built for 64-bit DXE. So we key the cap off\r | |
158 | // of those. The code below is based on CreateIdentityMappingPageTables() in\r | |
159 | // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r | |
160 | //\r | |
161 | Page1GSupport = FALSE;\r | |
162 | if (PcdGetBool (PcdUse1GPageTable)) {\r | |
163 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
164 | if (RegEax >= 0x80000001) {\r | |
165 | AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r | |
166 | if ((RegEdx & BIT26) != 0) {\r | |
167 | Page1GSupport = TRUE;\r | |
168 | }\r | |
169 | }\r | |
170 | }\r | |
171 | \r | |
172 | if (mPhysMemAddressWidth <= 39) {\r | |
173 | Pml4Entries = 1;\r | |
174 | PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r | |
175 | ASSERT (PdpEntries <= 0x200);\r | |
176 | } else {\r | |
177 | Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r | |
178 | ASSERT (Pml4Entries <= 0x200);\r | |
179 | PdpEntries = 512;\r | |
180 | }\r | |
181 | \r | |
182 | TotalPages = Page1GSupport ? Pml4Entries + 1 :\r | |
183 | (PdpEntries + 1) * Pml4Entries + 1;\r | |
184 | ASSERT (TotalPages <= 0x40201);\r | |
185 | \r | |
186 | //\r | |
187 | // Add 64 MB for miscellaneous allocations. Note that for\r | |
188 | // mPhysMemAddressWidth values close to 36, the cap will actually be\r | |
189 | // dominated by this increment.\r | |
190 | //\r | |
191 | return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r | |
192 | }\r | |
193 | \r | |
194 | \r | |
36658fff WL |
195 | /**\r |
196 | Publish PEI core memory\r | |
197 | \r | |
198 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
199 | \r | |
200 | **/\r | |
201 | EFI_STATUS\r | |
202 | PublishPeiMemory (\r | |
203 | VOID\r | |
204 | )\r | |
205 | {\r | |
206 | EFI_STATUS Status;\r | |
207 | EFI_PHYSICAL_ADDRESS MemoryBase;\r | |
208 | UINT64 MemorySize;\r | |
209 | UINT64 LowerMemorySize;\r | |
bc89fe48 | 210 | UINT32 PeiMemoryCap;\r |
36658fff | 211 | \r |
8e54500f JJ |
212 | if (mBootMode == BOOT_ON_S3_RESUME) {\r |
213 | MemoryBase = PcdGet32 (PcdS3AcpiReservedMemoryBase);\r | |
214 | MemorySize = PcdGet32 (PcdS3AcpiReservedMemorySize);\r | |
215 | } else {\r | |
216 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r | |
b09c1c6f LE |
217 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r |
218 | //\r | |
219 | // TSEG is chipped from the end of low RAM\r | |
220 | //\r | |
221 | LowerMemorySize -= FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;\r | |
222 | }\r | |
8e54500f | 223 | \r |
bc89fe48 LE |
224 | PeiMemoryCap = GetPeiMemoryCap ();\r |
225 | DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r | |
226 | __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r | |
227 | \r | |
8e54500f JJ |
228 | //\r |
229 | // Determine the range of memory to use during PEI\r | |
230 | //\r | |
efb0f16e LE |
231 | // Technically we could lay the permanent PEI RAM over SEC's temporary\r |
232 | // decompression and scratch buffer even if "secure S3" is needed, since\r | |
233 | // their lifetimes don't overlap. However, PeiFvInitialization() will cover\r | |
234 | // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory\r | |
235 | // allocation HOB, and other allocations served from the permanent PEI RAM\r | |
236 | // shouldn't overlap with that HOB.\r | |
237 | //\r | |
238 | MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r | |
239 | PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r | |
240 | PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r | |
8e54500f | 241 | MemorySize = LowerMemorySize - MemoryBase;\r |
bc89fe48 LE |
242 | if (MemorySize > PeiMemoryCap) {\r |
243 | MemoryBase = LowerMemorySize - PeiMemoryCap;\r | |
244 | MemorySize = PeiMemoryCap;\r | |
8e54500f | 245 | }\r |
36658fff WL |
246 | }\r |
247 | \r | |
248 | //\r | |
249 | // Publish this memory to the PEI Core\r | |
250 | //\r | |
251 | Status = PublishSystemMemory(MemoryBase, MemorySize);\r | |
252 | ASSERT_EFI_ERROR (Status);\r | |
253 | \r | |
254 | return Status;\r | |
255 | }\r | |
256 | \r | |
c0e10976 | 257 | \r |
49ba9447 | 258 | /**\r |
c034906e | 259 | Peform Memory Detection for QEMU / KVM\r |
49ba9447 | 260 | \r |
261 | **/\r | |
c034906e JJ |
262 | STATIC\r |
263 | VOID\r | |
264 | QemuInitializeRam (\r | |
265 | VOID\r | |
49ba9447 | 266 | )\r |
267 | {\r | |
c0e10976 | 268 | UINT64 LowerMemorySize;\r |
269 | UINT64 UpperMemorySize;\r | |
79d274b8 LE |
270 | MTRR_SETTINGS MtrrSettings;\r |
271 | EFI_STATUS Status;\r | |
49ba9447 | 272 | \r |
c034906e | 273 | DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));\r |
49ba9447 | 274 | \r |
275 | //\r | |
276 | // Determine total memory size available\r | |
277 | //\r | |
c0e10976 | 278 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r |
279 | UpperMemorySize = GetSystemMemorySizeAbove4gb ();\r | |
49ba9447 | 280 | \r |
bd386eaf JJ |
281 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
282 | //\r | |
283 | // Create memory HOBs\r | |
284 | //\r | |
bd386eaf | 285 | AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r |
b09c1c6f LE |
286 | \r |
287 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
288 | UINT32 TsegSize;\r | |
289 | \r | |
290 | TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;\r | |
291 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r | |
292 | AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,\r | |
293 | TRUE);\r | |
294 | } else {\r | |
295 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r | |
296 | }\r | |
297 | \r | |
cfc80e2e LE |
298 | if (UpperMemorySize != 0) {\r |
299 | AddUntestedMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r | |
300 | }\r | |
bd386eaf | 301 | }\r |
49ba9447 | 302 | \r |
79d274b8 LE |
303 | //\r |
304 | // We'd like to keep the following ranges uncached:\r | |
305 | // - [640 KB, 1 MB)\r | |
306 | // - [LowerMemorySize, 4 GB)\r | |
307 | //\r | |
308 | // Everything else should be WB. Unfortunately, programming the inverse (ie.\r | |
309 | // keeping the default UC, and configuring the complement set of the above as\r | |
310 | // WB) is not reliable in general, because the end of the upper RAM can have\r | |
311 | // practically any alignment, and we may not have enough variable MTRRs to\r | |
312 | // cover it exactly.\r | |
313 | //\r | |
314 | if (IsMtrrSupported ()) {\r | |
315 | MtrrGetAllMtrrs (&MtrrSettings);\r | |
316 | \r | |
317 | //\r | |
318 | // MTRRs disabled, fixed MTRRs disabled, default type is uncached\r | |
319 | //\r | |
320 | ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);\r | |
321 | ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);\r | |
322 | ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);\r | |
323 | \r | |
324 | //\r | |
325 | // flip default type to writeback\r | |
326 | //\r | |
327 | SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);\r | |
328 | ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);\r | |
329 | MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;\r | |
330 | MtrrSetAllMtrrs (&MtrrSettings);\r | |
e8e5cd4a | 331 | \r |
79d274b8 LE |
332 | //\r |
333 | // Set memory range from 640KB to 1MB to uncacheable\r | |
334 | //\r | |
335 | Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,\r | |
336 | BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);\r | |
337 | ASSERT_EFI_ERROR (Status);\r | |
e8e5cd4a | 338 | \r |
79d274b8 LE |
339 | //\r |
340 | // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as\r | |
341 | // uncacheable\r | |
342 | //\r | |
343 | Status = MtrrSetMemoryAttribute (LowerMemorySize,\r | |
344 | SIZE_4GB - LowerMemorySize, CacheUncacheable);\r | |
345 | ASSERT_EFI_ERROR (Status);\r | |
c0e10976 | 346 | }\r |
49ba9447 | 347 | }\r |
348 | \r | |
c034906e JJ |
349 | /**\r |
350 | Publish system RAM and reserve memory regions\r | |
351 | \r | |
352 | **/\r | |
353 | VOID\r | |
354 | InitializeRamRegions (\r | |
355 | VOID\r | |
356 | )\r | |
357 | {\r | |
2818c158 JJ |
358 | if (!mXen) {\r |
359 | QemuInitializeRam ();\r | |
360 | } else {\r | |
2818c158 JJ |
361 | XenPublishRamRegions ();\r |
362 | }\r | |
8e54500f JJ |
363 | \r |
364 | if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {\r | |
365 | //\r | |
366 | // This is the memory range that will be used for PEI on S3 resume\r | |
367 | //\r | |
368 | BuildMemoryAllocationHob (\r | |
369 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdS3AcpiReservedMemoryBase),\r | |
370 | (UINT64)(UINTN) PcdGet32 (PcdS3AcpiReservedMemorySize),\r | |
371 | EfiACPIMemoryNVS\r | |
372 | );\r | |
e249f906 LE |
373 | \r |
374 | //\r | |
375 | // Cover the initial RAM area used as stack and temporary PEI heap.\r | |
376 | //\r | |
377 | // This is reserved as ACPI NVS so it can be used on S3 resume.\r | |
378 | //\r | |
379 | BuildMemoryAllocationHob (\r | |
380 | PcdGet32 (PcdOvmfSecPeiTempRamBase),\r | |
381 | PcdGet32 (PcdOvmfSecPeiTempRamSize),\r | |
382 | EfiACPIMemoryNVS\r | |
383 | );\r | |
78a38b73 | 384 | \r |
ad43bc6b LE |
385 | //\r |
386 | // SEC stores its table of GUIDed section handlers here.\r | |
387 | //\r | |
388 | BuildMemoryAllocationHob (\r | |
389 | PcdGet64 (PcdGuidedExtractHandlerTableAddress),\r | |
390 | PcdGet32 (PcdGuidedExtractHandlerTableSize),\r | |
391 | EfiACPIMemoryNVS\r | |
392 | );\r | |
393 | \r | |
78a38b73 LE |
394 | #ifdef MDE_CPU_X64\r |
395 | //\r | |
396 | // Reserve the initial page tables built by the reset vector code.\r | |
397 | //\r | |
398 | // Since this memory range will be used by the Reset Vector on S3\r | |
399 | // resume, it must be reserved as ACPI NVS.\r | |
400 | //\r | |
401 | BuildMemoryAllocationHob (\r | |
402 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),\r | |
403 | (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),\r | |
404 | EfiACPIMemoryNVS\r | |
405 | );\r | |
406 | #endif\r | |
0e8a31f5 | 407 | }\r |
6a7cba79 | 408 | \r |
0e8a31f5 | 409 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
1a7edbbc LE |
410 | if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r |
411 | //\r | |
412 | // Reserve the lock box storage area\r | |
413 | //\r | |
414 | // Since this memory range will be used on S3 resume, it must be\r | |
415 | // reserved as ACPI NVS.\r | |
416 | //\r | |
417 | // If S3 is unsupported, then various drivers might still write to the\r | |
418 | // LockBox area. We ought to prevent DXE from serving allocation requests\r | |
419 | // such that they would overlap the LockBox storage.\r | |
420 | //\r | |
421 | ZeroMem (\r | |
422 | (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
423 | (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r | |
424 | );\r | |
425 | BuildMemoryAllocationHob (\r | |
426 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
427 | (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r | |
428 | mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r | |
429 | );\r | |
430 | }\r | |
b09c1c6f LE |
431 | \r |
432 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
433 | UINT32 TsegSize;\r | |
434 | \r | |
435 | //\r | |
436 | // Make sure the TSEG area that we reported as a reserved memory resource\r | |
437 | // cannot be used for reserved memory allocations.\r | |
438 | //\r | |
439 | TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;\r | |
440 | BuildMemoryAllocationHob (\r | |
441 | GetSystemMemorySizeBelow4gb() - TsegSize,\r | |
442 | TsegSize,\r | |
443 | EfiReservedMemoryType\r | |
444 | );\r | |
445 | }\r | |
8e54500f | 446 | }\r |
c034906e | 447 | }\r |