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49ba9447 | 1 | /**@file\r |
2 | Memory Detection for Virtual Machines.\r | |
3 | \r | |
035ce3b3 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
56d7640a | 5 | This program and the accompanying materials\r |
49ba9447 | 6 | are licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | Module Name:\r | |
14 | \r | |
15 | MemDetect.c\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | //\r | |
20 | // The package level header files this module uses\r | |
21 | //\r | |
22 | #include <PiPei.h>\r | |
23 | \r | |
24 | //\r | |
25 | // The Library classes this module consumes\r | |
26 | //\r | |
6a7cba79 | 27 | #include <Library/BaseMemoryLib.h>\r |
49ba9447 | 28 | #include <Library/DebugLib.h>\r |
29 | #include <Library/HobLib.h>\r | |
30 | #include <Library/IoLib.h>\r | |
c1c2669c | 31 | #include <Library/PcdLib.h>\r |
49ba9447 | 32 | #include <Library/PeimEntryPoint.h>\r |
33 | #include <Library/ResourcePublicationLib.h>\r | |
e8e5cd4a | 34 | #include <Library/MtrrLib.h>\r |
7e5b1b67 | 35 | #include <Library/QemuFwCfgLib.h>\r |
49ba9447 | 36 | \r |
37 | #include "Platform.h"\r | |
38 | #include "Cmos.h"\r | |
39 | \r | |
bc89fe48 LE |
40 | UINT8 mPhysMemAddressWidth;\r |
41 | \r | |
45d87081 LE |
42 | STATIC UINT32 mS3AcpiReservedMemoryBase;\r |
43 | STATIC UINT32 mS3AcpiReservedMemorySize;\r | |
44 | \r | |
4b455f7b | 45 | UINT32\r |
c0e10976 | 46 | GetSystemMemorySizeBelow4gb (\r |
4b455f7b | 47 | VOID\r |
49ba9447 | 48 | )\r |
49 | {\r | |
50 | UINT8 Cmos0x34;\r | |
51 | UINT8 Cmos0x35;\r | |
52 | \r | |
53 | //\r | |
54 | // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r | |
55 | // * CMOS(0x35) is the high byte\r | |
56 | // * CMOS(0x34) is the low byte\r | |
57 | // * The size is specified in 64kb chunks\r | |
58 | // * Since this is memory above 16MB, the 16MB must be added\r | |
59 | // into the calculation to get the total memory size.\r | |
60 | //\r | |
61 | \r | |
62 | Cmos0x34 = (UINT8) CmosRead8 (0x34);\r | |
63 | Cmos0x35 = (UINT8) CmosRead8 (0x35);\r | |
64 | \r | |
c4046161 | 65 | return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r |
49ba9447 | 66 | }\r |
67 | \r | |
68 | \r | |
c0e10976 | 69 | STATIC\r |
70 | UINT64\r | |
71 | GetSystemMemorySizeAbove4gb (\r | |
72 | )\r | |
73 | {\r | |
74 | UINT32 Size;\r | |
75 | UINTN CmosIndex;\r | |
76 | \r | |
77 | //\r | |
78 | // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r | |
79 | // * CMOS(0x5d) is the most significant size byte\r | |
80 | // * CMOS(0x5c) is the middle size byte\r | |
81 | // * CMOS(0x5b) is the least significant size byte\r | |
82 | // * The size is specified in 64kb chunks\r | |
83 | //\r | |
84 | \r | |
85 | Size = 0;\r | |
86 | for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r | |
87 | Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r | |
88 | }\r | |
89 | \r | |
90 | return LShiftU64 (Size, 16);\r | |
91 | }\r | |
92 | \r | |
bc89fe48 | 93 | \r |
d5371680 LE |
94 | /**\r |
95 | Return the highest address that DXE could possibly use, plus one.\r | |
96 | **/\r | |
97 | STATIC\r | |
98 | UINT64\r | |
99 | GetFirstNonAddress (\r | |
100 | VOID\r | |
101 | )\r | |
102 | {\r | |
103 | UINT64 FirstNonAddress;\r | |
7e5b1b67 LE |
104 | UINT64 Pci64Base, Pci64Size;\r |
105 | CHAR8 MbString[7 + 1];\r | |
106 | EFI_STATUS Status;\r | |
107 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
108 | UINTN FwCfgSize;\r | |
109 | UINT64 HotPlugMemoryEnd;\r | |
d5371680 LE |
110 | \r |
111 | FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r | |
7e5b1b67 LE |
112 | \r |
113 | //\r | |
114 | // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r | |
115 | // resources to 32-bit anyway. See DegradeResource() in\r | |
116 | // "PciResourceSupport.c".\r | |
117 | //\r | |
118 | #ifdef MDE_CPU_IA32\r | |
119 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r | |
120 | return FirstNonAddress;\r | |
121 | }\r | |
122 | #endif\r | |
123 | \r | |
124 | //\r | |
125 | // Otherwise, in order to calculate the highest address plus one, we must\r | |
126 | // consider the 64-bit PCI host aperture too. Fetch the default size.\r | |
127 | //\r | |
128 | Pci64Size = PcdGet64 (PcdPciMmio64Size);\r | |
129 | \r | |
130 | //\r | |
131 | // See if the user specified the number of megabytes for the 64-bit PCI host\r | |
132 | // aperture. The number of non-NUL characters in MbString allows for\r | |
133 | // 9,999,999 MB, which is approximately 10 TB.\r | |
134 | //\r | |
135 | // As signaled by the "X-" prefix, this knob is experimental, and might go\r | |
136 | // away at any time.\r | |
137 | //\r | |
138 | Status = QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem,\r | |
139 | &FwCfgSize);\r | |
140 | if (!EFI_ERROR (Status)) {\r | |
141 | if (FwCfgSize >= sizeof MbString) {\r | |
142 | DEBUG ((EFI_D_WARN,\r | |
143 | "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r | |
144 | __FUNCTION__));\r | |
145 | } else {\r | |
146 | QemuFwCfgSelectItem (FwCfgItem);\r | |
147 | QemuFwCfgReadBytes (FwCfgSize, MbString);\r | |
148 | MbString[FwCfgSize] = '\0';\r | |
149 | Pci64Size = LShiftU64 (AsciiStrDecimalToUint64 (MbString), 20);\r | |
150 | }\r | |
151 | }\r | |
152 | \r | |
153 | if (Pci64Size == 0) {\r | |
154 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
155 | DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n",\r | |
156 | __FUNCTION__));\r | |
157 | PcdSet64 (PcdPciMmio64Size, 0);\r | |
158 | }\r | |
159 | \r | |
160 | //\r | |
161 | // There's nothing more to do; the amount of memory above 4GB fully\r | |
162 | // determines the highest address plus one. The memory hotplug area (see\r | |
163 | // below) plays no role for the firmware in this case.\r | |
164 | //\r | |
165 | return FirstNonAddress;\r | |
166 | }\r | |
167 | \r | |
168 | //\r | |
169 | // The "etc/reserved-memory-end" fw_cfg file, when present, contains an\r | |
170 | // absolute, exclusive end address for the memory hotplug area. This area\r | |
171 | // starts right at the end of the memory above 4GB. The 64-bit PCI host\r | |
172 | // aperture must be placed above it.\r | |
173 | //\r | |
174 | Status = QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem,\r | |
175 | &FwCfgSize);\r | |
176 | if (!EFI_ERROR (Status) && FwCfgSize == sizeof HotPlugMemoryEnd) {\r | |
177 | QemuFwCfgSelectItem (FwCfgItem);\r | |
178 | QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);\r | |
179 | \r | |
180 | ASSERT (HotPlugMemoryEnd >= FirstNonAddress);\r | |
181 | FirstNonAddress = HotPlugMemoryEnd;\r | |
182 | }\r | |
183 | \r | |
184 | //\r | |
185 | // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r | |
186 | // that the host can map it with 1GB hugepages. Follow suit.\r | |
187 | //\r | |
188 | Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r | |
189 | Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);\r | |
190 | \r | |
191 | //\r | |
192 | // The 64-bit PCI host aperture should also be "naturally" aligned. The\r | |
193 | // alignment is determined by rounding the size of the aperture down to the\r | |
194 | // next smaller or equal power of two. That is, align the aperture by the\r | |
195 | // largest BAR size that can fit into it.\r | |
196 | //\r | |
197 | Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));\r | |
198 | \r | |
199 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
200 | //\r | |
201 | // The core PciHostBridgeDxe driver will automatically add this range to\r | |
202 | // the GCD memory space map through our PciHostBridgeLib instance; here we\r | |
203 | // only need to set the PCDs.\r | |
204 | //\r | |
205 | PcdSet64 (PcdPciMmio64Base, Pci64Base);\r | |
206 | PcdSet64 (PcdPciMmio64Size, Pci64Size);\r | |
207 | DEBUG ((EFI_D_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r | |
208 | __FUNCTION__, Pci64Base, Pci64Size));\r | |
209 | }\r | |
210 | \r | |
211 | //\r | |
212 | // The useful address space ends with the 64-bit PCI host aperture.\r | |
213 | //\r | |
214 | FirstNonAddress = Pci64Base + Pci64Size;\r | |
d5371680 LE |
215 | return FirstNonAddress;\r |
216 | }\r | |
217 | \r | |
218 | \r | |
bc89fe48 LE |
219 | /**\r |
220 | Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r | |
221 | **/\r | |
222 | VOID\r | |
223 | AddressWidthInitialization (\r | |
224 | VOID\r | |
225 | )\r | |
226 | {\r | |
227 | UINT64 FirstNonAddress;\r | |
228 | \r | |
229 | //\r | |
230 | // As guest-physical memory size grows, the permanent PEI RAM requirements\r | |
231 | // are dominated by the identity-mapping page tables built by the DXE IPL.\r | |
232 | // The DXL IPL keys off of the physical address bits advertized in the CPU\r | |
233 | // HOB. To conserve memory, we calculate the minimum address width here.\r | |
234 | //\r | |
d5371680 | 235 | FirstNonAddress = GetFirstNonAddress ();\r |
bc89fe48 LE |
236 | mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r |
237 | \r | |
238 | //\r | |
239 | // If FirstNonAddress is not an integral power of two, then we need an\r | |
240 | // additional bit.\r | |
241 | //\r | |
242 | if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r | |
243 | ++mPhysMemAddressWidth;\r | |
244 | }\r | |
245 | \r | |
246 | //\r | |
247 | // The minimum address width is 36 (covers up to and excluding 64 GB, which\r | |
248 | // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r | |
249 | // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r | |
250 | // can simply assert that here, since 48 bits are good enough for 256 TB.\r | |
251 | //\r | |
252 | if (mPhysMemAddressWidth <= 36) {\r | |
253 | mPhysMemAddressWidth = 36;\r | |
254 | }\r | |
255 | ASSERT (mPhysMemAddressWidth <= 48);\r | |
256 | }\r | |
257 | \r | |
258 | \r | |
259 | /**\r | |
260 | Calculate the cap for the permanent PEI memory.\r | |
261 | **/\r | |
262 | STATIC\r | |
263 | UINT32\r | |
264 | GetPeiMemoryCap (\r | |
265 | VOID\r | |
266 | )\r | |
267 | {\r | |
268 | BOOLEAN Page1GSupport;\r | |
269 | UINT32 RegEax;\r | |
270 | UINT32 RegEdx;\r | |
271 | UINT32 Pml4Entries;\r | |
272 | UINT32 PdpEntries;\r | |
273 | UINTN TotalPages;\r | |
274 | \r | |
275 | //\r | |
276 | // If DXE is 32-bit, then just return the traditional 64 MB cap.\r | |
277 | //\r | |
278 | #ifdef MDE_CPU_IA32\r | |
279 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r | |
280 | return SIZE_64MB;\r | |
281 | }\r | |
282 | #endif\r | |
283 | \r | |
284 | //\r | |
285 | // Dependent on physical address width, PEI memory allocations can be\r | |
286 | // dominated by the page tables built for 64-bit DXE. So we key the cap off\r | |
287 | // of those. The code below is based on CreateIdentityMappingPageTables() in\r | |
288 | // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r | |
289 | //\r | |
290 | Page1GSupport = FALSE;\r | |
291 | if (PcdGetBool (PcdUse1GPageTable)) {\r | |
292 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
293 | if (RegEax >= 0x80000001) {\r | |
294 | AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r | |
295 | if ((RegEdx & BIT26) != 0) {\r | |
296 | Page1GSupport = TRUE;\r | |
297 | }\r | |
298 | }\r | |
299 | }\r | |
300 | \r | |
301 | if (mPhysMemAddressWidth <= 39) {\r | |
302 | Pml4Entries = 1;\r | |
303 | PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r | |
304 | ASSERT (PdpEntries <= 0x200);\r | |
305 | } else {\r | |
306 | Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r | |
307 | ASSERT (Pml4Entries <= 0x200);\r | |
308 | PdpEntries = 512;\r | |
309 | }\r | |
310 | \r | |
311 | TotalPages = Page1GSupport ? Pml4Entries + 1 :\r | |
312 | (PdpEntries + 1) * Pml4Entries + 1;\r | |
313 | ASSERT (TotalPages <= 0x40201);\r | |
314 | \r | |
315 | //\r | |
316 | // Add 64 MB for miscellaneous allocations. Note that for\r | |
317 | // mPhysMemAddressWidth values close to 36, the cap will actually be\r | |
318 | // dominated by this increment.\r | |
319 | //\r | |
320 | return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r | |
321 | }\r | |
322 | \r | |
323 | \r | |
36658fff WL |
324 | /**\r |
325 | Publish PEI core memory\r | |
326 | \r | |
327 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
328 | \r | |
329 | **/\r | |
330 | EFI_STATUS\r | |
331 | PublishPeiMemory (\r | |
332 | VOID\r | |
333 | )\r | |
334 | {\r | |
335 | EFI_STATUS Status;\r | |
336 | EFI_PHYSICAL_ADDRESS MemoryBase;\r | |
337 | UINT64 MemorySize;\r | |
fc3f005a | 338 | UINT32 LowerMemorySize;\r |
bc89fe48 | 339 | UINT32 PeiMemoryCap;\r |
36658fff | 340 | \r |
45d87081 LE |
341 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r |
342 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
343 | //\r | |
344 | // TSEG is chipped from the end of low RAM\r | |
345 | //\r | |
346 | LowerMemorySize -= FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;\r | |
347 | }\r | |
348 | \r | |
349 | //\r | |
350 | // If S3 is supported, then the S3 permanent PEI memory is placed next,\r | |
351 | // downwards. Its size is primarily dictated by CpuMpPei. The formula below\r | |
352 | // is an approximation.\r | |
353 | //\r | |
354 | if (mS3Supported) {\r | |
355 | mS3AcpiReservedMemorySize = SIZE_512KB +\r | |
356 | PcdGet32 (PcdCpuMaxLogicalProcessorNumber) *\r | |
357 | PcdGet32 (PcdCpuApStackSize);\r | |
358 | mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;\r | |
359 | LowerMemorySize = mS3AcpiReservedMemoryBase;\r | |
360 | }\r | |
361 | \r | |
8e54500f | 362 | if (mBootMode == BOOT_ON_S3_RESUME) {\r |
45d87081 LE |
363 | MemoryBase = mS3AcpiReservedMemoryBase;\r |
364 | MemorySize = mS3AcpiReservedMemorySize;\r | |
8e54500f | 365 | } else {\r |
bc89fe48 LE |
366 | PeiMemoryCap = GetPeiMemoryCap ();\r |
367 | DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r | |
368 | __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r | |
369 | \r | |
8e54500f JJ |
370 | //\r |
371 | // Determine the range of memory to use during PEI\r | |
372 | //\r | |
efb0f16e LE |
373 | // Technically we could lay the permanent PEI RAM over SEC's temporary\r |
374 | // decompression and scratch buffer even if "secure S3" is needed, since\r | |
375 | // their lifetimes don't overlap. However, PeiFvInitialization() will cover\r | |
376 | // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory\r | |
377 | // allocation HOB, and other allocations served from the permanent PEI RAM\r | |
378 | // shouldn't overlap with that HOB.\r | |
379 | //\r | |
380 | MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r | |
381 | PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r | |
382 | PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r | |
8e54500f | 383 | MemorySize = LowerMemorySize - MemoryBase;\r |
bc89fe48 LE |
384 | if (MemorySize > PeiMemoryCap) {\r |
385 | MemoryBase = LowerMemorySize - PeiMemoryCap;\r | |
386 | MemorySize = PeiMemoryCap;\r | |
8e54500f | 387 | }\r |
36658fff WL |
388 | }\r |
389 | \r | |
390 | //\r | |
391 | // Publish this memory to the PEI Core\r | |
392 | //\r | |
393 | Status = PublishSystemMemory(MemoryBase, MemorySize);\r | |
394 | ASSERT_EFI_ERROR (Status);\r | |
395 | \r | |
396 | return Status;\r | |
397 | }\r | |
398 | \r | |
c0e10976 | 399 | \r |
49ba9447 | 400 | /**\r |
c034906e | 401 | Peform Memory Detection for QEMU / KVM\r |
49ba9447 | 402 | \r |
403 | **/\r | |
c034906e JJ |
404 | STATIC\r |
405 | VOID\r | |
406 | QemuInitializeRam (\r | |
407 | VOID\r | |
49ba9447 | 408 | )\r |
409 | {\r | |
c0e10976 | 410 | UINT64 LowerMemorySize;\r |
411 | UINT64 UpperMemorySize;\r | |
79d274b8 LE |
412 | MTRR_SETTINGS MtrrSettings;\r |
413 | EFI_STATUS Status;\r | |
49ba9447 | 414 | \r |
c034906e | 415 | DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));\r |
49ba9447 | 416 | \r |
417 | //\r | |
418 | // Determine total memory size available\r | |
419 | //\r | |
c0e10976 | 420 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r |
421 | UpperMemorySize = GetSystemMemorySizeAbove4gb ();\r | |
49ba9447 | 422 | \r |
e3e3090a LE |
423 | if (mBootMode == BOOT_ON_S3_RESUME) {\r |
424 | //\r | |
425 | // Create the following memory HOB as an exception on the S3 boot path.\r | |
426 | //\r | |
427 | // Normally we'd create memory HOBs only on the normal boot path. However,\r | |
428 | // CpuMpPei specifically needs such a low-memory HOB on the S3 path as\r | |
429 | // well, for "borrowing" a subset of it temporarily, for the AP startup\r | |
430 | // vector.\r | |
431 | //\r | |
432 | // CpuMpPei saves the original contents of the borrowed area in permanent\r | |
433 | // PEI RAM, in a backup buffer allocated with the normal PEI services.\r | |
434 | // CpuMpPei restores the original contents ("returns" the borrowed area) at\r | |
435 | // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before\r | |
436 | // transfering control to the OS's wakeup vector in the FACS.\r | |
437 | //\r | |
438 | // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to\r | |
439 | // restore the original contents. Furthermore, we expect all such PEIMs\r | |
440 | // (CpuMpPei included) to claim the borrowed areas by producing memory\r | |
441 | // allocation HOBs, and to honor preexistent memory allocation HOBs when\r | |
442 | // looking for an area to borrow.\r | |
443 | //\r | |
444 | AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r | |
445 | } else {\r | |
bd386eaf JJ |
446 | //\r |
447 | // Create memory HOBs\r | |
448 | //\r | |
bd386eaf | 449 | AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r |
b09c1c6f LE |
450 | \r |
451 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
452 | UINT32 TsegSize;\r | |
453 | \r | |
454 | TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;\r | |
455 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r | |
456 | AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,\r | |
457 | TRUE);\r | |
458 | } else {\r | |
459 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r | |
460 | }\r | |
461 | \r | |
cfc80e2e | 462 | if (UpperMemorySize != 0) {\r |
035ce3b3 | 463 | AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r |
cfc80e2e | 464 | }\r |
bd386eaf | 465 | }\r |
49ba9447 | 466 | \r |
79d274b8 LE |
467 | //\r |
468 | // We'd like to keep the following ranges uncached:\r | |
469 | // - [640 KB, 1 MB)\r | |
470 | // - [LowerMemorySize, 4 GB)\r | |
471 | //\r | |
472 | // Everything else should be WB. Unfortunately, programming the inverse (ie.\r | |
473 | // keeping the default UC, and configuring the complement set of the above as\r | |
474 | // WB) is not reliable in general, because the end of the upper RAM can have\r | |
475 | // practically any alignment, and we may not have enough variable MTRRs to\r | |
476 | // cover it exactly.\r | |
477 | //\r | |
478 | if (IsMtrrSupported ()) {\r | |
479 | MtrrGetAllMtrrs (&MtrrSettings);\r | |
480 | \r | |
481 | //\r | |
482 | // MTRRs disabled, fixed MTRRs disabled, default type is uncached\r | |
483 | //\r | |
484 | ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);\r | |
485 | ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);\r | |
486 | ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);\r | |
487 | \r | |
488 | //\r | |
489 | // flip default type to writeback\r | |
490 | //\r | |
491 | SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);\r | |
492 | ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);\r | |
493 | MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;\r | |
494 | MtrrSetAllMtrrs (&MtrrSettings);\r | |
e8e5cd4a | 495 | \r |
79d274b8 LE |
496 | //\r |
497 | // Set memory range from 640KB to 1MB to uncacheable\r | |
498 | //\r | |
499 | Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,\r | |
500 | BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);\r | |
501 | ASSERT_EFI_ERROR (Status);\r | |
e8e5cd4a | 502 | \r |
79d274b8 LE |
503 | //\r |
504 | // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as\r | |
505 | // uncacheable\r | |
506 | //\r | |
507 | Status = MtrrSetMemoryAttribute (LowerMemorySize,\r | |
508 | SIZE_4GB - LowerMemorySize, CacheUncacheable);\r | |
509 | ASSERT_EFI_ERROR (Status);\r | |
c0e10976 | 510 | }\r |
49ba9447 | 511 | }\r |
512 | \r | |
c034906e JJ |
513 | /**\r |
514 | Publish system RAM and reserve memory regions\r | |
515 | \r | |
516 | **/\r | |
517 | VOID\r | |
518 | InitializeRamRegions (\r | |
519 | VOID\r | |
520 | )\r | |
521 | {\r | |
2818c158 JJ |
522 | if (!mXen) {\r |
523 | QemuInitializeRam ();\r | |
524 | } else {\r | |
2818c158 JJ |
525 | XenPublishRamRegions ();\r |
526 | }\r | |
8e54500f JJ |
527 | \r |
528 | if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {\r | |
529 | //\r | |
530 | // This is the memory range that will be used for PEI on S3 resume\r | |
531 | //\r | |
532 | BuildMemoryAllocationHob (\r | |
45d87081 LE |
533 | mS3AcpiReservedMemoryBase,\r |
534 | mS3AcpiReservedMemorySize,\r | |
8e54500f JJ |
535 | EfiACPIMemoryNVS\r |
536 | );\r | |
e249f906 LE |
537 | \r |
538 | //\r | |
539 | // Cover the initial RAM area used as stack and temporary PEI heap.\r | |
540 | //\r | |
541 | // This is reserved as ACPI NVS so it can be used on S3 resume.\r | |
542 | //\r | |
543 | BuildMemoryAllocationHob (\r | |
544 | PcdGet32 (PcdOvmfSecPeiTempRamBase),\r | |
545 | PcdGet32 (PcdOvmfSecPeiTempRamSize),\r | |
546 | EfiACPIMemoryNVS\r | |
547 | );\r | |
78a38b73 | 548 | \r |
ad43bc6b LE |
549 | //\r |
550 | // SEC stores its table of GUIDed section handlers here.\r | |
551 | //\r | |
552 | BuildMemoryAllocationHob (\r | |
553 | PcdGet64 (PcdGuidedExtractHandlerTableAddress),\r | |
554 | PcdGet32 (PcdGuidedExtractHandlerTableSize),\r | |
555 | EfiACPIMemoryNVS\r | |
556 | );\r | |
557 | \r | |
78a38b73 LE |
558 | #ifdef MDE_CPU_X64\r |
559 | //\r | |
560 | // Reserve the initial page tables built by the reset vector code.\r | |
561 | //\r | |
562 | // Since this memory range will be used by the Reset Vector on S3\r | |
563 | // resume, it must be reserved as ACPI NVS.\r | |
564 | //\r | |
565 | BuildMemoryAllocationHob (\r | |
566 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),\r | |
567 | (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),\r | |
568 | EfiACPIMemoryNVS\r | |
569 | );\r | |
570 | #endif\r | |
0e8a31f5 | 571 | }\r |
6a7cba79 | 572 | \r |
0e8a31f5 | 573 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
1a7edbbc LE |
574 | if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r |
575 | //\r | |
576 | // Reserve the lock box storage area\r | |
577 | //\r | |
578 | // Since this memory range will be used on S3 resume, it must be\r | |
579 | // reserved as ACPI NVS.\r | |
580 | //\r | |
581 | // If S3 is unsupported, then various drivers might still write to the\r | |
582 | // LockBox area. We ought to prevent DXE from serving allocation requests\r | |
583 | // such that they would overlap the LockBox storage.\r | |
584 | //\r | |
585 | ZeroMem (\r | |
586 | (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
587 | (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r | |
588 | );\r | |
589 | BuildMemoryAllocationHob (\r | |
590 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
591 | (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r | |
592 | mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r | |
593 | );\r | |
594 | }\r | |
b09c1c6f LE |
595 | \r |
596 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
597 | UINT32 TsegSize;\r | |
598 | \r | |
599 | //\r | |
600 | // Make sure the TSEG area that we reported as a reserved memory resource\r | |
601 | // cannot be used for reserved memory allocations.\r | |
602 | //\r | |
603 | TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB;\r | |
604 | BuildMemoryAllocationHob (\r | |
605 | GetSystemMemorySizeBelow4gb() - TsegSize,\r | |
606 | TsegSize,\r | |
607 | EfiReservedMemoryType\r | |
608 | );\r | |
609 | }\r | |
8e54500f | 610 | }\r |
c034906e | 611 | }\r |