]>
Commit | Line | Data |
---|---|---|
30937f2f TL |
1 | ;------------------------------------------------------------------------------\r |
2 | ; @file\r | |
3 | ; First code executed by processor after resetting.\r | |
4 | ; Derived from UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm\r | |
5 | ;\r | |
6 | ; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
7 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
8 | ;\r | |
9 | ;------------------------------------------------------------------------------\r | |
10 | \r | |
11 | BITS 16\r | |
12 | \r | |
13 | ALIGN 16\r | |
14 | \r | |
15 | ;\r | |
16 | ; Pad the image size to 4k when page tables are in VTF0\r | |
17 | ;\r | |
18 | ; If the VTF0 image has page tables built in, then we need to make\r | |
19 | ; sure the end of VTF0 is 4k above where the page tables end.\r | |
20 | ;\r | |
21 | ; This is required so the page tables will be 4k aligned when VTF0 is\r | |
22 | ; located just below 0x100000000 (4GB) in the firmware device.\r | |
23 | ;\r | |
24 | %ifdef ALIGN_TOP_TO_4K_FOR_PAGING\r | |
25 | TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0\r | |
26 | %endif\r | |
27 | \r | |
ae1ef911 JB |
28 | ;\r |
29 | ; Padding to ensure first guid starts at 0xffffffd0\r | |
30 | ;\r | |
31 | TIMES (15 - ((guidedStructureEnd - guidedStructureStart + 15) % 16)) DB 0\r | |
32 | \r | |
33 | ; GUIDed structure. To traverse this you should first verify the\r | |
34 | ; presence of the table footer guid\r | |
35 | ; (96b582de-1fb2-45f7-baea-a366c55a082d) at 0xffffffd0. If that\r | |
36 | ; is found, the two bytes at 0xffffffce are the entire table length.\r | |
37 | ;\r | |
38 | ; The table is composed of structures with the form:\r | |
39 | ;\r | |
40 | ; Data (arbitrary bytes identified by guid)\r | |
41 | ; length from start of data to end of guid (2 bytes)\r | |
42 | ; guid (16 bytes)\r | |
43 | ;\r | |
44 | ; so work back from the footer using the length to traverse until you\r | |
45 | ; either find the guid you're looking for or run off the beginning of\r | |
46 | ; the table.\r | |
47 | ;\r | |
48 | guidedStructureStart:\r | |
49 | \r | |
30937f2f TL |
50 | ;\r |
51 | ; SEV-ES Processor Reset support\r | |
52 | ;\r | |
53 | ; sevEsResetBlock:\r | |
54 | ; For the initial boot of an AP under SEV-ES, the "reset" RIP must be\r | |
ae1ef911 JB |
55 | ; programmed to the RAM area defined by SEV_ES_AP_RESET_IP. The data\r |
56 | ; format is:\r | |
30937f2f | 57 | ;\r |
ae1ef911 JB |
58 | ; IP value [0:15]\r |
59 | ; CS segment base [31:16]\r | |
60 | ;\r | |
61 | ; GUID (SEV-ES reset block): 00f771de-1a7e-4fcb-890e-68c77e2fb44e\r | |
30937f2f TL |
62 | ;\r |
63 | ; A hypervisor reads the CS segement base and IP value. The CS segment base\r | |
64 | ; value represents the high order 16-bits of the CS segment base, so the\r | |
65 | ; hypervisor must left shift the value of the CS segement base by 16 bits to\r | |
66 | ; form the full CS segment base for the CS segment register. It would then\r | |
67 | ; program the EIP register with the IP value as read.\r | |
68 | ;\r | |
69 | \r | |
30937f2f TL |
70 | sevEsResetBlockStart:\r |
71 | DD SEV_ES_AP_RESET_IP\r | |
72 | DW sevEsResetBlockEnd - sevEsResetBlockStart\r | |
73 | DB 0xDE, 0x71, 0xF7, 0x00, 0x7E, 0x1A, 0xCB, 0x4F\r | |
74 | DB 0x89, 0x0E, 0x68, 0xC7, 0x7E, 0x2F, 0xB4, 0x4E\r | |
75 | sevEsResetBlockEnd:\r | |
76 | \r | |
ae1ef911 JB |
77 | ;\r |
78 | ; Table footer:\r | |
79 | ;\r | |
80 | ; length of whole table (16 bit word)\r | |
81 | ; GUID (table footer): 96b582de-1fb2-45f7-baea-a366c55a082d\r | |
82 | ;\r | |
83 | DW guidedStructureEnd - guidedStructureStart\r | |
84 | DB 0xDE, 0x82, 0xB5, 0x96, 0xB2, 0x1F, 0xF7, 0x45\r | |
85 | DB 0xBA, 0xEA, 0xA3, 0x66, 0xC5, 0x5A, 0x08, 0x2D\r | |
86 | \r | |
87 | guidedStructureEnd:\r | |
88 | \r | |
30937f2f TL |
89 | ALIGN 16\r |
90 | \r | |
91 | applicationProcessorEntryPoint:\r | |
92 | ;\r | |
93 | ; Application Processors entry point\r | |
94 | ;\r | |
95 | ; GenFv generates code aligned on a 4k boundary which will jump to this\r | |
96 | ; location. (0xffffffe0) This allows the Local APIC Startup IPI to be\r | |
97 | ; used to wake up the application processors.\r | |
98 | ;\r | |
99 | jmp EarlyApInitReal16\r | |
100 | \r | |
101 | ALIGN 8\r | |
102 | \r | |
103 | DD 0\r | |
104 | \r | |
105 | ;\r | |
106 | ; The VTF signature\r | |
107 | ;\r | |
108 | ; VTF-0 means that the VTF (Volume Top File) code does not require\r | |
109 | ; any fixups.\r | |
110 | ;\r | |
111 | vtfSignature:\r | |
112 | DB 'V', 'T', 'F', 0\r | |
113 | \r | |
114 | ALIGN 16\r | |
115 | \r | |
116 | resetVector:\r | |
117 | ;\r | |
118 | ; Reset Vector\r | |
119 | ;\r | |
120 | ; This is where the processor will begin execution\r | |
121 | ;\r | |
122 | nop\r | |
123 | nop\r | |
124 | jmp EarlyBspInitReal16\r | |
125 | \r | |
126 | ALIGN 16\r | |
127 | \r | |
128 | fourGigabytes:\r | |
129 | \r |