]>
Commit | Line | Data |
---|---|---|
c90e37b5 JJ |
1 | ;------------------------------------------------------------------------------\r |
2 | ; @file\r | |
3 | ; Sets the CR3 register for 64-bit paging\r | |
4 | ;\r | |
5 | ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r | |
6 | ; This program and the accompanying materials\r | |
7 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
8 | ; which accompanies this distribution. The full text of the license may be found at\r | |
9 | ; http://opensource.org/licenses/bsd-license.php\r | |
10 | ;\r | |
11 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | ;\r | |
14 | ;------------------------------------------------------------------------------\r | |
15 | \r | |
16 | BITS 32\r | |
17 | \r | |
18 | %define PAGE_PRESENT 0x01\r | |
19 | %define PAGE_READ_WRITE 0x02\r | |
20 | %define PAGE_USER_SUPERVISOR 0x04\r | |
21 | %define PAGE_WRITE_THROUGH 0x08\r | |
22 | %define PAGE_CACHE_DISABLE 0x010\r | |
23 | %define PAGE_ACCESSED 0x020\r | |
24 | %define PAGE_DIRTY 0x040\r | |
25 | %define PAGE_PAT 0x080\r | |
26 | %define PAGE_GLOBAL 0x0100\r | |
27 | %define PAGE_2M_MBO 0x080\r | |
28 | %define PAGE_2M_PAT 0x01000\r | |
29 | \r | |
30 | %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \\r | |
c90e37b5 JJ |
31 | PAGE_ACCESSED + \\r |
32 | PAGE_DIRTY + \\r | |
33 | PAGE_READ_WRITE + \\r | |
34 | PAGE_PRESENT)\r | |
35 | \r | |
98f378a7 | 36 | %define PAGE_PDP_ATTR (PAGE_ACCESSED + \\r |
c90e37b5 JJ |
37 | PAGE_READ_WRITE + \\r |
38 | PAGE_PRESENT)\r | |
39 | \r | |
e60af8a1 BS |
40 | ; Check if Secure Encrypted Virtualization (SEV) feature is enabled\r |
41 | ;\r | |
42 | ; If SEV is enabled then EAX will be at least 32\r | |
43 | ; If SEV is disabled then EAX will be zero.\r | |
44 | ;\r | |
45 | CheckSevFeature:\r | |
46 | ; Check if we have a valid (0x8000_001F) CPUID leaf\r | |
47 | mov eax, 0x80000000\r | |
48 | cpuid\r | |
49 | \r | |
50 | ; This check should fail on Intel or Non SEV AMD CPUs. In future if\r | |
51 | ; Intel CPUs supports this CPUID leaf then we are guranteed to have exact\r | |
52 | ; same bit definition.\r | |
53 | cmp eax, 0x8000001f\r | |
54 | jl NoSev\r | |
55 | \r | |
56 | ; Check for memory encryption feature:\r | |
57 | ; CPUID Fn8000_001F[EAX] - Bit 1\r | |
58 | ;\r | |
59 | mov eax, 0x8000001f\r | |
60 | cpuid\r | |
61 | bt eax, 1\r | |
62 | jnc NoSev\r | |
63 | \r | |
64 | ; Check if memory encryption is enabled\r | |
65 | ; MSR_0xC0010131 - Bit 0 (SEV enabled)\r | |
66 | mov ecx, 0xc0010131\r | |
67 | rdmsr\r | |
68 | bt eax, 0\r | |
69 | jnc NoSev\r | |
70 | \r | |
71 | ; Get pte bit position to enable memory encryption\r | |
72 | ; CPUID Fn8000_001F[EBX] - Bits 5:0\r | |
73 | ;\r | |
74 | mov eax, ebx\r | |
75 | and eax, 0x3f\r | |
76 | jmp SevExit\r | |
77 | \r | |
78 | NoSev:\r | |
79 | xor eax, eax\r | |
80 | \r | |
81 | SevExit:\r | |
82 | OneTimeCallRet CheckSevFeature\r | |
c90e37b5 JJ |
83 | \r |
84 | ;\r | |
e60af8a1 | 85 | ; Modified: EAX, EBX, ECX, EDX\r |
c90e37b5 JJ |
86 | ;\r |
87 | SetCr3ForPageTables64:\r | |
88 | \r | |
e60af8a1 BS |
89 | OneTimeCall CheckSevFeature\r |
90 | xor edx, edx\r | |
91 | test eax, eax\r | |
92 | jz SevNotActive\r | |
93 | \r | |
94 | ; If SEV is enabled, C-bit is always above 31\r | |
95 | sub eax, 32\r | |
96 | bts edx, eax\r | |
97 | \r | |
98 | SevNotActive:\r | |
99 | \r | |
c90e37b5 | 100 | ;\r |
73d66c58 MH |
101 | ; For OVMF, build some initial page tables at\r |
102 | ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).\r | |
b382ede3 | 103 | ;\r |
73d66c58 MH |
104 | ; This range should match with PcdOvmfSecPageTablesSize which is\r |
105 | ; declared in the FDF files.\r | |
c90e37b5 JJ |
106 | ;\r |
107 | ; At the end of PEI, the pages tables will be rebuilt into a\r | |
108 | ; more permanent location by DxeIpl.\r | |
109 | ;\r | |
110 | \r | |
111 | mov ecx, 6 * 0x1000 / 4\r | |
112 | xor eax, eax\r | |
113 | clearPageTablesMemoryLoop:\r | |
73d66c58 | 114 | mov dword[ecx * 4 + PT_ADDR (0) - 4], eax\r |
c90e37b5 JJ |
115 | loop clearPageTablesMemoryLoop\r |
116 | \r | |
117 | ;\r | |
118 | ; Top level Page Directory Pointers (1 * 512GB entry)\r | |
119 | ;\r | |
73d66c58 | 120 | mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR\r |
e60af8a1 | 121 | mov dword[PT_ADDR (4)], edx\r |
c90e37b5 JJ |
122 | \r |
123 | ;\r | |
124 | ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)\r | |
125 | ;\r | |
73d66c58 | 126 | mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR\r |
e60af8a1 | 127 | mov dword[PT_ADDR (0x1004)], edx\r |
73d66c58 | 128 | mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR\r |
e60af8a1 | 129 | mov dword[PT_ADDR (0x100C)], edx\r |
73d66c58 | 130 | mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR\r |
e60af8a1 | 131 | mov dword[PT_ADDR (0x1014)], edx\r |
73d66c58 | 132 | mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR\r |
e60af8a1 | 133 | mov dword[PT_ADDR (0x101C)], edx\r |
c90e37b5 JJ |
134 | \r |
135 | ;\r | |
136 | ; Page Table Entries (2048 * 2MB entries => 4GB)\r | |
137 | ;\r | |
138 | mov ecx, 0x800\r | |
139 | pageTableEntriesLoop:\r | |
140 | mov eax, ecx\r | |
141 | dec eax\r | |
142 | shl eax, 21\r | |
143 | add eax, PAGE_2M_PDE_ATTR\r | |
73d66c58 | 144 | mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax\r |
e60af8a1 | 145 | mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx\r |
c90e37b5 JJ |
146 | loop pageTableEntriesLoop\r |
147 | \r | |
148 | ;\r | |
149 | ; Set CR3 now that the paging structures are available\r | |
150 | ;\r | |
73d66c58 | 151 | mov eax, PT_ADDR (0)\r |
c90e37b5 JJ |
152 | mov cr3, eax\r |
153 | \r | |
154 | OneTimeCallRet SetCr3ForPageTables64\r |