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49ba9447 | 1 | ;------------------------------------------------------------------------------\r |
2 | ;\r | |
3 | ; Copyright (c) 2008, Intel Corporation\r | |
4 | ; All rights reserved. This program and the accompanying materials\r | |
5 | ; are licensed and made available under the terms and conditions of the BSD License\r | |
6 | ; which accompanies this distribution. The full text of the license may be found at\r | |
7 | ; http://opensource.org/licenses/bsd-license.php\r | |
8 | ;\r | |
9 | ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | ;\r | |
12 | ; Module Name:\r | |
13 | ;\r | |
14 | ; SerialDebug.asm\r | |
15 | ;\r | |
16 | ; Abstract:\r | |
17 | ;\r | |
18 | ; Serial port support macros\r | |
19 | ;\r | |
20 | ;------------------------------------------------------------------------------\r | |
21 | \r | |
22 | BITS 16\r | |
23 | \r | |
24 | ;//---------------------------------------------\r | |
25 | ;// UART Register Offsets\r | |
26 | ;//---------------------------------------------\r | |
27 | %define BAUD_LOW_OFFSET 0x00\r | |
28 | %define BAUD_HIGH_OFFSET 0x01\r | |
29 | %define IER_OFFSET 0x01\r | |
30 | %define LCR_SHADOW_OFFSET 0x01\r | |
31 | %define FCR_SHADOW_OFFSET 0x02\r | |
32 | %define IR_CONTROL_OFFSET 0x02\r | |
33 | %define FCR_OFFSET 0x02\r | |
34 | %define EIR_OFFSET 0x02\r | |
35 | %define BSR_OFFSET 0x03\r | |
36 | %define LCR_OFFSET 0x03\r | |
37 | %define MCR_OFFSET 0x04\r | |
38 | %define LSR_OFFSET 0x05\r | |
39 | %define MSR_OFFSET 0x06\r | |
40 | \r | |
41 | ;//---------------------------------------------\r | |
42 | ;// UART Register Bit Defines\r | |
43 | ;//---------------------------------------------\r | |
44 | %define LSR_TXRDY 0x20\r | |
45 | %define LSR_RXDA 0x01\r | |
46 | %define DLAB 0x01\r | |
47 | \r | |
48 | ; UINT16 gComBase = 0x3f8;\r | |
49 | ; UINTN gBps = 115200;\r | |
50 | ; UINT8 gData = 8;\r | |
51 | ; UINT8 gStop = 1;\r | |
52 | ; UINT8 gParity = 0;\r | |
53 | ; UINT8 gBreakSet = 0;\r | |
54 | \r | |
55 | %define DEFAULT_COM_BASE 0x3f8\r | |
56 | %define DEFAULT_BPS 115200\r | |
57 | %define DEFAULT_DATA 8\r | |
58 | %define DEFAULT_STOP 1\r | |
59 | %define DEFAULT_PARITY 0\r | |
60 | %define DEFAULT_BREAK_SET 0\r | |
61 | \r | |
62 | %define SERIAL_DEFAULT_LCR ( \\r | |
63 | (DEFAULT_BREAK_SET << 6) | \\r | |
64 | (DEFAULT_PARITY << 3) | \\r | |
65 | (DEFAULT_STOP << 2) | \\r | |
66 | (DEFAULT_DATA - 5) \\r | |
67 | )\r | |
68 | \r | |
69 | %define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE\r | |
70 | \r | |
71 | %macro inFromSerialPort 1\r | |
72 | mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r | |
73 | in al, dx\r | |
74 | %endmacro\r | |
75 | \r | |
76 | %macro waitForSerialTxReady 0\r | |
77 | \r | |
78 | %%waitingForTx:\r | |
79 | inFromSerialPort LSR_OFFSET\r | |
80 | test al, LSR_TXRDY\r | |
81 | jz %%waitingForTx\r | |
82 | \r | |
83 | %endmacro\r | |
84 | \r | |
85 | %macro outToSerialPort 2\r | |
86 | mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r | |
87 | mov al, %2\r | |
88 | out dx, al\r | |
89 | %endmacro\r | |
90 | \r | |
91 | %macro writeToSerialPort 1\r | |
92 | waitForSerialTxReady\r | |
93 | outToSerialPort 0, %1\r | |
94 | %endmacro\r | |
95 | \r | |
96 | real16InitSerialPort:\r | |
97 | ;\r | |
98 | ; Set communications format\r | |
99 | ;\r | |
100 | outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR)\r | |
101 | \r | |
102 | ;\r | |
103 | ; Configure baud rate\r | |
104 | ;\r | |
105 | outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8)\r | |
106 | outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff)\r | |
107 | \r | |
108 | ;\r | |
109 | ; Switch back to bank 0\r | |
110 | ;\r | |
111 | outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR\r | |
112 | \r | |
113 | jmp real16SerialPortInitReturn\r | |
114 | \r |