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9d560947 LE |
1 | /** @file\r |
2 | \r | |
3 | A PEIM with the following responsibilities:\r | |
4 | \r | |
5 | - verify & configure the Q35 TSEG in the entry point,\r | |
6 | - provide SMRAM access by producing PEI_SMM_ACCESS_PPI,\r | |
7 | - set aside the SMM_S3_RESUME_STATE object at the bottom of TSEG, and expose\r | |
8 | it via the gEfiAcpiVariableGuid GUID HOB.\r | |
9 | \r | |
10 | This PEIM runs from RAM, so we can write to variables with static storage\r | |
11 | duration.\r | |
12 | \r | |
13 | Copyright (C) 2013, 2015, Red Hat, Inc.<BR>\r | |
14 | Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r | |
15 | \r | |
16 | This program and the accompanying materials are licensed and made available\r | |
17 | under the terms and conditions of the BSD License which accompanies this\r | |
18 | distribution. The full text of the license may be found at\r | |
19 | http://opensource.org/licenses/bsd-license.php\r | |
20 | \r | |
21 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r | |
22 | WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
23 | \r | |
24 | **/\r | |
25 | \r | |
26 | #include <Guid/AcpiS3Context.h>\r | |
27 | #include <Library/BaseLib.h>\r | |
28 | #include <Library/BaseMemoryLib.h>\r | |
29 | #include <Library/DebugLib.h>\r | |
30 | #include <Library/HobLib.h>\r | |
31 | #include <Library/IoLib.h>\r | |
32 | #include <Library/PcdLib.h>\r | |
33 | #include <Library/PciLib.h>\r | |
34 | #include <Library/PeiServicesLib.h>\r | |
35 | #include <Ppi/SmmAccess.h>\r | |
36 | \r | |
37 | #include <OvmfPlatforms.h>\r | |
38 | \r | |
39 | #include "SmramInternal.h"\r | |
40 | \r | |
41 | //\r | |
42 | // PEI_SMM_ACCESS_PPI implementation.\r | |
43 | //\r | |
44 | \r | |
45 | /**\r | |
46 | Opens the SMRAM area to be accessible by a PEIM driver.\r | |
47 | \r | |
48 | This function "opens" SMRAM so that it is visible while not inside of SMM.\r | |
49 | The function should return EFI_UNSUPPORTED if the hardware does not support\r | |
50 | hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM\r | |
51 | configuration is locked.\r | |
52 | \r | |
53 | @param PeiServices General purpose services available to every\r | |
54 | PEIM.\r | |
55 | @param This The pointer to the SMM Access Interface.\r | |
56 | @param DescriptorIndex The region of SMRAM to Open.\r | |
57 | \r | |
58 | @retval EFI_SUCCESS The region was successfully opened.\r | |
59 | @retval EFI_DEVICE_ERROR The region could not be opened because locked\r | |
60 | by chipset.\r | |
61 | @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r | |
62 | \r | |
63 | **/\r | |
64 | STATIC\r | |
65 | EFI_STATUS\r | |
66 | EFIAPI\r | |
67 | SmmAccessPeiOpen (\r | |
68 | IN EFI_PEI_SERVICES **PeiServices,\r | |
69 | IN PEI_SMM_ACCESS_PPI *This,\r | |
70 | IN UINTN DescriptorIndex\r | |
71 | )\r | |
72 | {\r | |
73 | if (DescriptorIndex >= DescIdxCount) {\r | |
74 | return EFI_INVALID_PARAMETER;\r | |
75 | }\r | |
76 | \r | |
77 | //\r | |
78 | // According to current practice, DescriptorIndex is not considered at all,\r | |
79 | // beyond validating it.\r | |
80 | //\r | |
81 | return SmramAccessOpen (&This->LockState, &This->OpenState);\r | |
82 | }\r | |
83 | \r | |
84 | /**\r | |
85 | Inhibits access to the SMRAM.\r | |
86 | \r | |
87 | This function "closes" SMRAM so that it is not visible while outside of SMM.\r | |
88 | The function should return EFI_UNSUPPORTED if the hardware does not support\r | |
89 | hiding of SMRAM.\r | |
90 | \r | |
91 | @param PeiServices General purpose services available to every\r | |
92 | PEIM.\r | |
93 | @param This The pointer to the SMM Access Interface.\r | |
94 | @param DescriptorIndex The region of SMRAM to Close.\r | |
95 | \r | |
96 | @retval EFI_SUCCESS The region was successfully closed.\r | |
97 | @retval EFI_DEVICE_ERROR The region could not be closed because\r | |
98 | locked by chipset.\r | |
99 | @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r | |
100 | \r | |
101 | **/\r | |
102 | STATIC\r | |
103 | EFI_STATUS\r | |
104 | EFIAPI\r | |
105 | SmmAccessPeiClose (\r | |
106 | IN EFI_PEI_SERVICES **PeiServices,\r | |
107 | IN PEI_SMM_ACCESS_PPI *This,\r | |
108 | IN UINTN DescriptorIndex\r | |
109 | )\r | |
110 | {\r | |
111 | if (DescriptorIndex >= DescIdxCount) {\r | |
112 | return EFI_INVALID_PARAMETER;\r | |
113 | }\r | |
114 | \r | |
115 | //\r | |
116 | // According to current practice, DescriptorIndex is not considered at all,\r | |
117 | // beyond validating it.\r | |
118 | //\r | |
119 | return SmramAccessClose (&This->LockState, &This->OpenState);\r | |
120 | }\r | |
121 | \r | |
122 | /**\r | |
123 | Inhibits access to the SMRAM.\r | |
124 | \r | |
125 | This function prohibits access to the SMRAM region. This function is usually\r | |
126 | implemented such that it is a write-once operation.\r | |
127 | \r | |
128 | @param PeiServices General purpose services available to every\r | |
129 | PEIM.\r | |
130 | @param This The pointer to the SMM Access Interface.\r | |
131 | @param DescriptorIndex The region of SMRAM to Close.\r | |
132 | \r | |
133 | @retval EFI_SUCCESS The region was successfully locked.\r | |
134 | @retval EFI_DEVICE_ERROR The region could not be locked because at\r | |
135 | least one range is still open.\r | |
136 | @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r | |
137 | \r | |
138 | **/\r | |
139 | STATIC\r | |
140 | EFI_STATUS\r | |
141 | EFIAPI\r | |
142 | SmmAccessPeiLock (\r | |
143 | IN EFI_PEI_SERVICES **PeiServices,\r | |
144 | IN PEI_SMM_ACCESS_PPI *This,\r | |
145 | IN UINTN DescriptorIndex\r | |
146 | )\r | |
147 | {\r | |
148 | if (DescriptorIndex >= DescIdxCount) {\r | |
149 | return EFI_INVALID_PARAMETER;\r | |
150 | }\r | |
151 | \r | |
152 | //\r | |
153 | // According to current practice, DescriptorIndex is not considered at all,\r | |
154 | // beyond validating it.\r | |
155 | //\r | |
156 | return SmramAccessLock (&This->LockState, &This->OpenState);\r | |
157 | }\r | |
158 | \r | |
159 | /**\r | |
160 | Queries the memory controller for the possible regions that will support\r | |
161 | SMRAM.\r | |
162 | \r | |
163 | @param PeiServices General purpose services available to every\r | |
164 | PEIM.\r | |
165 | @param This The pointer to the SmmAccessPpi Interface.\r | |
166 | @param SmramMapSize The pointer to the variable containing size of\r | |
167 | the buffer to contain the description\r | |
168 | information.\r | |
169 | @param SmramMap The buffer containing the data describing the\r | |
170 | Smram region descriptors.\r | |
171 | \r | |
172 | @retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buffer.\r | |
173 | @retval EFI_SUCCESS The user provided a sufficiently-sized buffer.\r | |
174 | \r | |
175 | **/\r | |
176 | STATIC\r | |
177 | EFI_STATUS\r | |
178 | EFIAPI\r | |
179 | SmmAccessPeiGetCapabilities (\r | |
180 | IN EFI_PEI_SERVICES **PeiServices,\r | |
181 | IN PEI_SMM_ACCESS_PPI *This,\r | |
182 | IN OUT UINTN *SmramMapSize,\r | |
183 | IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap\r | |
184 | )\r | |
185 | {\r | |
186 | return SmramAccessGetCapabilities (This->LockState, This->OpenState,\r | |
187 | SmramMapSize, SmramMap);\r | |
188 | }\r | |
189 | \r | |
190 | //\r | |
191 | // LockState and OpenState will be filled in by the entry point.\r | |
192 | //\r | |
193 | STATIC PEI_SMM_ACCESS_PPI mAccess = {\r | |
194 | &SmmAccessPeiOpen,\r | |
195 | &SmmAccessPeiClose,\r | |
196 | &SmmAccessPeiLock,\r | |
197 | &SmmAccessPeiGetCapabilities\r | |
198 | };\r | |
199 | \r | |
200 | \r | |
201 | STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {\r | |
202 | {\r | |
203 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
204 | &gPeiSmmAccessPpiGuid, &mAccess\r | |
205 | }\r | |
206 | };\r | |
207 | \r | |
208 | \r | |
209 | //\r | |
210 | // Utility functions.\r | |
211 | //\r | |
212 | STATIC\r | |
213 | UINT8\r | |
214 | CmosRead8 (\r | |
215 | IN UINT8 Index\r | |
216 | )\r | |
217 | {\r | |
218 | IoWrite8 (0x70, Index);\r | |
219 | return IoRead8 (0x71);\r | |
220 | }\r | |
221 | \r | |
222 | STATIC\r | |
223 | UINT32\r | |
224 | GetSystemMemorySizeBelow4gb (\r | |
225 | VOID\r | |
226 | )\r | |
227 | {\r | |
228 | UINT32 Cmos0x34;\r | |
229 | UINT32 Cmos0x35;\r | |
230 | \r | |
231 | Cmos0x34 = CmosRead8 (0x34);\r | |
232 | Cmos0x35 = CmosRead8 (0x35);\r | |
233 | \r | |
234 | return ((Cmos0x35 << 8 | Cmos0x34) << 16) + SIZE_16MB;\r | |
235 | }\r | |
236 | \r | |
237 | \r | |
238 | //\r | |
239 | // Entry point of this driver.\r | |
240 | //\r | |
241 | EFI_STATUS\r | |
242 | EFIAPI\r | |
243 | SmmAccessPeiEntryPoint (\r | |
244 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
245 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
246 | )\r | |
247 | {\r | |
248 | UINT16 HostBridgeDevId;\r | |
249 | UINT8 EsmramcVal;\r | |
250 | UINT8 RegMask8;\r | |
251 | UINT32 TopOfLowRam, TopOfLowRamMb;\r | |
252 | EFI_STATUS Status;\r | |
253 | UINTN SmramMapSize;\r | |
254 | EFI_SMRAM_DESCRIPTOR SmramMap[DescIdxCount];\r | |
255 | VOID *GuidHob;\r | |
256 | \r | |
257 | //\r | |
258 | // This module should only be included if SMRAM support is required.\r | |
259 | //\r | |
260 | ASSERT (FeaturePcdGet (PcdSmmSmramRequire));\r | |
261 | \r | |
262 | //\r | |
263 | // Verify if we're running on a Q35 machine type.\r | |
264 | //\r | |
265 | HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
266 | if (HostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r | |
267 | DEBUG ((EFI_D_ERROR, "%a: no SMRAM with host bridge DID=0x%04x; only "\r | |
268 | "DID=0x%04x (Q35) is supported\n", __FUNCTION__, HostBridgeDevId,\r | |
269 | INTEL_Q35_MCH_DEVICE_ID));\r | |
270 | goto WrongConfig;\r | |
271 | }\r | |
272 | \r | |
273 | //\r | |
274 | // Confirm if QEMU supports SMRAM.\r | |
275 | //\r | |
276 | // With no support for it, the ESMRAMC (Extended System Management RAM\r | |
277 | // Control) register reads as zero. If there is support, the cache-enable\r | |
278 | // bits are hard-coded as 1 by QEMU.\r | |
279 | //\r | |
280 | EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));\r | |
281 | RegMask8 = MCH_ESMRAMC_SM_CACHE | MCH_ESMRAMC_SM_L1 | MCH_ESMRAMC_SM_L2;\r | |
282 | if ((EsmramcVal & RegMask8) != RegMask8) {\r | |
283 | DEBUG ((EFI_D_ERROR, "%a: this Q35 implementation lacks SMRAM\n",\r | |
284 | __FUNCTION__));\r | |
285 | goto WrongConfig;\r | |
286 | }\r | |
287 | \r | |
288 | TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r | |
289 | ASSERT ((TopOfLowRam & (SIZE_1MB - 1)) == 0);\r | |
290 | TopOfLowRamMb = TopOfLowRam >> 20;\r | |
291 | \r | |
292 | //\r | |
293 | // Some of the following registers are no-ops for QEMU at the moment, but it\r | |
294 | // is recommended to set them correctly, since the ESMRAMC that we ultimately\r | |
295 | // care about is in the same set of registers.\r | |
296 | //\r | |
297 | // First, we disable the integrated VGA, and set both the GTT Graphics Memory\r | |
298 | // Size and the Graphics Mode Select memory pre-allocation fields to zero.\r | |
299 | // This takes just one write to the Graphics Control Register.\r | |
300 | //\r | |
301 | PciWrite16 (DRAMC_REGISTER_Q35 (MCH_GGC), MCH_GGC_IVD);\r | |
302 | \r | |
303 | //\r | |
304 | // Set Top of Low Usable DRAM.\r | |
305 | //\r | |
306 | PciWrite16 (DRAMC_REGISTER_Q35 (MCH_TOLUD),\r | |
307 | (UINT16)(TopOfLowRamMb << MCH_TOLUD_MB_SHIFT));\r | |
308 | \r | |
309 | //\r | |
310 | // Given the zero graphics memory sizes configured above, set the\r | |
311 | // graphics-related stolen memory bases to the same as TOLUD.\r | |
312 | //\r | |
313 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_GBSM),\r | |
314 | TopOfLowRamMb << MCH_GBSM_MB_SHIFT);\r | |
315 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM),\r | |
316 | TopOfLowRamMb << MCH_BGSM_MB_SHIFT);\r | |
317 | \r | |
318 | //\r | |
319 | // Set TSEG Memory Base.\r | |
320 | //\r | |
321 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB),\r | |
322 | (TopOfLowRamMb - FixedPcdGet8 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHIFT);\r | |
323 | \r | |
324 | //\r | |
325 | // Set TSEG size, and disable TSEG visibility outside of SMM. Note that the\r | |
326 | // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is\r | |
327 | // *restricted* to SMM.\r | |
328 | //\r | |
329 | EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK;\r | |
330 | EsmramcVal |= FixedPcdGet8 (PcdQ35TsegMbytes) == 8 ? MCH_ESMRAMC_TSEG_8MB :\r | |
331 | FixedPcdGet8 (PcdQ35TsegMbytes) == 2 ? MCH_ESMRAMC_TSEG_2MB :\r | |
332 | MCH_ESMRAMC_TSEG_1MB;\r | |
333 | EsmramcVal |= MCH_ESMRAMC_T_EN;\r | |
334 | PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal);\r | |
335 | \r | |
336 | //\r | |
337 | // TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME\r | |
338 | // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it.\r | |
339 | //\r | |
340 | PciAndThenOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM),\r | |
341 | (UINT8)((~(UINT32)MCH_SMRAM_D_LCK) & 0xff), MCH_SMRAM_G_SMRAME);\r | |
342 | \r | |
343 | //\r | |
344 | // Create the GUID HOB and point it to the first SMRAM range.\r | |
345 | //\r | |
346 | GetStates (&mAccess.LockState, &mAccess.OpenState);\r | |
347 | SmramMapSize = sizeof SmramMap;\r | |
348 | Status = SmramAccessGetCapabilities (mAccess.LockState, mAccess.OpenState,\r | |
349 | &SmramMapSize, SmramMap);\r | |
350 | ASSERT_EFI_ERROR (Status);\r | |
351 | \r | |
352 | DEBUG_CODE_BEGIN ();\r | |
353 | {\r | |
354 | UINTN Count;\r | |
355 | UINTN Idx;\r | |
356 | \r | |
357 | Count = SmramMapSize / sizeof SmramMap[0];\r | |
358 | DEBUG ((EFI_D_VERBOSE, "%a: SMRAM map follows, %d entries\n", __FUNCTION__,\r | |
359 | (INT32)Count));\r | |
360 | DEBUG ((EFI_D_VERBOSE, "% 20a % 20a % 20a % 20a\n", "PhysicalStart(0x)",\r | |
361 | "PhysicalSize(0x)", "CpuStart(0x)", "RegionState(0x)"));\r | |
362 | for (Idx = 0; Idx < Count; ++Idx) {\r | |
363 | DEBUG ((EFI_D_VERBOSE, "% 20Lx % 20Lx % 20Lx % 20Lx\n",\r | |
364 | SmramMap[Idx].PhysicalStart, SmramMap[Idx].PhysicalSize,\r | |
365 | SmramMap[Idx].CpuStart, SmramMap[Idx].RegionState));\r | |
366 | }\r | |
367 | }\r | |
368 | DEBUG_CODE_END ();\r | |
369 | \r | |
370 | GuidHob = BuildGuidHob (&gEfiAcpiVariableGuid,\r | |
371 | sizeof SmramMap[DescIdxSmmS3ResumeState]);\r | |
372 | if (GuidHob == NULL) {\r | |
373 | return EFI_OUT_OF_RESOURCES;\r | |
374 | }\r | |
375 | \r | |
376 | CopyMem (GuidHob, &SmramMap[DescIdxSmmS3ResumeState],\r | |
377 | sizeof SmramMap[DescIdxSmmS3ResumeState]);\r | |
378 | \r | |
379 | //\r | |
380 | // We're done. The next step should succeed, but even if it fails, we can't\r | |
381 | // roll back the above BuildGuidHob() allocation, because PEI doesn't support\r | |
382 | // releasing memory.\r | |
383 | //\r | |
384 | return PeiServicesInstallPpi (mPpiList);\r | |
385 | \r | |
386 | WrongConfig:\r | |
387 | //\r | |
388 | // We really don't want to continue in this case.\r | |
389 | //\r | |
390 | ASSERT (FALSE);\r | |
391 | CpuDeadLoop ();\r | |
392 | return EFI_UNSUPPORTED;\r | |
393 | }\r |