OvmfPkg/PvScsiDxe: Enable device 64-bit DMA addresses

[mirror_edk2.git] / OvmfPkg / SmmAccess / SmramInternal.c

/** @file\r
\r
  Functions and types shared by the SMM accessor PEI and DXE modules.\r
\r
  Copyright (C) 2015, Red Hat, Inc.\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Guid/AcpiS3Context.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
\r
#include "SmramInternal.h"\r
\r
//\r
// The value of PcdQ35TsegMbytes is saved into this variable at module startup.\r
//\r
UINT16 mQ35TsegMbytes;\r
\r
//\r
// The value of PcdQ35SmramAtDefaultSmbase is saved into this variable at\r
// module startup.\r
//\r
STATIC BOOLEAN mQ35SmramAtDefaultSmbase;\r
\r
/**\r
  Save PcdQ35TsegMbytes into mQ35TsegMbytes.\r
**/\r
VOID\r
InitQ35TsegMbytes (\r
  VOID\r
  )\r
{\r
  mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
}\r
\r
/**\r
  Save PcdQ35SmramAtDefaultSmbase into mQ35SmramAtDefaultSmbase.\r
**/\r
VOID\r
InitQ35SmramAtDefaultSmbase (\r
  VOID\r
  )\r
{\r
  mQ35SmramAtDefaultSmbase = PcdGetBool (PcdQ35SmramAtDefaultSmbase);\r
}\r
\r
/**\r
  Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and\r
  OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL object,\r
  from the D_LCK and T_EN bits.\r
\r
  PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rely on\r
  the LockState and OpenState fields being up-to-date on entry, and they need\r
  to restore the same invariant on exit, if they touch the bits in question.\r
\r
  @param[out] LockState  Reflects the D_LCK bit on output; TRUE iff SMRAM is\r
                         locked.\r
  @param[out] OpenState  Reflects the inverse of the T_EN bit on output; TRUE\r
                         iff SMRAM is open.\r
**/\r
VOID\r
GetStates (\r
  OUT BOOLEAN *LockState,\r
  OUT BOOLEAN *OpenState\r
)\r
{\r
  UINT8 SmramVal, EsmramcVal;\r
\r
  SmramVal   = PciRead8 (DRAMC_REGISTER_Q35 (MCH_SMRAM));\r
  EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));\r
\r
  *LockState = !!(SmramVal & MCH_SMRAM_D_LCK);\r
  *OpenState = !(EsmramcVal & MCH_ESMRAMC_T_EN);\r
}\r
\r
//\r
// The functions below follow the PEI_SMM_ACCESS_PPI and\r
// EFI_SMM_ACCESS2_PROTOCOL member declarations. The PeiServices and This\r
// pointers are removed (TSEG doesn't depend on them), and so is the\r
// DescriptorIndex parameter (TSEG doesn't support range-wise locking).\r
//\r
// The LockState and OpenState members that are common to both\r
// PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL are taken and updated in\r
// isolation from the rest of the (non-shared) members.\r
//\r
\r
EFI_STATUS\r
SmramAccessOpen (\r
  OUT BOOLEAN *LockState,\r
  OUT BOOLEAN *OpenState\r
  )\r
{\r
  //\r
  // Open TSEG by clearing T_EN.\r
  //\r
  PciAnd8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC),\r
    (UINT8)((~(UINT32)MCH_ESMRAMC_T_EN) & 0xff));\r
\r
  GetStates (LockState, OpenState);\r
  if (!*OpenState) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
SmramAccessClose (\r
  OUT BOOLEAN *LockState,\r
  OUT BOOLEAN *OpenState\r
  )\r
{\r
  //\r
  // Close TSEG by setting T_EN.\r
  //\r
  PciOr8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), MCH_ESMRAMC_T_EN);\r
\r
  GetStates (LockState, OpenState);\r
  if (*OpenState) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
SmramAccessLock (\r
  OUT    BOOLEAN *LockState,\r
  IN OUT BOOLEAN *OpenState\r
  )\r
{\r
  if (*OpenState) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  //\r
  // Close & lock TSEG by setting T_EN and D_LCK.\r
  //\r
  PciOr8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), MCH_ESMRAMC_T_EN);\r
  PciOr8 (DRAMC_REGISTER_Q35 (MCH_SMRAM),   MCH_SMRAM_D_LCK);\r
\r
  //\r
  // Close & lock the SMRAM at the default SMBASE, if it exists.\r
  //\r
  if (mQ35SmramAtDefaultSmbase) {\r
    PciWrite8 (DRAMC_REGISTER_Q35 (MCH_DEFAULT_SMBASE_CTL),\r
      MCH_DEFAULT_SMBASE_LCK);\r
  }\r
\r
  GetStates (LockState, OpenState);\r
  if (*OpenState || !*LockState) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
SmramAccessGetCapabilities (\r
  IN BOOLEAN                  LockState,\r
  IN BOOLEAN                  OpenState,\r
  IN OUT UINTN                *SmramMapSize,\r
  IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap\r
  )\r
{\r
  UINTN  OriginalSize;\r
  UINT32 TsegMemoryBaseMb, TsegMemoryBase;\r
  UINT64 CommonRegionState;\r
  UINT8  TsegSizeBits;\r
\r
  OriginalSize  = *SmramMapSize;\r
  *SmramMapSize = DescIdxCount * sizeof *SmramMap;\r
  if (OriginalSize < *SmramMapSize) {\r
    return EFI_BUFFER_TOO_SMALL;\r
  }\r
\r
  //\r
  // Read the TSEG Memory Base register.\r
  //\r
  TsegMemoryBaseMb = PciRead32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB));\r
  TsegMemoryBase = (TsegMemoryBaseMb >> MCH_TSEGMB_MB_SHIFT) << 20;\r
\r
  //\r
  // Precompute the region state bits that will be set for all regions.\r
  //\r
  CommonRegionState = (OpenState ? EFI_SMRAM_OPEN : EFI_SMRAM_CLOSED) |\r
                      (LockState ? EFI_SMRAM_LOCKED : 0) |\r
                      EFI_CACHEABLE;\r
\r
  //\r
  // The first region hosts an SMM_S3_RESUME_STATE object. It is located at the\r
  // start of TSEG. We round up the size to whole pages, and we report it as\r
  // EFI_ALLOCATED, so that the SMM_CORE stays away from it.\r
  //\r
  SmramMap[DescIdxSmmS3ResumeState].PhysicalStart = TsegMemoryBase;\r
  SmramMap[DescIdxSmmS3ResumeState].CpuStart      = TsegMemoryBase;\r
  SmramMap[DescIdxSmmS3ResumeState].PhysicalSize  =\r
    EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (sizeof (SMM_S3_RESUME_STATE)));\r
  SmramMap[DescIdxSmmS3ResumeState].RegionState   =\r
    CommonRegionState | EFI_ALLOCATED;\r
\r
  //\r
  // Get the TSEG size bits from the ESMRAMC register.\r
  //\r
  TsegSizeBits = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC)) &\r
                 MCH_ESMRAMC_TSEG_MASK;\r
\r
  //\r
  // The second region is the main one, following the first.\r
  //\r
  SmramMap[DescIdxMain].PhysicalStart =\r
    SmramMap[DescIdxSmmS3ResumeState].PhysicalStart +\r
    SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;\r
  SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;\r
  SmramMap[DescIdxMain].PhysicalSize =\r
    (TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :\r
     TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :\r
     TsegSizeBits == MCH_ESMRAMC_TSEG_1MB ? SIZE_1MB :\r
     mQ35TsegMbytes * SIZE_1MB) -\r
    SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;\r
  SmramMap[DescIdxMain].RegionState = CommonRegionState;\r
\r
  return EFI_SUCCESS;\r
}\r