[mirror_edk2.git] / OvmfPkg / SmmControl2Dxe / SmmControl2Dxe.c

/** @file\r
\r
  A DXE_RUNTIME_DRIVER providing synchronous SMI activations via the\r
  EFI_SMM_CONTROL2_PROTOCOL.\r
\r
  We expect the PEI phase to have covered the following:\r
  - ensure that the underlying QEMU machine type be Q35\r
    (responsible: OvmfPkg/SmmAccess/SmmAccessPei.inf)\r
  - ensure that the ACPI PM IO space be configured\r
    (responsible: OvmfPkg/PlatformPei/PlatformPei.inf)\r
\r
  Our own entry point is responsible for confirming the SMI feature and for\r
  configuring it.\r
\r
  Copyright (C) 2013, 2015, Red Hat, Inc.<BR>\r
  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Protocol/S3SaveState.h>\r
#include <Protocol/SmmControl2.h>\r
\r
#include "SmiFeatures.h"\r
\r
//\r
// Forward declaration.\r
//\r
STATIC\r
VOID\r
EFIAPI\r
OnS3SaveStateInstalled (\r
  IN EFI_EVENT Event,\r
  IN VOID      *Context\r
  );\r
\r
//\r
// The absolute IO port address of the SMI Control and Enable Register. It is\r
// only used to carry information from the entry point function to the\r
// S3SaveState protocol installation callback, strictly before the runtime\r
// phase.\r
//\r
STATIC UINTN mSmiEnable;\r
\r
//\r
// Captures whether SMI feature negotiation is supported. The variable is only\r
// used to carry this information from the entry point function to the\r
// S3SaveState protocol installation callback.\r
//\r
STATIC BOOLEAN mSmiFeatureNegotiation;\r
\r
//\r
// Event signaled when an S3SaveState protocol interface is installed.\r
//\r
STATIC EFI_EVENT mS3SaveStateInstalled;\r
\r
/**\r
  Invokes SMI activation from either the preboot or runtime environment.\r
\r
  This function generates an SMI.\r
\r
  @param[in]     This                The EFI_SMM_CONTROL2_PROTOCOL instance.\r
  @param[in,out] CommandPort         The value written to the command port.\r
  @param[in,out] DataPort            The value written to the data port.\r
  @param[in]     Periodic            Optional mechanism to engender a periodic\r
                                     stream.\r
  @param[in]     ActivationInterval  Optional parameter to repeat at this\r
                                     period one time or, if the Periodic\r
                                     Boolean is set, periodically.\r
\r
  @retval EFI_SUCCESS            The SMI/PMI has been engendered.\r
  @retval EFI_DEVICE_ERROR       The timing is unsupported.\r
  @retval EFI_INVALID_PARAMETER  The activation period is unsupported.\r
  @retval EFI_INVALID_PARAMETER  The last periodic activation has not been\r
                                 cleared.\r
  @retval EFI_NOT_STARTED        The SMM base service has not been initialized.\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmControl2DxeTrigger (\r
  IN CONST EFI_SMM_CONTROL2_PROTOCOL  *This,\r
  IN OUT UINT8                        *CommandPort       OPTIONAL,\r
  IN OUT UINT8                        *DataPort          OPTIONAL,\r
  IN BOOLEAN                          Periodic           OPTIONAL,\r
  IN UINTN                            ActivationInterval OPTIONAL\r
  )\r
{\r
  //\r
  // No support for queued or periodic activation.\r
  //\r
  if (Periodic || ActivationInterval > 0) {\r
    return EFI_DEVICE_ERROR;\r
  }\r
\r
  //\r
  // The so-called "Advanced Power Management Status Port Register" is in fact\r
  // a generic data passing register, between the caller and the SMI\r
  // dispatcher. The ICH9 spec calls it "scratchpad register" --  calling it\r
  // "status" elsewhere seems quite the misnomer. Status registers usually\r
  // report about hardware status, while this register is fully governed by\r
  // software.\r
  //\r
  // Write to the status register first, as this won't trigger the SMI just\r
  // yet. Then write to the control register.\r
  //\r
  IoWrite8 (ICH9_APM_STS, DataPort    == NULL ? 0 : *DataPort);\r
  IoWrite8 (ICH9_APM_CNT, CommandPort == NULL ? 0 : *CommandPort);\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Clears any system state that was created in response to the Trigger() call.\r
\r
  This function acknowledges and causes the deassertion of the SMI activation\r
  source.\r
\r
  @param[in] This                The EFI_SMM_CONTROL2_PROTOCOL instance.\r
  @param[in] Periodic            Optional parameter to repeat at this period\r
                                 one time\r
\r
  @retval EFI_SUCCESS            The SMI/PMI has been engendered.\r
  @retval EFI_DEVICE_ERROR       The source could not be cleared.\r
  @retval EFI_INVALID_PARAMETER  The service did not support the Periodic input\r
                                 argument.\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
SmmControl2DxeClear (\r
  IN CONST EFI_SMM_CONTROL2_PROTOCOL  *This,\r
  IN BOOLEAN                          Periodic OPTIONAL\r
  )\r
{\r
  if (Periodic) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // The PI spec v1.4 explains that Clear() is only supposed to clear software\r
  // status; it is not in fact responsible for deasserting the SMI. It gives\r
  // two reasons for this: (a) many boards clear the SMI automatically when\r
  // entering SMM, (b) if Clear() actually deasserted the SMI, then it could\r
  // incorrectly suppress an SMI that was asynchronously asserted between the\r
  // last return of the SMI handler and the call made to Clear().\r
  //\r
  // In fact QEMU automatically deasserts CPU_INTERRUPT_SMI in:\r
  // - x86_cpu_exec_interrupt() [target-i386/seg_helper.c], and\r
  // - kvm_arch_pre_run() [target-i386/kvm.c].\r
  //\r
  // So, nothing to do here.\r
  //\r
  return EFI_SUCCESS;\r
}\r
\r
STATIC EFI_SMM_CONTROL2_PROTOCOL mControl2 = {\r
  &SmmControl2DxeTrigger,\r
  &SmmControl2DxeClear,\r
  MAX_UINTN // MinimumTriggerPeriod -- we don't support periodic SMIs\r
};\r
\r
//\r
// Entry point of this driver.\r
//\r
EFI_STATUS\r
EFIAPI\r
SmmControl2DxeEntryPoint (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  )\r
{\r
  UINT32     PmBase;\r
  UINT32     SmiEnableVal;\r
  EFI_STATUS Status;\r
\r
  //\r
  // This module should only be included if SMRAM support is required.\r
  //\r
  ASSERT (FeaturePcdGet (PcdSmmSmramRequire));\r
\r
  //\r
  // Calculate the absolute IO port address of the SMI Control and Enable\r
  // Register. (As noted at the top, the PEI phase has left us with a working\r
  // ACPI PM IO space.)\r
  //\r
  PmBase = PciRead32 (POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE)) &\r
    ICH9_PMBASE_MASK;\r
  mSmiEnable = PmBase + ICH9_PMBASE_OFS_SMI_EN;\r
\r
  //\r
  // If APMC_EN is pre-set in SMI_EN, that's QEMU's way to tell us that SMI\r
  // support is not available. (For example due to KVM lacking it.) Otherwise,\r
  // this bit is clear after each reset.\r
  //\r
  SmiEnableVal = IoRead32 (mSmiEnable);\r
  if ((SmiEnableVal & ICH9_SMI_EN_APMC_EN) != 0) {\r
    DEBUG ((DEBUG_ERROR, "%a: this Q35 implementation lacks SMI\n",\r
      __FUNCTION__));\r
    goto FatalError;\r
  }\r
\r
  //\r
  // Otherwise, configure the board to inject an SMI when ICH9_APM_CNT is\r
  // written to. (See the Trigger() method above.)\r
  //\r
  SmiEnableVal |= ICH9_SMI_EN_APMC_EN | ICH9_SMI_EN_GBL_SMI_EN;\r
  IoWrite32 (mSmiEnable, SmiEnableVal);\r
\r
  //\r
  // Prevent software from undoing the above (until platform reset).\r
  //\r
  PciOr16 (POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),\r
    ICH9_GEN_PMCON_1_SMI_LOCK);\r
\r
  //\r
  // If we can clear GBL_SMI_EN now, that means QEMU's SMI support is not\r
  // appropriate.\r
  //\r
  IoWrite32 (mSmiEnable, SmiEnableVal & ~(UINT32)ICH9_SMI_EN_GBL_SMI_EN);\r
  if (IoRead32 (mSmiEnable) != SmiEnableVal) {\r
    DEBUG ((DEBUG_ERROR, "%a: failed to lock down GBL_SMI_EN\n",\r
      __FUNCTION__));\r
    goto FatalError;\r
  }\r
\r
  //\r
  // QEMU can inject SMIs in different ways, negotiate our preferences.\r
  //\r
  mSmiFeatureNegotiation = NegotiateSmiFeatures ();\r
\r
  if (PcdGetBool (PcdAcpiS3Enable)) {\r
    VOID *Registration;\r
\r
    //\r
    // On S3 resume the above register settings have to be repeated. Register a\r
    // protocol notify callback that, when boot script saving becomes\r
    // available, saves operations equivalent to the above to the boot script.\r
    //\r
    Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,\r
                    OnS3SaveStateInstalled, NULL /* Context */,\r
                    &mS3SaveStateInstalled);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((DEBUG_ERROR, "%a: CreateEvent: %r\n", __FUNCTION__, Status));\r
      goto FatalError;\r
    }\r
\r
    Status = gBS->RegisterProtocolNotify (&gEfiS3SaveStateProtocolGuid,\r
                    mS3SaveStateInstalled, &Registration);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((DEBUG_ERROR, "%a: RegisterProtocolNotify: %r\n", __FUNCTION__,\r
        Status));\r
      goto ReleaseEvent;\r
    }\r
\r
    //\r
    // Kick the event right now -- maybe the boot script is already saveable.\r
    //\r
    Status = gBS->SignalEvent (mS3SaveStateInstalled);\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((DEBUG_ERROR, "%a: SignalEvent: %r\n", __FUNCTION__, Status));\r
      goto ReleaseEvent;\r
    }\r
  }\r
\r
  //\r
  // We have no pointers to convert to virtual addresses. The handle itself\r
  // doesn't matter, as protocol services are not accessible at runtime.\r
  //\r
  Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,\r
                  &gEfiSmmControl2ProtocolGuid, &mControl2,\r
                  NULL);\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "%a: InstallMultipleProtocolInterfaces: %r\n",\r
      __FUNCTION__, Status));\r
    goto ReleaseEvent;\r
  }\r
\r
  return EFI_SUCCESS;\r
\r
ReleaseEvent:\r
  if (mS3SaveStateInstalled != NULL) {\r
    gBS->CloseEvent (mS3SaveStateInstalled);\r
  }\r
\r
FatalError:\r
  //\r
  // We really don't want to continue in this case.\r
  //\r
  ASSERT (FALSE);\r
  CpuDeadLoop ();\r
  return EFI_UNSUPPORTED;\r
}\r
\r
/**\r
  Notification callback for S3SaveState installation.\r
\r
  @param[in] Event    Event whose notification function is being invoked.\r
\r
  @param[in] Context  The pointer to the notification function's context, which\r
                      is implementation-dependent.\r
**/\r
STATIC\r
VOID\r
EFIAPI\r
OnS3SaveStateInstalled (\r
  IN EFI_EVENT Event,\r
  IN VOID      *Context\r
  )\r
{\r
  EFI_STATUS                 Status;\r
  EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState;\r
  UINT32                     SmiEnOrMask, SmiEnAndMask;\r
  UINT64                     GenPmCon1Address;\r
  UINT16                     GenPmCon1OrMask, GenPmCon1AndMask;\r
\r
  ASSERT (Event == mS3SaveStateInstalled);\r
\r
  Status = gBS->LocateProtocol (&gEfiS3SaveStateProtocolGuid,\r
                  NULL /* Registration */, (VOID **)&S3SaveState);\r
  if (EFI_ERROR (Status)) {\r
    return;\r
  }\r
\r
  //\r
  // These operations were originally done, verified and explained in the entry\r
  // point function of the driver.\r
  //\r
  SmiEnOrMask  = ICH9_SMI_EN_APMC_EN | ICH9_SMI_EN_GBL_SMI_EN;\r
  SmiEnAndMask = MAX_UINT32;\r
  Status = S3SaveState->Write (\r
                          S3SaveState,\r
                          EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE,\r
                          EfiBootScriptWidthUint32,\r
                          (UINT64)mSmiEnable,\r
                          &SmiEnOrMask,\r
                          &SmiEnAndMask\r
                          );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "%a: EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE: %r\n",\r
      __FUNCTION__, Status));\r
    ASSERT (FALSE);\r
    CpuDeadLoop ();\r
  }\r
\r
  GenPmCon1Address = POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS (\r
                       ICH9_GEN_PMCON_1);\r
  GenPmCon1OrMask  = ICH9_GEN_PMCON_1_SMI_LOCK;\r
  GenPmCon1AndMask = MAX_UINT16;\r
  Status = S3SaveState->Write (\r
                          S3SaveState,\r
                          EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE,\r
                          EfiBootScriptWidthUint16,\r
                          GenPmCon1Address,\r
                          &GenPmCon1OrMask,\r
                          &GenPmCon1AndMask\r
                          );\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR,\r
      "%a: EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE: %r\n", __FUNCTION__,\r
      Status));\r
    ASSERT (FALSE);\r
    CpuDeadLoop ();\r
  }\r
\r
  DEBUG ((DEBUG_VERBOSE, "%a: chipset boot script saved\n", __FUNCTION__));\r
\r
  //\r
  // Append a boot script fragment that re-selects the negotiated SMI features.\r
  //\r
  if (mSmiFeatureNegotiation) {\r
    SaveSmiFeatures ();\r
  }\r
\r
  gBS->CloseEvent (Event);\r
  mS3SaveStateInstalled = NULL;\r
}\r
Commit	Line	Data
c40e1a0c LE	1	/** @file\r
	2	\r
	3	A DXE_RUNTIME_DRIVER providing synchronous SMI activations via the\r
	4	EFI_SMM_CONTROL2_PROTOCOL.\r
	5	\r
	6	We expect the PEI phase to have covered the following:\r
	7	- ensure that the underlying QEMU machine type be Q35\r
	8	(responsible: OvmfPkg/SmmAccess/SmmAccessPei.inf)\r
	9	- ensure that the ACPI PM IO space be configured\r
	10	(responsible: OvmfPkg/PlatformPei/PlatformPei.inf)\r
	11	\r
	12	Our own entry point is responsible for confirming the SMI feature and for\r
	13	configuring it.\r
	14	\r
	15	Copyright (C) 2013, 2015, Red Hat, Inc.<BR>\r
	16	Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
	17	\r
b26f0cf9	18	SPDX-License-Identifier: BSD-2-Clause-Patent\r
c40e1a0c LE	19	\r
	20	**/\r
	21	\r
	22	#include <IndustryStandard/Q35MchIch9.h>\r
	23	#include <Library/BaseLib.h>\r
	24	#include <Library/DebugLib.h>\r
	25	#include <Library/IoLib.h>\r
	26	#include <Library/PcdLib.h>\r
	27	#include <Library/PciLib.h>\r
c40e1a0c LE	28	#include <Library/UefiBootServicesTableLib.h>\r
	29	#include <Protocol/S3SaveState.h>\r
	30	#include <Protocol/SmmControl2.h>\r
	31	\r
a316d7ac LE	32	#include "SmiFeatures.h"\r
a316d7ac LE	33	\r
c40e1a0c LE	34	//\r
	35	// Forward declaration.\r
	36	//\r
	37	STATIC\r
	38	VOID\r
	39	EFIAPI\r
	40	OnS3SaveStateInstalled (\r
	41	IN EFI_EVENT Event,\r
	42	IN VOID *Context\r
	43	);\r
	44	\r
	45	//\r
	46	// The absolute IO port address of the SMI Control and Enable Register. It is\r
	47	// only used to carry information from the entry point function to the\r
	48	// S3SaveState protocol installation callback, strictly before the runtime\r
	49	// phase.\r
	50	//\r
	51	STATIC UINTN mSmiEnable;\r
	52	\r
a316d7ac LE	53	//\r
	54	// Captures whether SMI feature negotiation is supported. The variable is only\r
	55	// used to carry this information from the entry point function to the\r
	56	// S3SaveState protocol installation callback.\r
	57	//\r
	58	STATIC BOOLEAN mSmiFeatureNegotiation;\r
	59	\r
c40e1a0c LE	60	//\r
	61	// Event signaled when an S3SaveState protocol interface is installed.\r
	62	//\r
	63	STATIC EFI_EVENT mS3SaveStateInstalled;\r
	64	\r
	65	/**\r
	66	Invokes SMI activation from either the preboot or runtime environment.\r
	67	\r
	68	This function generates an SMI.\r
	69	\r
	70	@param[in] This The EFI_SMM_CONTROL2_PROTOCOL instance.\r
	71	@param[in,out] CommandPort The value written to the command port.\r
	72	@param[in,out] DataPort The value written to the data port.\r
	73	@param[in] Periodic Optional mechanism to engender a periodic\r
	74	stream.\r
	75	@param[in] ActivationInterval Optional parameter to repeat at this\r
	76	period one time or, if the Periodic\r
	77	Boolean is set, periodically.\r
	78	\r
	79	@retval EFI_SUCCESS The SMI/PMI has been engendered.\r
	80	@retval EFI_DEVICE_ERROR The timing is unsupported.\r
	81	@retval EFI_INVALID_PARAMETER The activation period is unsupported.\r
	82	@retval EFI_INVALID_PARAMETER The last periodic activation has not been\r
	83	cleared.\r
	84	@retval EFI_NOT_STARTED The SMM base service has not been initialized.\r
	85	**/\r
	86	STATIC\r
	87	EFI_STATUS\r
	88	EFIAPI\r
	89	SmmControl2DxeTrigger (\r
	90	IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,\r
	91	IN OUT UINT8 *CommandPort OPTIONAL,\r
	92	IN OUT UINT8 *DataPort OPTIONAL,\r
	93	IN BOOLEAN Periodic OPTIONAL,\r
	94	IN UINTN ActivationInterval OPTIONAL\r
	95	)\r
	96	{\r
	97	//\r
	98	// No support for queued or periodic activation.\r
	99	//\r
	100	if (Periodic \|\| ActivationInterval > 0) {\r
	101	return EFI_DEVICE_ERROR;\r
	102	}\r
	103	\r
	104	//\r
	105	// The so-called "Advanced Power Management Status Port Register" is in fact\r
	106	// a generic data passing register, between the caller and the SMI\r
	107	// dispatcher. The ICH9 spec calls it "scratchpad register" -- calling it\r
	108	// "status" elsewhere seems quite the misnomer. Status registers usually\r
	109	// report about hardware status, while this register is fully governed by\r
	110	// software.\r
	111	//\r
	112	// Write to the status register first, as this won't trigger the SMI just\r
	113	// yet. Then write to the control register.\r
	114	//\r
	115	IoWrite8 (ICH9_APM_STS, DataPort == NULL ? 0 : *DataPort);\r
	116	IoWrite8 (ICH9_APM_CNT, CommandPort == NULL ? 0 : *CommandPort);\r
	117	return EFI_SUCCESS;\r
	118	}\r
	119	\r
	120	/**\r
	121	Clears any system state that was created in response to the Trigger() call.\r
	122	\r
	123	This function acknowledges and causes the deassertion of the SMI activation\r
124	source.\r
125	\r
126	@param[in] This The EFI_SMM_CONTROL2_PROTOCOL instance.\r
127	@param[in] Periodic Optional parameter to repeat at this period\r
128	one time\r
129	\r
130	@retval EFI_SUCCESS The SMI/PMI has been engendered.\r
131	@retval EFI_DEVICE_ERROR The source could not be cleared.\r
132	@retval EFI_INVALID_PARAMETER The service did not support the Periodic input\r
133	argument.\r
134	**/\r
135	STATIC\r
136	EFI_STATUS\r
137	EFIAPI\r
138	SmmControl2DxeClear (\r
139	IN CONST EFI_SMM_CONTROL2_PROTOCOL *This,\r
140	IN BOOLEAN Periodic OPTIONAL\r
141	)\r
142	{\r
143	if (Periodic) {\r
144	return EFI_INVALID_PARAMETER;\r
145	}\r
146	\r
147	//\r
148	// The PI spec v1.4 explains that Clear() is only supposed to clear software\r
149	// status; it is not in fact responsible for deasserting the SMI. It gives\r
150	// two reasons for this: (a) many boards clear the SMI automatically when\r
151	// entering SMM, (b) if Clear() actually deasserted the SMI, then it could\r
152	// incorrectly suppress an SMI that was asynchronously asserted between the\r
153	// last return of the SMI handler and the call made to Clear().\r
154	//\r
155	// In fact QEMU automatically deasserts CPU_INTERRUPT_SMI in:\r
156	// - x86_cpu_exec_interrupt() [target-i386/seg_helper.c], and\r
157	// - kvm_arch_pre_run() [target-i386/kvm.c].\r
158	//\r
159	// So, nothing to do here.\r
160	//\r
161	return EFI_SUCCESS;\r
162	}\r
163	\r
164	STATIC EFI_SMM_CONTROL2_PROTOCOL mControl2 = {\r
165	&SmmControl2DxeTrigger,\r
166	&SmmControl2DxeClear,\r
167	MAX_UINTN // MinimumTriggerPeriod -- we don't support periodic SMIs\r
168	};\r
169	\r
170	//\r
171	// Entry point of this driver.\r
172	//\r
173	EFI_STATUS\r
174	EFIAPI\r
175	SmmControl2DxeEntryPoint (\r
176	IN EFI_HANDLE ImageHandle,\r
177	IN EFI_SYSTEM_TABLE *SystemTable\r
178	)\r
179	{\r
180	UINT32 PmBase;\r
181	UINT32 SmiEnableVal;\r
182	EFI_STATUS Status;\r
183	\r
184	//\r
185	// This module should only be included if SMRAM support is required.\r
186	//\r
187	ASSERT (FeaturePcdGet (PcdSmmSmramRequire));\r
188	\r
189	//\r
190	// Calculate the absolute IO port address of the SMI Control and Enable\r
191	// Register. (As noted at the top, the PEI phase has left us with a working\r
192	// ACPI PM IO space.)\r
193	//\r
194	PmBase = PciRead32 (POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE)) &\r
195	ICH9_PMBASE_MASK;\r
196	mSmiEnable = PmBase + ICH9_PMBASE_OFS_SMI_EN;\r
197	\r
198	//\r
199	// If APMC_EN is pre-set in SMI_EN, that's QEMU's way to tell us that SMI\r
200	// support is not available. (For example due to KVM lacking it.) Otherwise,\r
201	// this bit is clear after each reset.\r
202	//\r
203	SmiEnableVal = IoRead32 (mSmiEnable);\r
204	if ((SmiEnableVal & ICH9_SMI_EN_APMC_EN) != 0) {\r
70d5086c	205	DEBUG ((DEBUG_ERROR, "%a: this Q35 implementation lacks SMI\n",\r
c40e1a0c LE	206	__FUNCTION__));\r
	207	goto FatalError;\r
	208	}\r
	209	\r
	210	//\r
	211	// Otherwise, configure the board to inject an SMI when ICH9_APM_CNT is\r
	212	// written to. (See the Trigger() method above.)\r
	213	//\r
	214	SmiEnableVal \|= ICH9_SMI_EN_APMC_EN \| ICH9_SMI_EN_GBL_SMI_EN;\r
	215	IoWrite32 (mSmiEnable, SmiEnableVal);\r
	216	\r
	217	//\r
	218	// Prevent software from undoing the above (until platform reset).\r
	219	//\r
	220	PciOr16 (POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1),\r
	221	ICH9_GEN_PMCON_1_SMI_LOCK);\r
	222	\r
	223	//\r
	224	// If we can clear GBL_SMI_EN now, that means QEMU's SMI support is not\r
	225	// appropriate.\r
	226	//\r
	227	IoWrite32 (mSmiEnable, SmiEnableVal & ~(UINT32)ICH9_SMI_EN_GBL_SMI_EN);\r
	228	if (IoRead32 (mSmiEnable) != SmiEnableVal) {\r
70d5086c	229	DEBUG ((DEBUG_ERROR, "%a: failed to lock down GBL_SMI_EN\n",\r
c40e1a0c LE	230	__FUNCTION__));\r
	231	goto FatalError;\r
	232	}\r
	233	\r
a316d7ac LE	234	//\r
	235	// QEMU can inject SMIs in different ways, negotiate our preferences.\r
	236	//\r
	237	mSmiFeatureNegotiation = NegotiateSmiFeatures ();\r
	238	\r
5b5f10d7	239	if (PcdGetBool (PcdAcpiS3Enable)) {\r
c40e1a0c LE	240	VOID *Registration;\r
	241	\r
	242	//\r
	243	// On S3 resume the above register settings have to be repeated. Register a\r
	244	// protocol notify callback that, when boot script saving becomes\r
	245	// available, saves operations equivalent to the above to the boot script.\r
	246	//\r
	247	Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,\r
	248	OnS3SaveStateInstalled, NULL /* Context */,\r
	249	&mS3SaveStateInstalled);\r
	250	if (EFI_ERROR (Status)) {\r
70d5086c	251	DEBUG ((DEBUG_ERROR, "%a: CreateEvent: %r\n", __FUNCTION__, Status));\r
c40e1a0c LE	252	goto FatalError;\r
	253	}\r
	254	\r
	255	Status = gBS->RegisterProtocolNotify (&gEfiS3SaveStateProtocolGuid,\r
	256	mS3SaveStateInstalled, &Registration);\r
	257	if (EFI_ERROR (Status)) {\r
70d5086c	258	DEBUG ((DEBUG_ERROR, "%a: RegisterProtocolNotify: %r\n", __FUNCTION__,\r
c40e1a0c LE	259	Status));\r
	260	goto ReleaseEvent;\r
	261	}\r
	262	\r
	263	//\r
	264	// Kick the event right now -- maybe the boot script is already saveable.\r
	265	//\r
	266	Status = gBS->SignalEvent (mS3SaveStateInstalled);\r
	267	if (EFI_ERROR (Status)) {\r
70d5086c	268	DEBUG ((DEBUG_ERROR, "%a: SignalEvent: %r\n", __FUNCTION__, Status));\r
c40e1a0c LE	269	goto ReleaseEvent;\r
	270	}\r
	271	}\r
	272	\r
	273	//\r
	274	// We have no pointers to convert to virtual addresses. The handle itself\r
	275	// doesn't matter, as protocol services are not accessible at runtime.\r
	276	//\r
	277	Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,\r
	278	&gEfiSmmControl2ProtocolGuid, &mControl2,\r
	279	NULL);\r
	280	if (EFI_ERROR (Status)) {\r
70d5086c	281	DEBUG ((DEBUG_ERROR, "%a: InstallMultipleProtocolInterfaces: %r\n",\r
c40e1a0c LE	282	__FUNCTION__, Status));\r
	283	goto ReleaseEvent;\r
	284	}\r
	285	\r
	286	return EFI_SUCCESS;\r
	287	\r
	288	ReleaseEvent:\r
	289	if (mS3SaveStateInstalled != NULL) {\r
	290	gBS->CloseEvent (mS3SaveStateInstalled);\r
	291	}\r
	292	\r
	293	FatalError:\r
	294	//\r
	295	// We really don't want to continue in this case.\r
	296	//\r
	297	ASSERT (FALSE);\r
	298	CpuDeadLoop ();\r
	299	return EFI_UNSUPPORTED;\r
	300	}\r
	301	\r
	302	/**\r
	303	Notification callback for S3SaveState installation.\r
	304	\r
	305	@param[in] Event Event whose notification function is being invoked.\r
	306	\r
	307	@param[in] Context The pointer to the notification function's context, which\r
	308	is implementation-dependent.\r
	309	**/\r
	310	STATIC\r
	311	VOID\r
	312	EFIAPI\r
	313	OnS3SaveStateInstalled (\r
	314	IN EFI_EVENT Event,\r
	315	IN VOID *Context\r
	316	)\r
	317	{\r
	318	EFI_STATUS Status;\r
	319	EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState;\r
	320	UINT32 SmiEnOrMask, SmiEnAndMask;\r
7ecfa0aa	321	UINT64 GenPmCon1Address;\r
c40e1a0c LE	322	UINT16 GenPmCon1OrMask, GenPmCon1AndMask;\r
	323	\r
	324	ASSERT (Event == mS3SaveStateInstalled);\r
	325	\r
	326	Status = gBS->LocateProtocol (&gEfiS3SaveStateProtocolGuid,\r
	327	NULL /* Registration /, (VOID *)&S3SaveState);\r
	328	if (EFI_ERROR (Status)) {\r
	329	return;\r
	330	}\r
	331	\r
	332	//\r
	333	// These operations were originally done, verified and explained in the entry\r
	334	// point function of the driver.\r
	335	//\r
	336	SmiEnOrMask = ICH9_SMI_EN_APMC_EN \| ICH9_SMI_EN_GBL_SMI_EN;\r
	337	SmiEnAndMask = MAX_UINT32;\r
	338	Status = S3SaveState->Write (\r
	339	S3SaveState,\r
	340	EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE,\r
	341	EfiBootScriptWidthUint32,\r
	342	(UINT64)mSmiEnable,\r
	343	&SmiEnOrMask,\r
	344	&SmiEnAndMask\r
	345	);\r
	346	if (EFI_ERROR (Status)) {\r
70d5086c	347	DEBUG ((DEBUG_ERROR, "%a: EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE: %r\n",\r
c40e1a0c LE	348	__FUNCTION__, Status));\r
	349	ASSERT (FALSE);\r
	350	CpuDeadLoop ();\r
	351	}\r
	352	\r
7ecfa0aa LE	353	GenPmCon1Address = POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS (\r
7ecfa0aa LE	354	ICH9_GEN_PMCON_1);\r
c40e1a0c LE	355	GenPmCon1OrMask = ICH9_GEN_PMCON_1_SMI_LOCK;\r
	356	GenPmCon1AndMask = MAX_UINT16;\r
	357	Status = S3SaveState->Write (\r
	358	S3SaveState,\r
	359	EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE,\r
	360	EfiBootScriptWidthUint16,\r
7ecfa0aa	361	GenPmCon1Address,\r
c40e1a0c LE	362	&GenPmCon1OrMask,\r
	363	&GenPmCon1AndMask\r
	364	);\r
	365	if (EFI_ERROR (Status)) {\r
70d5086c	366	DEBUG ((DEBUG_ERROR,\r
c40e1a0c LE	367	"%a: EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE: %r\n", __FUNCTION__,\r
	368	Status));\r
	369	ASSERT (FALSE);\r
	370	CpuDeadLoop ();\r
	371	}\r
	372	\r
36a6aa6c LE	373	DEBUG ((DEBUG_VERBOSE, "%a: chipset boot script saved\n", __FUNCTION__));\r
36a6aa6c LE	374	\r
a316d7ac LE	375	//\r
	376	// Append a boot script fragment that re-selects the negotiated SMI features.\r
	377	//\r
	378	if (mSmiFeatureNegotiation) {\r
36a6aa6c	379	SaveSmiFeatures ();\r
a316d7ac LE	380	}\r
a316d7ac LE	381	\r
c40e1a0c LE	382	gBS->CloseEvent (Event);\r
	383	mS3SaveStateInstalled = NULL;\r
	384	}\r