OvmfPkg/XenPlatformPei: no hvmloader: get the E820 table via hypercall

[mirror_edk2.git] / OvmfPkg / XenPlatformPei / MemDetect.c

/**@file\r
  Memory Detection for Virtual Machines.\r
\r
  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2019, Citrix Systems, Inc.\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
Module Name:\r
\r
  MemDetect.c\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <PiPei.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/ResourcePublicationLib.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
\r
UINT8 mPhysMemAddressWidth;\r
\r
STATIC UINT32 mS3AcpiReservedMemoryBase;\r
STATIC UINT32 mS3AcpiReservedMemorySize;\r
\r
STATIC UINT16 mQ35TsegMbytes;\r
\r
VOID\r
Q35TsegMbytesInitialization (\r
  VOID\r
  )\r
{\r
  UINT16        ExtendedTsegMbytes;\r
  RETURN_STATUS PcdStatus;\r
\r
  if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r
    DEBUG ((\r
      DEBUG_ERROR,\r
      "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r
      "only DID=0x%04x (Q35) is supported\n",\r
      __FUNCTION__,\r
      mHostBridgeDevId,\r
      INTEL_Q35_MCH_DEVICE_ID\r
      ));\r
    ASSERT (FALSE);\r
    CpuDeadLoop ();\r
  }\r
\r
  //\r
  // Check if QEMU offers an extended TSEG.\r
  //\r
  // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r
  // register, and reading back the register.\r
  //\r
  // On a QEMU machine type that does not offer an extended TSEG, the initial\r
  // write overwrites whatever value a malicious guest OS may have placed in\r
  // the (unimplemented) register, before entering S3 or rebooting.\r
  // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r
  //\r
  // On a QEMU machine type that offers an extended TSEG, the initial write\r
  // triggers an update to the register. Subsequently, the value read back\r
  // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r
  // number of megabytes.\r
  //\r
  PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r
  ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r
  if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r
    mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r
    return;\r
  }\r
\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "%a: QEMU offers an extended TSEG (%d MB)\n",\r
    __FUNCTION__,\r
    ExtendedTsegMbytes\r
    ));\r
  PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r
  ASSERT_RETURN_ERROR (PcdStatus);\r
  mQ35TsegMbytes = ExtendedTsegMbytes;\r
}\r
\r
\r
UINT32\r
GetSystemMemorySizeBelow4gb (\r
  VOID\r
  )\r
{\r
  UINT8 Cmos0x34;\r
  UINT8 Cmos0x35;\r
\r
  //\r
  // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r
  // * CMOS(0x35) is the high byte\r
  // * CMOS(0x34) is the low byte\r
  // * The size is specified in 64kb chunks\r
  // * Since this is memory above 16MB, the 16MB must be added\r
  //   into the calculation to get the total memory size.\r
  //\r
\r
  Cmos0x34 = (UINT8) CmosRead8 (0x34);\r
  Cmos0x35 = (UINT8) CmosRead8 (0x35);\r
\r
  return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
}\r
\r
\r
STATIC\r
UINT64\r
GetSystemMemorySizeAbove4gb (\r
  )\r
{\r
  UINT32 Size;\r
  UINTN  CmosIndex;\r
\r
  //\r
  // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r
  // * CMOS(0x5d) is the most significant size byte\r
  // * CMOS(0x5c) is the middle size byte\r
  // * CMOS(0x5b) is the least significant size byte\r
  // * The size is specified in 64kb chunks\r
  //\r
\r
  Size = 0;\r
  for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r
    Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r
  }\r
\r
  return LShiftU64 (Size, 16);\r
}\r
\r
\r
/**\r
  Return the highest address that DXE could possibly use, plus one.\r
**/\r
STATIC\r
UINT64\r
GetFirstNonAddress (\r
  VOID\r
  )\r
{\r
  UINT64               FirstNonAddress;\r
  UINT64               Pci64Base, Pci64Size;\r
  RETURN_STATUS        PcdStatus;\r
\r
  FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r
\r
  //\r
  // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r
  // resources to 32-bit anyway. See DegradeResource() in\r
  // "PciResourceSupport.c".\r
  //\r
#ifdef MDE_CPU_IA32\r
  if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
    return FirstNonAddress;\r
  }\r
#endif\r
\r
  //\r
  // Otherwise, in order to calculate the highest address plus one, we must\r
  // consider the 64-bit PCI host aperture too. Fetch the default size.\r
  //\r
  Pci64Size = PcdGet64 (PcdPciMmio64Size);\r
\r
  if (Pci64Size == 0) {\r
    if (mBootMode != BOOT_ON_S3_RESUME) {\r
      DEBUG ((DEBUG_INFO, "%a: disabling 64-bit PCI host aperture\n",\r
        __FUNCTION__));\r
      PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r
      ASSERT_RETURN_ERROR (PcdStatus);\r
    }\r
\r
    //\r
    // There's nothing more to do; the amount of memory above 4GB fully\r
    // determines the highest address plus one. The memory hotplug area (see\r
    // below) plays no role for the firmware in this case.\r
    //\r
    return FirstNonAddress;\r
  }\r
\r
  //\r
  // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r
  // that the host can map it with 1GB hugepages. Follow suit.\r
  //\r
  Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r
  Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);\r
\r
  //\r
  // The 64-bit PCI host aperture should also be "naturally" aligned. The\r
  // alignment is determined by rounding the size of the aperture down to the\r
  // next smaller or equal power of two. That is, align the aperture by the\r
  // largest BAR size that can fit into it.\r
  //\r
  Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));\r
\r
  if (mBootMode != BOOT_ON_S3_RESUME) {\r
    //\r
    // The core PciHostBridgeDxe driver will automatically add this range to\r
    // the GCD memory space map through our PciHostBridgeLib instance; here we\r
    // only need to set the PCDs.\r
    //\r
    PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);\r
    ASSERT_RETURN_ERROR (PcdStatus);\r
    PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r
    ASSERT_RETURN_ERROR (PcdStatus);\r
\r
    DEBUG ((DEBUG_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r
      __FUNCTION__, Pci64Base, Pci64Size));\r
  }\r
\r
  //\r
  // The useful address space ends with the 64-bit PCI host aperture.\r
  //\r
  FirstNonAddress = Pci64Base + Pci64Size;\r
  return FirstNonAddress;\r
}\r
\r
\r
/**\r
  Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r
**/\r
VOID\r
AddressWidthInitialization (\r
  VOID\r
  )\r
{\r
  UINT64 FirstNonAddress;\r
\r
  //\r
  // As guest-physical memory size grows, the permanent PEI RAM requirements\r
  // are dominated by the identity-mapping page tables built by the DXE IPL.\r
  // The DXL IPL keys off of the physical address bits advertized in the CPU\r
  // HOB. To conserve memory, we calculate the minimum address width here.\r
  //\r
  FirstNonAddress      = GetFirstNonAddress ();\r
  mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r
\r
  //\r
  // If FirstNonAddress is not an integral power of two, then we need an\r
  // additional bit.\r
  //\r
  if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r
    ++mPhysMemAddressWidth;\r
  }\r
\r
  //\r
  // The minimum address width is 36 (covers up to and excluding 64 GB, which\r
  // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r
  // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r
  // can simply assert that here, since 48 bits are good enough for 256 TB.\r
  //\r
  if (mPhysMemAddressWidth <= 36) {\r
    mPhysMemAddressWidth = 36;\r
  }\r
  ASSERT (mPhysMemAddressWidth <= 48);\r
}\r
\r
\r
/**\r
  Calculate the cap for the permanent PEI memory.\r
**/\r
STATIC\r
UINT32\r
GetPeiMemoryCap (\r
  VOID\r
  )\r
{\r
  BOOLEAN Page1GSupport;\r
  UINT32  RegEax;\r
  UINT32  RegEdx;\r
  UINT32  Pml4Entries;\r
  UINT32  PdpEntries;\r
  UINTN   TotalPages;\r
\r
  //\r
  // If DXE is 32-bit, then just return the traditional 64 MB cap.\r
  //\r
#ifdef MDE_CPU_IA32\r
  if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
    return SIZE_64MB;\r
  }\r
#endif\r
\r
  //\r
  // Dependent on physical address width, PEI memory allocations can be\r
  // dominated by the page tables built for 64-bit DXE. So we key the cap off\r
  // of those. The code below is based on CreateIdentityMappingPageTables() in\r
  // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r
  //\r
  Page1GSupport = FALSE;\r
  if (PcdGetBool (PcdUse1GPageTable)) {\r
    AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
    if (RegEax >= 0x80000001) {\r
      AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
      if ((RegEdx & BIT26) != 0) {\r
        Page1GSupport = TRUE;\r
      }\r
    }\r
  }\r
\r
  if (mPhysMemAddressWidth <= 39) {\r
    Pml4Entries = 1;\r
    PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r
    ASSERT (PdpEntries <= 0x200);\r
  } else {\r
    Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r
    ASSERT (Pml4Entries <= 0x200);\r
    PdpEntries = 512;\r
  }\r
\r
  TotalPages = Page1GSupport ? Pml4Entries + 1 :\r
                               (PdpEntries + 1) * Pml4Entries + 1;\r
  ASSERT (TotalPages <= 0x40201);\r
\r
  //\r
  // Add 64 MB for miscellaneous allocations. Note that for\r
  // mPhysMemAddressWidth values close to 36, the cap will actually be\r
  // dominated by this increment.\r
  //\r
  return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r
}\r
\r
\r
/**\r
  Publish PEI core memory\r
\r
  @return EFI_SUCCESS     The PEIM initialized successfully.\r
\r
**/\r
EFI_STATUS\r
PublishPeiMemory (\r
  VOID\r
  )\r
{\r
  EFI_STATUS                  Status;\r
  EFI_PHYSICAL_ADDRESS        MemoryBase;\r
  UINT64                      MemorySize;\r
  UINT32                      LowerMemorySize;\r
  UINT32                      PeiMemoryCap;\r
\r
  LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r
\r
  if (mBootMode == BOOT_ON_S3_RESUME) {\r
    MemoryBase = mS3AcpiReservedMemoryBase;\r
    MemorySize = mS3AcpiReservedMemorySize;\r
  } else {\r
    PeiMemoryCap = GetPeiMemoryCap ();\r
    DEBUG ((DEBUG_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r
      __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r
\r
    //\r
    // Determine the range of memory to use during PEI\r
    //\r
    MemoryBase =\r
      PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r
    MemorySize = LowerMemorySize - MemoryBase;\r
    if (MemorySize > PeiMemoryCap) {\r
      MemoryBase = LowerMemorySize - PeiMemoryCap;\r
      MemorySize = PeiMemoryCap;\r
    }\r
  }\r
\r
  //\r
  // Publish this memory to the PEI Core\r
  //\r
  Status = PublishSystemMemory(MemoryBase, MemorySize);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
}\r
\r
\r
/**\r
  Publish system RAM and reserve memory regions\r
\r
**/\r
VOID\r
InitializeRamRegions (\r
  VOID\r
  )\r
{\r
  XenPublishRamRegions ();\r
\r
  if (mBootMode != BOOT_ON_S3_RESUME) {\r
    //\r
    // Reserve the lock box storage area\r
    //\r
    // Since this memory range will be used on S3 resume, it must be\r
    // reserved as ACPI NVS.\r
    //\r
    // If S3 is unsupported, then various drivers might still write to the\r
    // LockBox area. We ought to prevent DXE from serving allocation requests\r
    // such that they would overlap the LockBox storage.\r
    //\r
    ZeroMem (\r
      (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
      (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r
      );\r
    BuildMemoryAllocationHob (\r
      (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r
      (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r
      EfiBootServicesData\r
      );\r
  }\r
}\r