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3b96221f AP |
1 | /**@file\r |
2 | Platform PEI driver\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
5 | Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r | |
6 | Copyright (c) 2019, Citrix Systems, Inc.\r | |
7 | \r | |
8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
9 | \r | |
10 | **/\r | |
11 | \r | |
12 | //\r | |
13 | // The package level header files this module uses\r | |
14 | //\r | |
15 | #include <PiPei.h>\r | |
16 | \r | |
17 | //\r | |
18 | // The Library classes this module consumes\r | |
19 | //\r | |
20 | #include <Library/BaseLib.h>\r | |
21 | #include <Library/DebugLib.h>\r | |
22 | #include <Library/HobLib.h>\r | |
23 | #include <Library/IoLib.h>\r | |
24 | #include <Library/MemoryAllocationLib.h>\r | |
25 | #include <Library/PcdLib.h>\r | |
26 | #include <Library/PciLib.h>\r | |
27 | #include <Library/PeimEntryPoint.h>\r | |
28 | #include <Library/PeiServicesLib.h>\r | |
29 | #include <Library/ResourcePublicationLib.h>\r | |
30 | #include <Guid/MemoryTypeInformation.h>\r | |
31 | #include <Ppi/MasterBootMode.h>\r | |
32 | #include <IndustryStandard/Pci22.h>\r | |
33 | #include <OvmfPlatforms.h>\r | |
34 | \r | |
35 | #include "Platform.h"\r | |
36 | #include "Cmos.h"\r | |
37 | \r | |
38 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
39 | { EfiACPIMemoryNVS, 0x004 },\r | |
40 | { EfiACPIReclaimMemory, 0x008 },\r | |
41 | { EfiReservedMemoryType, 0x004 },\r | |
42 | { EfiRuntimeServicesData, 0x024 },\r | |
43 | { EfiRuntimeServicesCode, 0x030 },\r | |
44 | { EfiBootServicesCode, 0x180 },\r | |
45 | { EfiBootServicesData, 0xF00 },\r | |
46 | { EfiMaxMemoryType, 0x000 }\r | |
47 | };\r | |
48 | \r | |
49 | \r | |
50 | EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r | |
51 | {\r | |
52 | EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r | |
53 | &gEfiPeiMasterBootModePpiGuid,\r | |
54 | NULL\r | |
55 | }\r | |
56 | };\r | |
57 | \r | |
58 | \r | |
59 | UINT16 mHostBridgeDevId;\r | |
60 | \r | |
61 | EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r | |
62 | \r | |
63 | \r | |
64 | VOID\r | |
65 | AddIoMemoryBaseSizeHob (\r | |
66 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
67 | UINT64 MemorySize\r | |
68 | )\r | |
69 | {\r | |
70 | BuildResourceDescriptorHob (\r | |
71 | EFI_RESOURCE_MEMORY_MAPPED_IO,\r | |
72 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
73 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
74 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
75 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
76 | MemoryBase,\r | |
77 | MemorySize\r | |
78 | );\r | |
79 | }\r | |
80 | \r | |
81 | VOID\r | |
82 | AddReservedMemoryBaseSizeHob (\r | |
83 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
84 | UINT64 MemorySize,\r | |
85 | BOOLEAN Cacheable\r | |
86 | )\r | |
87 | {\r | |
88 | BuildResourceDescriptorHob (\r | |
89 | EFI_RESOURCE_MEMORY_RESERVED,\r | |
90 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
91 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
92 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
93 | (Cacheable ?\r | |
94 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
95 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
96 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r | |
97 | 0\r | |
98 | ) |\r | |
99 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
100 | MemoryBase,\r | |
101 | MemorySize\r | |
102 | );\r | |
103 | }\r | |
104 | \r | |
24465c38 AP |
105 | VOID\r |
106 | AddReservedMemoryRangeHob (\r | |
107 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
108 | EFI_PHYSICAL_ADDRESS MemoryLimit,\r | |
109 | BOOLEAN Cacheable\r | |
110 | )\r | |
111 | {\r | |
112 | AddReservedMemoryBaseSizeHob (MemoryBase,\r | |
113 | (UINT64)(MemoryLimit - MemoryBase), Cacheable);\r | |
114 | }\r | |
115 | \r | |
3b96221f AP |
116 | VOID\r |
117 | AddIoMemoryRangeHob (\r | |
118 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
119 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
120 | )\r | |
121 | {\r | |
122 | AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
123 | }\r | |
124 | \r | |
125 | \r | |
126 | VOID\r | |
127 | AddMemoryBaseSizeHob (\r | |
128 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
129 | UINT64 MemorySize\r | |
130 | )\r | |
131 | {\r | |
132 | BuildResourceDescriptorHob (\r | |
133 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
134 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
135 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
136 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
137 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
138 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
139 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
140 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
141 | MemoryBase,\r | |
142 | MemorySize\r | |
143 | );\r | |
144 | }\r | |
145 | \r | |
146 | \r | |
147 | VOID\r | |
148 | AddMemoryRangeHob (\r | |
149 | EFI_PHYSICAL_ADDRESS MemoryBase,\r | |
150 | EFI_PHYSICAL_ADDRESS MemoryLimit\r | |
151 | )\r | |
152 | {\r | |
153 | AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r | |
154 | }\r | |
155 | \r | |
156 | \r | |
157 | VOID\r | |
158 | MemMapInitialization (\r | |
159 | VOID\r | |
160 | )\r | |
161 | {\r | |
162 | UINT64 PciIoBase;\r | |
163 | UINT64 PciIoSize;\r | |
164 | RETURN_STATUS PcdStatus;\r | |
165 | \r | |
166 | PciIoBase = 0xC000;\r | |
167 | PciIoSize = 0x4000;\r | |
168 | \r | |
169 | //\r | |
170 | // Create Memory Type Information HOB\r | |
171 | //\r | |
172 | BuildGuidDataHob (\r | |
173 | &gEfiMemoryTypeInformationGuid,\r | |
174 | mDefaultMemoryTypeInformation,\r | |
175 | sizeof(mDefaultMemoryTypeInformation)\r | |
176 | );\r | |
177 | \r | |
178 | //\r | |
179 | // Video memory + Legacy BIOS region\r | |
180 | //\r | |
181 | AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r | |
182 | \r | |
183 | //\r | |
184 | // Add PCI IO Port space available for PCI resource allocations.\r | |
185 | //\r | |
186 | BuildResourceDescriptorHob (\r | |
187 | EFI_RESOURCE_IO,\r | |
188 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
189 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r | |
190 | PciIoBase,\r | |
191 | PciIoSize\r | |
192 | );\r | |
193 | PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r | |
194 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
195 | PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r | |
196 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
197 | }\r | |
198 | \r | |
199 | VOID\r | |
200 | PciExBarInitialization (\r | |
201 | VOID\r | |
202 | )\r | |
203 | {\r | |
204 | union {\r | |
205 | UINT64 Uint64;\r | |
206 | UINT32 Uint32[2];\r | |
207 | } PciExBarBase;\r | |
208 | \r | |
209 | //\r | |
210 | // We only support the 256MB size for the MMCONFIG area:\r | |
211 | // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r | |
212 | //\r | |
213 | // The masks used below enforce the Q35 requirements that the MMCONFIG area\r | |
214 | // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r | |
215 | //\r | |
216 | // Note that (b) also ensures that the minimum address width we have\r | |
217 | // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r | |
218 | // for DXE's page tables to cover the MMCONFIG area.\r | |
219 | //\r | |
220 | PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
221 | ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r | |
222 | ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r | |
223 | \r | |
224 | //\r | |
225 | // Clear the PCIEXBAREN bit first, before programming the high register.\r | |
226 | //\r | |
227 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r | |
228 | \r | |
229 | //\r | |
230 | // Program the high register. Then program the low register, setting the\r | |
231 | // MMCONFIG area size and enabling decoding at once.\r | |
232 | //\r | |
233 | PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r | |
234 | PciWrite32 (\r | |
235 | DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r | |
236 | PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r | |
237 | );\r | |
238 | }\r | |
239 | \r | |
240 | VOID\r | |
241 | MiscInitialization (\r | |
242 | VOID\r | |
243 | )\r | |
244 | {\r | |
245 | UINTN PmCmd;\r | |
246 | UINTN Pmba;\r | |
247 | UINT32 PmbaAndVal;\r | |
248 | UINT32 PmbaOrVal;\r | |
249 | UINTN AcpiCtlReg;\r | |
250 | UINT8 AcpiEnBit;\r | |
251 | RETURN_STATUS PcdStatus;\r | |
252 | \r | |
253 | //\r | |
254 | // Disable A20 Mask\r | |
255 | //\r | |
256 | IoOr8 (0x92, BIT1);\r | |
257 | \r | |
258 | //\r | |
259 | // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r | |
260 | // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r | |
261 | // S3 resume as well, so we build it unconditionally.)\r | |
262 | //\r | |
263 | BuildCpuHob (mPhysMemAddressWidth, 16);\r | |
264 | \r | |
265 | //\r | |
266 | // Determine platform type and save Host Bridge DID to PCD\r | |
267 | //\r | |
268 | switch (mHostBridgeDevId) {\r | |
269 | case INTEL_82441_DEVICE_ID:\r | |
270 | PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r | |
271 | Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r | |
272 | PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r | |
273 | PmbaOrVal = PIIX4_PMBA_VALUE;\r | |
274 | AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r | |
275 | AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r | |
276 | break;\r | |
277 | case INTEL_Q35_MCH_DEVICE_ID:\r | |
278 | PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r | |
279 | Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r | |
280 | PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r | |
281 | PmbaOrVal = ICH9_PMBASE_VALUE;\r | |
282 | AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r | |
283 | AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r | |
284 | break;\r | |
285 | default:\r | |
198a8dc9 AP |
286 | if (XenPvhDetected ()) {\r |
287 | //\r | |
288 | // There is no PCI bus in this case\r | |
289 | //\r | |
290 | return;\r | |
291 | }\r | |
3b96221f AP |
292 | DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r |
293 | __FUNCTION__, mHostBridgeDevId));\r | |
294 | ASSERT (FALSE);\r | |
295 | return;\r | |
296 | }\r | |
297 | PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r | |
298 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
299 | \r | |
300 | //\r | |
301 | // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r | |
302 | // has been configured (e.g., by Xen) and skip the setup here.\r | |
303 | // This matches the logic in AcpiTimerLibConstructor ().\r | |
304 | //\r | |
305 | if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r | |
306 | //\r | |
307 | // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r | |
308 | // 1. set PMBA\r | |
309 | //\r | |
310 | PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r | |
311 | \r | |
312 | //\r | |
313 | // 2. set PCICMD/IOSE\r | |
314 | //\r | |
315 | PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r | |
316 | \r | |
317 | //\r | |
318 | // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r | |
319 | //\r | |
320 | PciOr8 (AcpiCtlReg, AcpiEnBit);\r | |
321 | }\r | |
322 | \r | |
323 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
324 | //\r | |
325 | // Set Root Complex Register Block BAR\r | |
326 | //\r | |
327 | PciWrite32 (\r | |
328 | POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r | |
329 | ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r | |
330 | );\r | |
331 | \r | |
332 | //\r | |
333 | // Set PCI Express Register Range Base Address\r | |
334 | //\r | |
335 | PciExBarInitialization ();\r | |
336 | }\r | |
337 | }\r | |
338 | \r | |
339 | \r | |
340 | VOID\r | |
341 | BootModeInitialization (\r | |
342 | VOID\r | |
343 | )\r | |
344 | {\r | |
345 | EFI_STATUS Status;\r | |
346 | \r | |
347 | if (CmosRead8 (0xF) == 0xFE) {\r | |
348 | mBootMode = BOOT_ON_S3_RESUME;\r | |
349 | }\r | |
350 | CmosWrite8 (0xF, 0x00);\r | |
351 | \r | |
352 | Status = PeiServicesSetBootMode (mBootMode);\r | |
353 | ASSERT_EFI_ERROR (Status);\r | |
354 | \r | |
355 | Status = PeiServicesInstallPpi (mPpiBootMode);\r | |
356 | ASSERT_EFI_ERROR (Status);\r | |
357 | }\r | |
358 | \r | |
359 | \r | |
360 | VOID\r | |
361 | ReserveEmuVariableNvStore (\r | |
362 | )\r | |
363 | {\r | |
364 | EFI_PHYSICAL_ADDRESS VariableStore;\r | |
365 | RETURN_STATUS PcdStatus;\r | |
366 | \r | |
367 | //\r | |
368 | // Allocate storage for NV variables early on so it will be\r | |
369 | // at a consistent address. Since VM memory is preserved\r | |
370 | // across reboots, this allows the NV variable storage to survive\r | |
371 | // a VM reboot.\r | |
372 | //\r | |
373 | VariableStore =\r | |
374 | (EFI_PHYSICAL_ADDRESS)(UINTN)\r | |
375 | AllocateRuntimePages (\r | |
376 | EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r | |
377 | );\r | |
378 | DEBUG ((DEBUG_INFO,\r | |
379 | "Reserved variable store memory: 0x%lX; size: %dkb\n",\r | |
380 | VariableStore,\r | |
381 | (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r | |
382 | ));\r | |
383 | PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r | |
384 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
385 | }\r | |
386 | \r | |
387 | \r | |
388 | VOID\r | |
389 | DebugDumpCmos (\r | |
390 | VOID\r | |
391 | )\r | |
392 | {\r | |
393 | UINT32 Loop;\r | |
394 | \r | |
395 | DEBUG ((DEBUG_INFO, "CMOS:\n"));\r | |
396 | \r | |
397 | for (Loop = 0; Loop < 0x80; Loop++) {\r | |
398 | if ((Loop % 0x10) == 0) {\r | |
399 | DEBUG ((DEBUG_INFO, "%02x:", Loop));\r | |
400 | }\r | |
401 | DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));\r | |
402 | if ((Loop % 0x10) == 0xf) {\r | |
403 | DEBUG ((DEBUG_INFO, "\n"));\r | |
404 | }\r | |
405 | }\r | |
406 | }\r | |
407 | \r | |
408 | \r | |
409 | \r | |
410 | /**\r | |
411 | Perform Platform PEI initialization.\r | |
412 | \r | |
413 | @param FileHandle Handle of the file being invoked.\r | |
414 | @param PeiServices Describes the list of possible PEI Services.\r | |
415 | \r | |
416 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
417 | \r | |
418 | **/\r | |
419 | EFI_STATUS\r | |
420 | EFIAPI\r | |
421 | InitializeXenPlatform (\r | |
422 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
423 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
424 | )\r | |
425 | {\r | |
426 | DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r | |
427 | \r | |
428 | DebugDumpCmos ();\r | |
429 | \r | |
430 | if (!XenDetect ()) {\r | |
431 | DEBUG ((DEBUG_ERROR, "ERROR: Xen isn't detected\n"));\r | |
432 | ASSERT (FALSE);\r | |
433 | CpuDeadLoop ();\r | |
434 | }\r | |
435 | \r | |
12998837 AP |
436 | XenConnect ();\r |
437 | \r | |
3b96221f AP |
438 | BootModeInitialization ();\r |
439 | AddressWidthInitialization ();\r | |
440 | \r | |
441 | //\r | |
442 | // Query Host Bridge DID\r | |
443 | //\r | |
444 | mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
445 | \r | |
446 | PublishPeiMemory ();\r | |
447 | \r | |
448 | InitializeRamRegions ();\r | |
449 | \r | |
450 | InitializeXen ();\r | |
451 | \r | |
452 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
453 | ReserveEmuVariableNvStore ();\r | |
454 | PeiFvInitialization ();\r | |
455 | MemMapInitialization ();\r | |
456 | }\r | |
457 | \r | |
458 | InstallClearCacheCallback ();\r | |
459 | AmdSevInitialize ();\r | |
460 | MiscInitialization ();\r | |
461 | \r | |
462 | return EFI_SUCCESS;\r | |
463 | }\r |