]> git.proxmox.com Git - mirror_edk2.git/blame - OvmfPkg/XenPlatformPei/Platform.c
projects / mirror_edk2.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OvmfPkg/XenPlatformPei: Introduce XenHvmloaderDetected
[mirror_edk2.git] / OvmfPkg / XenPlatformPei / Platform.c
CommitLineData
3b96221f
AP		 1/**@file\r
2 Platform PEI driver\r
3\r
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
6 Copyright (c) 2019, Citrix Systems, Inc.\r
7\r
8 SPDX-License-Identifier: BSD-2-Clause-Patent\r
9\r
10**/\r
11\r
12//\r
13// The package level header files this module uses\r
14//\r
15#include <PiPei.h>\r
16\r
17//\r
18// The Library classes this module consumes\r
19//\r
20#include <Library/BaseLib.h>\r
21#include <Library/DebugLib.h>\r
22#include <Library/HobLib.h>\r
23#include <Library/IoLib.h>\r
24#include <Library/MemoryAllocationLib.h>\r
25#include <Library/PcdLib.h>\r
26#include <Library/PciLib.h>\r
27#include <Library/PeimEntryPoint.h>\r
28#include <Library/PeiServicesLib.h>\r
29#include <Library/ResourcePublicationLib.h>\r
30#include <Guid/MemoryTypeInformation.h>\r
31#include <Ppi/MasterBootMode.h>\r
32#include <IndustryStandard/Pci22.h>\r
33#include <OvmfPlatforms.h>\r
34\r
35#include "Platform.h"\r
36#include "Cmos.h"\r
37\r
38EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
39 { EfiACPIMemoryNVS, 0x004 },\r
40 { EfiACPIReclaimMemory, 0x008 },\r
41 { EfiReservedMemoryType, 0x004 },\r
42 { EfiRuntimeServicesData, 0x024 },\r
43 { EfiRuntimeServicesCode, 0x030 },\r
44 { EfiBootServicesCode, 0x180 },\r
45 { EfiBootServicesData, 0xF00 },\r
46 { EfiMaxMemoryType, 0x000 }\r
47};\r
48\r
49\r
50EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
51 {\r
52 EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
53 &gEfiPeiMasterBootModePpiGuid,\r
54 NULL\r
55 }\r
56};\r
57\r
58\r
59UINT16 mHostBridgeDevId;\r
60\r
61EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
62\r
63\r
64VOID\r
65AddIoMemoryBaseSizeHob (\r
66 EFI_PHYSICAL_ADDRESS MemoryBase,\r
67 UINT64 MemorySize\r
68 )\r
69{\r
70 BuildResourceDescriptorHob (\r
71 EFI_RESOURCE_MEMORY_MAPPED_IO,\r
72 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
73 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
74 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
75 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
76 MemoryBase,\r
77 MemorySize\r
78 );\r
79}\r
80\r
81VOID\r
82AddReservedMemoryBaseSizeHob (\r
83 EFI_PHYSICAL_ADDRESS MemoryBase,\r
84 UINT64 MemorySize,\r
85 BOOLEAN Cacheable\r
86 )\r
87{\r
88 BuildResourceDescriptorHob (\r
89 EFI_RESOURCE_MEMORY_RESERVED,\r
90 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
91 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
92 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
93 (Cacheable ?\r
94 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
95 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
96 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
97 0\r
98 ) |\r
99 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
100 MemoryBase,\r
101 MemorySize\r
102 );\r
103}\r
104\r
105VOID\r
106AddIoMemoryRangeHob (\r
107 EFI_PHYSICAL_ADDRESS MemoryBase,\r
108 EFI_PHYSICAL_ADDRESS MemoryLimit\r
109 )\r
110{\r
111 AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
112}\r
113\r
114\r
115VOID\r
116AddMemoryBaseSizeHob (\r
117 EFI_PHYSICAL_ADDRESS MemoryBase,\r
118 UINT64 MemorySize\r
119 )\r
120{\r
121 BuildResourceDescriptorHob (\r
122 EFI_RESOURCE_SYSTEM_MEMORY,\r
123 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
124 EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
125 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
126 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
127 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
128 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
129 EFI_RESOURCE_ATTRIBUTE_TESTED,\r
130 MemoryBase,\r
131 MemorySize\r
132 );\r
133}\r
134\r
135\r
136VOID\r
137AddMemoryRangeHob (\r
138 EFI_PHYSICAL_ADDRESS MemoryBase,\r
139 EFI_PHYSICAL_ADDRESS MemoryLimit\r
140 )\r
141{\r
142 AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
143}\r
144\r
145\r
146VOID\r
147MemMapInitialization (\r
148 VOID\r
149 )\r
150{\r
151 UINT64 PciIoBase;\r
152 UINT64 PciIoSize;\r
153 RETURN_STATUS PcdStatus;\r
154\r
155 PciIoBase = 0xC000;\r
156 PciIoSize = 0x4000;\r
157\r
158 //\r
159 // Create Memory Type Information HOB\r
160 //\r
161 BuildGuidDataHob (\r
162 &gEfiMemoryTypeInformationGuid,\r
163 mDefaultMemoryTypeInformation,\r
164 sizeof(mDefaultMemoryTypeInformation)\r
165 );\r
166\r
167 //\r
168 // Video memory + Legacy BIOS region\r
169 //\r
170 AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
171\r
172 //\r
173 // Add PCI IO Port space available for PCI resource allocations.\r
174 //\r
175 BuildResourceDescriptorHob (\r
176 EFI_RESOURCE_IO,\r
177 EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
178 EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
179 PciIoBase,\r
180 PciIoSize\r
181 );\r
182 PcdStatus = PcdSet64S (PcdPciIoBase, PciIoBase);\r
183 ASSERT_RETURN_ERROR (PcdStatus);\r
184 PcdStatus = PcdSet64S (PcdPciIoSize, PciIoSize);\r
185 ASSERT_RETURN_ERROR (PcdStatus);\r
186}\r
187\r
188VOID\r
189PciExBarInitialization (\r
190 VOID\r
191 )\r
192{\r
193 union {\r
194 UINT64 Uint64;\r
195 UINT32 Uint32[2];\r
196 } PciExBarBase;\r
197\r
198 //\r
199 // We only support the 256MB size for the MMCONFIG area:\r
200 // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r
201 //\r
202 // The masks used below enforce the Q35 requirements that the MMCONFIG area\r
203 // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r
204 //\r
205 // Note that (b) also ensures that the minimum address width we have\r
206 // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r
207 // for DXE's page tables to cover the MMCONFIG area.\r
208 //\r
209 PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
210 ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r
211 ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r
212\r
213 //\r
214 // Clear the PCIEXBAREN bit first, before programming the high register.\r
215 //\r
216 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r
217\r
218 //\r
219 // Program the high register. Then program the low register, setting the\r
220 // MMCONFIG area size and enabling decoding at once.\r
221 //\r
222 PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r
223 PciWrite32 (\r
224 DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r
225 PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r
226 );\r
227}\r
228\r
229VOID\r
230MiscInitialization (\r
231 VOID\r
232 )\r
233{\r
234 UINTN PmCmd;\r
235 UINTN Pmba;\r
236 UINT32 PmbaAndVal;\r
237 UINT32 PmbaOrVal;\r
238 UINTN AcpiCtlReg;\r
239 UINT8 AcpiEnBit;\r
240 RETURN_STATUS PcdStatus;\r
241\r
242 //\r
243 // Disable A20 Mask\r
244 //\r
245 IoOr8 (0x92, BIT1);\r
246\r
247 //\r
248 // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
249 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
250 // S3 resume as well, so we build it unconditionally.)\r
251 //\r
252 BuildCpuHob (mPhysMemAddressWidth, 16);\r
253\r
254 //\r
255 // Determine platform type and save Host Bridge DID to PCD\r
256 //\r
257 switch (mHostBridgeDevId) {\r
258 case INTEL_82441_DEVICE_ID:\r
259 PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
260 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
261 PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
262 PmbaOrVal = PIIX4_PMBA_VALUE;\r
263 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
264 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
265 break;\r
266 case INTEL_Q35_MCH_DEVICE_ID:\r
267 PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
268 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
269 PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
270 PmbaOrVal = ICH9_PMBASE_VALUE;\r
271 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
272 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
273 break;\r
274 default:\r
275 DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
276 __FUNCTION__, mHostBridgeDevId));\r
277 ASSERT (FALSE);\r
278 return;\r
279 }\r
280 PcdStatus = PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
281 ASSERT_RETURN_ERROR (PcdStatus);\r
282\r
283 //\r
284 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
285 // has been configured (e.g., by Xen) and skip the setup here.\r
286 // This matches the logic in AcpiTimerLibConstructor ().\r
287 //\r
288 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
289 //\r
290 // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
291 // 1. set PMBA\r
292 //\r
293 PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
294\r
295 //\r
296 // 2. set PCICMD/IOSE\r
297 //\r
298 PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
299\r
300 //\r
301 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
302 //\r
303 PciOr8 (AcpiCtlReg, AcpiEnBit);\r
304 }\r
305\r
306 if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
307 //\r
308 // Set Root Complex Register Block BAR\r
309 //\r
310 PciWrite32 (\r
311 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
312 ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
313 );\r
314\r
315 //\r
316 // Set PCI Express Register Range Base Address\r
317 //\r
318 PciExBarInitialization ();\r
319 }\r
320}\r
321\r
322\r
323VOID\r
324BootModeInitialization (\r
325 VOID\r
326 )\r
327{\r
328 EFI_STATUS Status;\r
329\r
330 if (CmosRead8 (0xF) == 0xFE) {\r
331 mBootMode = BOOT_ON_S3_RESUME;\r
332 }\r
333 CmosWrite8 (0xF, 0x00);\r
334\r
335 Status = PeiServicesSetBootMode (mBootMode);\r
336 ASSERT_EFI_ERROR (Status);\r
337\r
338 Status = PeiServicesInstallPpi (mPpiBootMode);\r
339 ASSERT_EFI_ERROR (Status);\r
340}\r
341\r
342\r
343VOID\r
344ReserveEmuVariableNvStore (\r
345 )\r
346{\r
347 EFI_PHYSICAL_ADDRESS VariableStore;\r
348 RETURN_STATUS PcdStatus;\r
349\r
350 //\r
351 // Allocate storage for NV variables early on so it will be\r
352 // at a consistent address. Since VM memory is preserved\r
353 // across reboots, this allows the NV variable storage to survive\r
354 // a VM reboot.\r
355 //\r
356 VariableStore =\r
357 (EFI_PHYSICAL_ADDRESS)(UINTN)\r
358 AllocateRuntimePages (\r
359 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize))\r
360 );\r
361 DEBUG ((DEBUG_INFO,\r
362 "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
363 VariableStore,\r
364 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
365 ));\r
366 PcdStatus = PcdSet64S (PcdEmuVariableNvStoreReserved, VariableStore);\r
367 ASSERT_RETURN_ERROR (PcdStatus);\r
368}\r
369\r
370\r
371VOID\r
372DebugDumpCmos (\r
373 VOID\r
374 )\r
375{\r
376 UINT32 Loop;\r
377\r
378 DEBUG ((DEBUG_INFO, "CMOS:\n"));\r
379\r
380 for (Loop = 0; Loop < 0x80; Loop++) {\r
381 if ((Loop % 0x10) == 0) {\r
382 DEBUG ((DEBUG_INFO, "%02x:", Loop));\r
383 }\r
384 DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop)));\r
385 if ((Loop % 0x10) == 0xf) {\r
386 DEBUG ((DEBUG_INFO, "\n"));\r
387 }\r
388 }\r
389}\r
390\r
391\r
392\r
393/**\r
394 Perform Platform PEI initialization.\r
395\r
396 @param FileHandle Handle of the file being invoked.\r
397 @param PeiServices Describes the list of possible PEI Services.\r
398\r
399 @return EFI_SUCCESS The PEIM initialized successfully.\r
400\r
401**/\r
402EFI_STATUS\r
403EFIAPI\r
404InitializeXenPlatform (\r
405 IN EFI_PEI_FILE_HANDLE FileHandle,\r
406 IN CONST EFI_PEI_SERVICES **PeiServices\r
407 )\r
408{\r
409 DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));\r
410\r
411 DebugDumpCmos ();\r
412\r
413 if (!XenDetect ()) {\r
414 DEBUG ((DEBUG_ERROR, "ERROR: Xen isn't detected\n"));\r
415 ASSERT (FALSE);\r
416 CpuDeadLoop ();\r
417 }\r
418\r
419 BootModeInitialization ();\r
420 AddressWidthInitialization ();\r
421\r
422 //\r
423 // Query Host Bridge DID\r
424 //\r
425 mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
426\r
427 PublishPeiMemory ();\r
428\r
429 InitializeRamRegions ();\r
430\r
431 InitializeXen ();\r
432\r
433 if (mBootMode != BOOT_ON_S3_RESUME) {\r
434 ReserveEmuVariableNvStore ();\r
435 PeiFvInitialization ();\r
436 MemMapInitialization ();\r
437 }\r
438\r
439 InstallClearCacheCallback ();\r
440 AmdSevInitialize ();\r
441 MiscInitialization ();\r
442\r
443 return EFI_SUCCESS;\r
444}\r
EFI Development Kit II mirror for PVE