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7b202cb0 | 1 | ## @file\r |
31ed75a9 | 2 | # Public definitions for PcAtChipset package.\r |
3 | #\r | |
4 | # This package is designed to public interfaces and implementation which follows\r | |
5 | # PcAt defacto standard.\r | |
6 | #\r | |
36dd3c78 | 7 | # Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r |
e78aab9d | 8 | # Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r |
31ed75a9 | 9 | #\r |
e1d302e5 | 10 | # SPDX-License-Identifier: BSD-2-Clause-Patent\r |
31ed75a9 | 11 | #\r |
7b202cb0 | 12 | ##\r |
31ed75a9 | 13 | \r |
14 | [Defines]\r | |
15 | DEC_SPECIFICATION = 0x00010005\r | |
16 | PACKAGE_NAME = PcAtChipsetPkg\r | |
b414ac4d | 17 | PACKAGE_UNI_FILE = PcAtChipsetPkg.uni\r |
31ed75a9 | 18 | PACKAGE_GUID = B728689A-52D3-4b8c-AE89-2CE5514CC6DC\r |
9325f684 | 19 | PACKAGE_VERSION = 0.3\r |
31ed75a9 | 20 | \r |
986d1dfb | 21 | [Includes]\r |
22 | Include\r | |
23 | \r | |
24 | [LibraryClasses]\r | |
25 | ## @libraryclass Provides functions to manage I/O APIC Redirection Table Entries.\r | |
26 | #\r | |
27 | IoApicLib|Include/Library/IoApicLib.h\r | |
5a702acd | 28 | \r |
53705ed1 | 29 | [Guids]\r |
30 | gPcAtChipsetPkgTokenSpaceGuid = { 0x326ae723, 0xae32, 0x4589, { 0x98, 0xb8, 0xca, 0xc2, 0x3c, 0xdc, 0xc1, 0xb1 } }\r | |
31 | \r | |
f5f47471 RN |
32 | #\r |
33 | # [Error.gPcAtChipsetPkgTokenSpaceGuid]\r | |
34 | # 0x80000001 | Invalid value provided.\r | |
35 | #\r | |
36 | \r | |
986d1dfb | 37 | [PcdsFeatureFlag]\r |
b414ac4d QS |
38 | ## Indicates the HPET Timer will be configured to use MSI interrupts if the HPET timer supports them, or use I/O APIC interrupts.<BR><BR>\r |
39 | # TRUE - Configures the HPET Timer to use MSI interrupts if the HPET Timer supports them.<BR>\r | |
40 | # FALSE - Configures the HPET Timer to use I/O APIC interrupts.<BR>\r | |
41 | # @Prompt Configure HPET to use MSI.\r | |
986d1dfb | 42 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetMsiEnable|TRUE|BOOLEAN|0x00001000\r |
b414ac4d | 43 | \r |
856f592c | 44 | [PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule]\r |
b414ac4d | 45 | ## Pcd8259LegacyModeMask defines the default mask value for platform. This value is determined<BR><BR>\r |
31ed75a9 | 46 | # 1) If platform only support pure UEFI, value should be set to 0xFFFF or 0xFFFE;\r |
b414ac4d QS |
47 | # Because only clock interrupt is allowed in legacy mode in pure UEFI platform.<BR>\r |
48 | # 2) If platform install CSM and use thunk module:<BR>\r | |
5a702acd | 49 | # a) If thunk call provided by CSM binary requires some legacy interrupt support, the corresponding bit\r |
b414ac4d QS |
50 | # should be opened as 0.<BR>\r |
51 | # For example, if keyboard interfaces provided CSM binary use legacy keyboard interrupt in 8259 bit 1, then\r | |
52 | # the value should be set to 0xFFFC.<BR>\r | |
31ed75a9 | 53 | # b) If all thunk call provied by CSM binary do not require legacy interrupt support, value should be set\r |
b414ac4d | 54 | # to 0xFFFF or 0xFFFE.<BR>\r |
31ed75a9 | 55 | #\r |
31ed75a9 | 56 | # The default value of legacy mode mask could be changed by EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely\r |
5a702acd | 57 | # need change it except some special cases such as when initializing the CSM binary, it should be set to 0xFFFF to\r |
b414ac4d QS |
58 | # mask all legacy interrupt. Please restore the original legacy mask value if changing is made for these special case.<BR>\r |
59 | # @Prompt 8259 Legacy Mode mask.\r | |
1f44ee10 | 60 | gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x00000001\r |
5a702acd | 61 | \r |
e356f999 | 62 | ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy mode's interrrupt controller.\r |
b414ac4d QS |
63 | # For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r |
64 | # @Prompt 8259 Legacy Mode edge level.\r | |
1f44ee10 | 65 | gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x00000002\r |
e8bce4b4 | 66 | \r |
b414ac4d QS |
67 | ## Indicates if we need enable IsaAcpiCom1 device.<BR><BR>\r |
68 | # TRUE - Enables IsaAcpiCom1 device.<BR>\r | |
69 | # FALSE - Doesn't enable IsaAcpiCom1 device.<BR>\r | |
70 | # @Prompt Enable IsaAcpiCom1 device.\r | |
e8bce4b4 RN |
71 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom1Enable|TRUE|BOOLEAN|0x00000003\r |
72 | \r | |
b414ac4d QS |
73 | ## Indicates if we need enable IsaAcpiCom2 device.<BR><BR>\r |
74 | # TRUE - Enables IsaAcpiCom2 device.<BR>\r | |
75 | # FALSE - Doesn't enable IsaAcpiCom2 device.<BR>\r | |
76 | # @Prompt Enable IsaAcpiCom12 device.\r | |
e8bce4b4 RN |
77 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiCom2Enable|TRUE|BOOLEAN|0x00000004\r |
78 | \r | |
b414ac4d QS |
79 | ## Indicates if we need enable IsaAcpiPs2Keyboard device.<BR><BR>\r |
80 | # TRUE - Enables IsaAcpiPs2Keyboard device.<BR>\r | |
81 | # FALSE - Doesn't enable IsaAcpiPs2Keyboard device.<BR>\r | |
82 | # @Prompt Enable IsaAcpiPs2Keyboard device.\r | |
e8bce4b4 RN |
83 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2KeyboardEnable|TRUE|BOOLEAN|0x00000005\r |
84 | \r | |
b414ac4d QS |
85 | ## Indicates if we need enable IsaAcpiPs2Mouse device.<BR><BR>\r |
86 | # TRUE - Enables IsaAcpiPs2Mouse device.<BR>\r | |
87 | # FALSE - Doesn't enable IsaAcpiPs2Mouse device.<BR>\r | |
88 | # @Prompt Enable IsaAcpiPs2Mouse device.\r | |
e8bce4b4 RN |
89 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiPs2MouseEnable|TRUE|BOOLEAN|0x00000006\r |
90 | \r | |
b414ac4d QS |
91 | ## Indicates if we need enable IsaAcpiFloppyA device.<BR><BR>\r |
92 | # TRUE - Enables IsaAcpiFloppyA device.<BR>\r | |
93 | # FALSE - Doesn't enable IsaAcpiFloppyA device.<BR>\r | |
94 | # @Prompt Enable IsaAcpiFloppyA device.\r | |
e8bce4b4 RN |
95 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyAEnable|TRUE|BOOLEAN|0x00000007\r |
96 | \r | |
b414ac4d QS |
97 | ## Indicates if we need enable IsaAcpiFloppyB device.<BR><BR>\r |
98 | # TRUE - Enables IsaAcpiFloppyB device.<BR>\r | |
99 | # FALSE - Doesn't enable IsaAcpiFloppyB device.<BR>\r | |
100 | # @Prompt Enable IsaAcpiFloppyB device.\r | |
e8bce4b4 | 101 | gPcAtChipsetPkgTokenSpaceGuid.PcdIsaAcpiFloppyBEnable|TRUE|BOOLEAN|0x00000008\r |
986d1dfb | 102 | \r |
103 | ## This PCD specifies the base address of the HPET timer.\r | |
b414ac4d | 104 | # @Prompt HPET base address.\r |
986d1dfb | 105 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000|UINT32|0x00000009\r |
106 | \r | |
107 | ## This PCD specifies the Local APIC Interrupt Vector for the HPET Timer.\r | |
b414ac4d | 108 | # @Prompt HPET local APIC vector.\r |
986d1dfb | 109 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x0000000A\r |
110 | \r | |
111 | ## This PCD specifies the defaut period of the HPET Timer in 100 ns units.\r | |
112 | # The default value of 100000 100 ns units is the same as 10 ms.\r | |
b414ac4d | 113 | # @Prompt Default period of HPET timer.\r |
986d1dfb | 114 | gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B\r |
5a702acd | 115 | \r |
b414ac4d QS |
116 | ## This PCD specifies the base address of the IO APIC.\r |
117 | # @Prompt IO APIC base address.\r | |
986d1dfb | 118 | gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT32|0x0000000C\r |
1e5fff63 EL |
119 | \r |
120 | ## This PCD specifies the minimal valid year in RTC.\r | |
121 | # @Prompt Minimal valid year in RTC.\r | |
122 | gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1998|UINT16|0x0000000D\r | |
123 | \r | |
124 | ## This PCD specifies the maximal valid year in RTC.\r | |
125 | # @Prompt Maximal valid year in RTC.\r | |
f5f47471 | 126 | # @Expression 0x80000001 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear < gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear + 100\r |
fe320967 | 127 | gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2097|UINT16|0x0000000E\r |
5a702acd | 128 | \r |
83d1ffb9 LG |
129 | [PcdsFixedAtBuild, PcdsPatchableInModule]\r |
130 | ## Defines the ACPI register set base address.\r | |
5a702acd | 131 | # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r |
83d1ffb9 LG |
132 | # @Prompt ACPI Timer IO Port Address\r |
133 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress |0xFFFF|UINT16|0x00000010\r | |
134 | \r | |
135 | ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r | |
136 | # @Prompt ACPI Hardware PCI Bus Number\r | |
137 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00| UINT8|0x00000011\r | |
138 | \r | |
139 | ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r | |
5a702acd | 140 | # The invalid 0xFF is as its default value. It must be configured to the real value.\r |
83d1ffb9 LG |
141 | # @Prompt ACPI Hardware PCI Device Number\r |
142 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0xFF| UINT8|0x00000012\r | |
143 | \r | |
144 | ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.\r | |
5a702acd | 145 | # The invalid 0xFF is as its default value. It must be configured to the real value.\r |
83d1ffb9 LG |
146 | # @Prompt ACPI Hardware PCI Function Number\r |
147 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0xFF| UINT8|0x00000013\r | |
5a702acd | 148 | \r |
83d1ffb9 | 149 | ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.\r |
5a702acd | 150 | # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r |
83d1ffb9 LG |
151 | # @Prompt ACPI Hardware PCI Register Offset\r |
152 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0xFFFF|UINT16|0x00000014\r | |
5a702acd | 153 | \r |
83d1ffb9 LG |
154 | ## Defines the bit mask that must be set to enable the APIC hardware register BAR.\r |
155 | # @Prompt ACPI Hardware PCI Bar Enable BitMask\r | |
156 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x00| UINT8|0x00000015\r | |
5a702acd | 157 | \r |
83d1ffb9 | 158 | ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.\r |
5a702acd | 159 | # The invalid 0xFFFF is as its default value. It must be configured to the real value.\r |
83d1ffb9 LG |
160 | # @Prompt ACPI Hardware PCI Bar Register Offset\r |
161 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0xFFFF|UINT16|0x00000016\r | |
162 | \r | |
163 | ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.\r | |
164 | # @Prompt Offset to 32-bit Timer register in ACPI BAR\r | |
165 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008|UINT16|0x00000017\r | |
b414ac4d | 166 | \r |
9ff926d6 LG |
167 | ## Defines the bit mask to retrieve ACPI IO Port Base Address\r |
168 | # @Prompt ACPI IO Port Base Address Mask\r | |
169 | gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFE|UINT16|0x00000018\r | |
170 | \r | |
a38b89c7 LG |
171 | ## Reset Control Register address in I/O space.\r |
172 | # @Prompt Reset Control Register address\r | |
173 | gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlRegister|0x64|UINT64|0x00000019\r | |
174 | \r | |
175 | ## 8bit Reset Control Register value for cold reset.\r | |
176 | # @Prompt Reset Control Register value for cold reset\r | |
177 | gPcAtChipsetPkgTokenSpaceGuid.PcdResetControlValueColdReset|0xFE|UINT8|0x0000001A\r | |
178 | \r | |
e78aab9d LD |
179 | ## Specifies the initial value for Register_A in RTC.\r |
180 | # @Prompt Initial value for Register_A in RTC.\r | |
181 | gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterA|0x26|UINT8|0x0000001B\r | |
182 | \r | |
183 | ## Specifies the initial value for Register_B in RTC.\r | |
184 | # @Prompt Initial value for Register_B in RTC.\r | |
185 | gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterB|0x02|UINT8|0x0000001C\r | |
186 | \r | |
187 | ## Specifies the initial value for Register_D in RTC.\r | |
188 | # @Prompt Initial value for Register_D in RTC.\r | |
189 | gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x0000001D\r | |
190 | \r | |
36dd3c78 RN |
191 | ## Specifies RTC Index Register address in I/O space.\r |
192 | # @Prompt RTC Index Register address\r | |
193 | gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x70|UINT8|0x0000001E\r | |
194 | \r | |
195 | ## Specifies RTC Target Register address in I/O space.\r | |
196 | # @Prompt RTC Target Register address\r | |
197 | gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x71|UINT8|0x0000001F\r | |
198 | \r | |
b414ac4d | 199 | [UserExtensions.TianoCore."ExtraFiles"]\r |
fe320967 | 200 | PcAtChipsetPkgExtra.uni\r |