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21b404d1 | 1 | /** @file\r |
2 | The Header file of the Pci Host Bridge Driver \r | |
3 | \r | |
cac2ab95 | 4 | Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r |
95d48e82 | 5 | This program and the accompanying materials are\r |
21b404d1 | 6 | licensed and made available under the terms and conditions of the BSD License\r |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/ \r | |
14 | \r | |
15 | #ifndef _PCI_HOST_BRIDGE_H_\r | |
16 | #define _PCI_HOST_BRIDGE_H_\r | |
17 | \r | |
18 | #include <PiDxe.h>\r | |
19 | \r | |
20 | #include <IndustryStandard/Pci.h>\r | |
21 | #include <IndustryStandard/Acpi.h>\r | |
22 | \r | |
23 | #include <Protocol/PciHostBridgeResourceAllocation.h>\r | |
24 | #include <Protocol/PciRootBridgeIo.h>\r | |
21b404d1 | 25 | #include <Protocol/Metronome.h>\r |
26 | #include <Protocol/DevicePath.h>\r | |
27 | \r | |
28 | \r | |
29 | #include <Library/BaseLib.h>\r | |
30 | #include <Library/DebugLib.h>\r | |
31 | #include <Library/BaseMemoryLib.h>\r | |
32 | #include <Library/MemoryAllocationLib.h>\r | |
33 | #include <Library/UefiLib.h>\r | |
34 | #include <Library/UefiBootServicesTableLib.h>\r | |
35 | #include <Library/DxeServicesTableLib.h>\r | |
36 | #include <Library/DevicePathLib.h>\r | |
cac2ab95 | 37 | #include <Library/IoLib.h>\r |
38 | #include <Library/PciLib.h>\r | |
21b404d1 | 39 | \r |
40 | //\r | |
41 | // Hard code the host bridge number in the platform.\r | |
42 | // In this chipset, there is only one host bridge.\r | |
43 | //\r | |
44 | #define HOST_BRIDGE_NUMBER 1\r | |
45 | \r | |
cac2ab95 | 46 | #define MAX_PCI_DEVICE_NUMBER 31\r |
47 | #define MAX_PCI_FUNCTION_NUMBER 7\r | |
48 | #define MAX_PCI_REG_ADDRESS 0xFF\r | |
49 | \r | |
50 | typedef enum {\r | |
51 | IoOperation,\r | |
52 | MemOperation,\r | |
53 | PciOperation\r | |
54 | } OPERATION_TYPE;\r | |
55 | \r | |
21b404d1 | 56 | #define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')\r |
57 | typedef struct {\r | |
58 | UINTN Signature;\r | |
59 | EFI_HANDLE HostBridgeHandle;\r | |
60 | UINTN RootBridgeNumber;\r | |
61 | LIST_ENTRY Head;\r | |
62 | BOOLEAN ResourceSubmited; \r | |
63 | BOOLEAN CanRestarted; \r | |
64 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r | |
65 | } PCI_HOST_BRIDGE_INSTANCE;\r | |
66 | \r | |
67 | #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r | |
68 | CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r | |
69 | \r | |
70 | //\r | |
71 | // Driver Entry Point\r | |
72 | //\r | |
73 | EFI_STATUS\r | |
74 | EFIAPI\r | |
75 | EfiMain (\r | |
76 | IN EFI_HANDLE ImageHandle,\r | |
77 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
78 | );\r | |
79 | \r | |
80 | //\r | |
81 | // HostBridge Resource Allocation interface\r | |
82 | //\r | |
83 | EFI_STATUS\r | |
84 | EFIAPI\r | |
85 | NotifyPhase(\r | |
86 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
87 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r | |
88 | );\r | |
89 | \r | |
90 | EFI_STATUS\r | |
91 | EFIAPI\r | |
92 | GetNextRootBridge(\r | |
93 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
94 | IN OUT EFI_HANDLE *RootBridgeHandle\r | |
95 | );\r | |
96 | \r | |
97 | EFI_STATUS\r | |
98 | EFIAPI\r | |
99 | GetAttributes(\r | |
100 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
101 | IN EFI_HANDLE RootBridgeHandle,\r | |
102 | OUT UINT64 *Attributes\r | |
103 | );\r | |
104 | \r | |
105 | EFI_STATUS\r | |
106 | EFIAPI\r | |
107 | StartBusEnumeration(\r | |
108 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
109 | IN EFI_HANDLE RootBridgeHandle,\r | |
110 | OUT VOID **Configuration\r | |
111 | );\r | |
112 | \r | |
113 | EFI_STATUS\r | |
114 | EFIAPI\r | |
115 | SetBusNumbers(\r | |
116 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
117 | IN EFI_HANDLE RootBridgeHandle,\r | |
118 | IN VOID *Configuration\r | |
119 | );\r | |
120 | \r | |
121 | EFI_STATUS\r | |
122 | EFIAPI\r | |
123 | SubmitResources(\r | |
124 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
125 | IN EFI_HANDLE RootBridgeHandle,\r | |
126 | IN VOID *Configuration\r | |
127 | );\r | |
128 | \r | |
129 | EFI_STATUS\r | |
130 | EFIAPI\r | |
131 | GetProposedResources(\r | |
132 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
133 | IN EFI_HANDLE RootBridgeHandle,\r | |
134 | OUT VOID **Configuration\r | |
135 | );\r | |
136 | \r | |
137 | EFI_STATUS\r | |
138 | EFIAPI\r | |
139 | PreprocessController (\r | |
140 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
141 | IN EFI_HANDLE RootBridgeHandle,\r | |
142 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r | |
143 | IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r | |
144 | );\r | |
145 | \r | |
146 | \r | |
147 | //\r | |
148 | // Define resource status constant \r | |
149 | //\r | |
150 | #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r | |
151 | #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r | |
152 | \r | |
153 | \r | |
154 | //\r | |
155 | // Driver Instance Data Prototypes\r | |
156 | //\r | |
157 | \r | |
158 | typedef struct {\r | |
159 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r | |
160 | UINTN NumberOfBytes;\r | |
161 | UINTN NumberOfPages;\r | |
162 | EFI_PHYSICAL_ADDRESS HostAddress;\r | |
163 | EFI_PHYSICAL_ADDRESS MappedHostAddress;\r | |
164 | } MAP_INFO;\r | |
165 | \r | |
166 | typedef struct {\r | |
167 | ACPI_HID_DEVICE_PATH AcpiDevicePath;\r | |
168 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
169 | } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r | |
170 | \r | |
171 | typedef struct {\r | |
172 | UINT64 BusBase;\r | |
173 | UINT64 BusLimit; \r | |
174 | \r | |
175 | UINT64 MemBase; \r | |
176 | UINT64 MemLimit; \r | |
177 | \r | |
178 | UINT64 IoBase; \r | |
179 | UINT64 IoLimit; \r | |
180 | } PCI_ROOT_BRIDGE_RESOURCE_APPETURE;\r | |
181 | \r | |
182 | typedef enum {\r | |
183 | TypeIo = 0,\r | |
184 | TypeMem32,\r | |
185 | TypePMem32,\r | |
186 | TypeMem64,\r | |
187 | TypePMem64,\r | |
188 | TypeBus,\r | |
189 | TypeMax\r | |
190 | } PCI_RESOURCE_TYPE;\r | |
191 | \r | |
192 | typedef enum {\r | |
193 | ResNone = 0,\r | |
194 | ResSubmitted,\r | |
195 | ResRequested,\r | |
196 | ResAllocated,\r | |
197 | ResStatusMax\r | |
198 | } RES_STATUS;\r | |
199 | \r | |
200 | typedef struct {\r | |
201 | PCI_RESOURCE_TYPE Type;\r | |
202 | UINT64 Base;\r | |
203 | UINT64 Length;\r | |
204 | UINT64 Alignment;\r | |
205 | RES_STATUS Status;\r | |
206 | } PCI_RES_NODE;\r | |
207 | \r | |
208 | #define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')\r | |
209 | \r | |
210 | typedef struct {\r | |
211 | UINT32 Signature;\r | |
212 | LIST_ENTRY Link;\r | |
213 | EFI_HANDLE Handle;\r | |
214 | UINT64 RootBridgeAttrib;\r | |
215 | UINT64 Attributes;\r | |
216 | UINT64 Supports;\r | |
217 | \r | |
218 | //\r | |
219 | // Specific for this memory controller: Bus, I/O, Mem\r | |
220 | //\r | |
221 | PCI_RES_NODE ResAllocNode[6];\r | |
222 | \r | |
223 | //\r | |
224 | // Addressing for Memory and I/O and Bus arrange\r | |
225 | //\r | |
226 | UINT64 BusBase;\r | |
227 | UINT64 MemBase; \r | |
228 | UINT64 IoBase; \r | |
229 | UINT64 BusLimit; \r | |
230 | UINT64 MemLimit; \r | |
231 | UINT64 IoLimit; \r | |
232 | \r | |
21b404d1 | 233 | UINTN PciAddress;\r |
234 | UINTN PciData;\r | |
235 | \r | |
236 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r | |
237 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r | |
238 | \r | |
239 | } PCI_ROOT_BRIDGE_INSTANCE;\r | |
240 | \r | |
241 | \r | |
242 | //\r | |
243 | // Driver Instance Data Macros\r | |
244 | //\r | |
245 | #define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r | |
246 | CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r | |
247 | \r | |
248 | \r | |
249 | #define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r | |
250 | CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r | |
251 | \r | |
252 | \r | |
253 | EFI_STATUS\r | |
254 | RootBridgeConstructor (\r | |
255 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r | |
256 | IN EFI_HANDLE HostBridgeHandle,\r | |
257 | IN UINT64 Attri,\r | |
258 | IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture\r | |
259 | );\r | |
260 | \r | |
261 | #endif\r |