projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| b303605e MK |
1 | /** @file\r |
| 2 | CPU EIST control methods\r | |
| 3 | \r | |
| 4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 5 | \r | |
| 0eb3de2e | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| b303605e MK |
7 | \r |
| 8 | **/\r | |
| 9 | \r | |
| 10 | DefinitionBlock (\r | |
| 11 | "CPU0IST.aml",\r | |
| 12 | "SSDT",\r | |
| 13 | 0x01,\r | |
| 14 | "SsgPmm",\r | |
| 15 | "Cpu0Ist",\r | |
| 16 | 0x0012\r | |
| 17 | )\r | |
| 18 | {\r | |
| 19 | External (PDC0, IntObj)\r | |
| 20 | External (CFGD, FieldUnitObj)\r | |
| 21 | External(\_PR.CPU0, DeviceObj)\r | |
| 22 | \r | |
| 23 | Scope(\_PR.CPU0)\r | |
| 24 | {\r | |
| 25 | Method(_PPC,0)\r | |
| 26 | {\r | |
| 27 | Return(ZERO) // Return All States Available.\r | |
| 28 | }\r | |
| 29 | \r | |
| 30 | Method(_PCT,0)\r | |
| 31 | {\r | |
| 32 | //\r | |
| 33 | // If GV3 is supported and OSPM is capable of direct access to\r | |
| 34 | // performance state MSR, we use MSR method\r | |
| 35 | //\r | |
| 36 | //\r | |
| 37 | // PDCx[0] = Indicates whether OSPM is capable of direct access to\r | |
| 38 | // performance state MSR.\r | |
| 39 | //\r | |
| 40 | If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))\r | |
| 41 | {\r | |
| 42 | Return(Package() // MSR Method\r | |
| 43 | {\r | |
| 44 | ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},\r | |
| 45 | ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}\r | |
| 46 | })\r | |
| 47 | \r | |
| 48 | }\r | |
| 49 | \r | |
| 50 | //\r | |
| 51 | // Otherwise, we use smi method\r | |
| 52 | //\r | |
| 53 | Return(Package() // SMI Method\r | |
| 54 | {\r | |
| 55 | ResourceTemplate(){Register(SystemIO,16,0,0xB2)},\r | |
| 56 | ResourceTemplate(){Register(SystemIO, 8,0,0xB3)}\r | |
| 57 | })\r | |
| 58 | }\r | |
| 59 | \r | |
| 60 | Method(_PSS,0)\r | |
| 61 | {\r | |
| 62 | //\r | |
| 63 | // If OSPM is capable of direct access to performance state MSR,\r | |
| 64 | // we report NPSS, otherwise, we report SPSS.\r | |
| 65 | If (And(PDC0,0x0001))\r | |
| 66 | {\r | |
| 67 | Return(NPSS)\r | |
| 68 | }\r | |
| 69 | \r | |
| 70 | Return(SPSS)\r | |
| 71 | }\r | |
| 72 | \r | |
| 73 | Name(SPSS,Package()\r | |
| 74 | {\r | |
| 75 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 76 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 77 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 78 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 79 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 80 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 81 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 82 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 83 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 84 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 85 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 86 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r | |
| 87 | })\r | |
| 88 | \r | |
| 89 | Name(NPSS,Package()\r | |
| 90 | {\r | |
| 91 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 92 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 93 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 94 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 95 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 96 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 97 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 98 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 99 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 100 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 101 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},\r | |
| 102 | Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}\r | |
| 103 | })\r | |
| 104 | \r | |
| 105 | Method(_PSD,0)\r | |
| 106 | {\r | |
| 107 | //\r | |
| 108 | // If CMP is suppored, we report the dependency with two processors\r | |
| 109 | //\r | |
| 110 | If(And(CFGD,0x1000000))\r | |
| 111 | {\r | |
| 112 | //\r | |
| 113 | // If OSPM is capable of hardware coordination of P-states, we report\r | |
| 114 | // the dependency with hardware coordination.\r | |
| 115 | //\r | |
| 116 | // PDCx[11] = Indicates whether OSPM is capable of hardware coordination of P-states\r | |
| 117 | //\r | |
| 118 | If(And(PDC0,0x0800))\r | |
| 119 | {\r | |
| 120 | Return(Package(){\r | |
| 121 | Package(){\r | |
| 122 | 5, // # entries.\r | |
| 123 | 0, // Revision.\r | |
| 124 | 0, // Domain #.\r | |
| 125 | 0xFE, // Coord Type- HW_ALL.\r | |
| 126 | 2 // # processors.\r | |
| 127 | }\r | |
| 128 | })\r | |
| 129 | }\r | |
| 130 | \r | |
| 131 | //\r | |
| 132 | // Otherwise, the dependency with OSPM coordination\r | |
| 133 | //\r | |
| 134 | Return(Package(){\r | |
| 135 | Package(){\r | |
| 136 | 5, // # entries.\r | |
| 137 | 0, // Revision.\r | |
| 138 | 0, // Domain #.\r | |
| 139 | 0xFC, // Coord Type- SW_ALL.\r | |
| 140 | 2 // # processors.\r | |
| 141 | }\r | |
| 142 | })\r | |
| 143 | }\r | |
| 144 | \r | |
| 145 | //\r | |
| 146 | // Otherwise, we report the dependency with one processor\r | |
| 147 | //\r | |
| 148 | Return(Package(){\r | |
| 149 | Package(){\r | |
| 150 | 5, // # entries.\r | |
| 151 | 0, // Revision.\r | |
| 152 | 0, // Domain #.\r | |
| 153 | 0xFC, // Coord Type- SW_ALL.\r | |
| 154 | 1 // # processors.\r | |
| 155 | }\r | |
| 156 | })\r | |
| 157 | }\r | |
| 158 | }\r | |
| 159 | }\r |