ArmPkg/CompilerIntrinsicsLib: Add uread, uwrite GCC assembly sources

[mirror_edk2.git] / QuarkPlatformPkg / Acpi / AcpiTables / Dsdt / PcieExpansionPrt.asi

/** @file\r
PCI express expansion ports\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef PcieExpansionPrt_asi\r
#define PcieExpansionPrt_asi\r
\r
Device (PEX0)    // PCI express bus bridged from [Bus 0, Device 23, Function 0]\r
{\r
    Name(_ADR,0x00170000)            // Device (HI WORD)=23, Func (LO WORD)=0\r
    Name(_PRW,Package(){0x11,0x03})  // GPE pin 0x11, Wake from S3 -- PCI PME#\r
\r
    OperationRegion (PES0,PCI_Config,0x40,0xA0)\r
    Field (PES0, AnyAcc, NoLock, Preserve)\r
    {\r
    Offset(0x1A),              // SLSTS - Slot Status Register\r
    ABP0,  1,                  // Bit 0, Attention Button Pressed\r
    ,  2,\r
    PDC0,  1,                  // Bit 3, Presence Detect Changed\r
    ,  2,\r
    PDS0,  1,                  // Bit 6, Presence Detect State\r
    , 1,\r
    LSC0,  1,                  // Bit 8, Link Active State Changed\r
    offset (0x20),\r
    , 16,\r
    PMS0, 1,                   // Bit 16, PME Status\r
    offset (0x98),\r
    , 30,\r
    HPE0, 1,                   // Bit 30, Hot Plug SCI Enable\r
    PCE0, 1,                   // Bit 31, Power Management SCI Enable.\r
    , 30,\r
    HPS0, 1,                   // Bit 30, Hot Plug SCI Status\r
    PCS0, 1,                   // Bit 31, Power Management SCI Status.\r
    }\r
\r
    Method(_PRT,0,NotSerialized) {\r
        If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing\r
        {\r
            Return (\r
                Package()\r
                {\r
                    // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH\r
                    Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1\r
                    Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0},\r
                    Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0},\r
                    Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0},\r
                }\r
            )\r
        }\r
        else    // IOAPIC Routing\r
        {\r
            Return (\r
                Package()\r
                {\r
                    // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH\r
                    Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1\r
                    Package() {0x0000ffff, 1, 0, 21},\r
                    Package() {0x0000ffff, 2, 0, 22},\r
                    Package() {0x0000ffff, 3, 0, 23},\r
                }\r
            )\r
        }\r
    }\r
}\r
\r
Device (PEX1)    // PCI express bus bridged from [Bus 0, Device 23, Function 1]\r
{\r
    Name(_ADR,0x00170001)            // Device (HI WORD)=23, Func (LO WORD)=1\r
    Name(_PRW,Package(){0x11,0x03})  // GPE pin 0x11, Wake from S3 -- PCI PME#\r
    OperationRegion (PES1,PCI_Config,0x40,0xA0)\r
    Field (PES1, AnyAcc, NoLock, Preserve)\r
    {\r
    Offset(0x1A),              // SLSTS - Slot Status Register\r
    ABP1,  1,                  // Bit 0, Attention Button Pressed\r
    ,  2,\r
    PDC1,  1,                  // Bit 3, Presence Detect Changed\r
    ,  2,\r
    PDS1,  1,                  // Bit 6, Presence Detect State\r
    , 1,\r
    LSC1,  1,                  // Bit 8, Link Active State Changed\r
    offset (0x20),\r
    , 16,\r
    PMS1, 1,                   // Bit 16, PME Status\r
    offset (0x98),\r
    , 30,\r
    HPE1, 1,                   // Bit 30, Hot Plug SCI Enable\r
    PCE1, 1,                   // Bit 31, Power Management SCI Enable.\r
    , 30,\r
    HPS1, 1,                   // Bit 30, Hot Plug SCI Status\r
    PCS1, 1,                   // Bit 31, Power Management SCI Status.\r
    }\r
    Method(_PRT,0,NotSerialized) {\r
        If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing\r
        {\r
            Return (\r
                Package()\r
                {\r
                    // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE\r
                    Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0},\r
                    Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0},\r
                    Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0},\r
                    Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0},\r
                }\r
            )\r
        }\r
        else    // IOAPIC Routing\r
        {\r
            Return (\r
                Package()\r
                {\r
                    // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE\r
                    Package() {0x0000ffff, 0, 0, 21},\r
                    Package() {0x0000ffff, 1, 0, 22},\r
                    Package() {0x0000ffff, 2, 0, 23},\r
                    Package() {0x0000ffff, 3, 0, 20},\r
                }\r
            )\r
        }\r
    }\r
}\r
\r
#endif\r