ArmPkg/CompilerIntrinsicsLib: Add uread, uwrite GCC assembly sources

[mirror_edk2.git] / QuarkPlatformPkg / Acpi / AcpiTables / Dsdt / QuarkSouthCluster.asi

/** @file\r
Quark South Cluster Devices.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef QuarkSouthCluster_asi\r
#define QuarkSouthCluster_asi\r
\r
Device (SDIO)    // SDIO [Bus 0, Device 20, Function 0]\r
{\r
    Name(_ADR,0x00140000)            // Device (HI WORD)=20, Func (LO WORD)=0\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (URT0)    // UART0 [Bus 0, Device 20, Function 1]\r
{\r
    Name(_ADR,0x00140001)            // Device (HI WORD)=20, Func (LO WORD)=1\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (USBD)    // USB Device [Bus 0, Device 20, Function 2]\r
{\r
    Name(_ADR,0x00140002)            // Device (HI WORD)=20, Func (LO WORD)=2\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (EHCI)    // EHCI [Bus 0, Device 20, Function 3]\r
{\r
    Name(_ADR,0x00140003)            // Device (HI WORD)=20, Func (LO WORD)=3\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (OHCI)    // OHCI [Bus 0, Device 20, Function 4]\r
{\r
    Name(_ADR,0x00140004)            // Device (HI WORD)=20, Func (LO WORD)=4\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (URT1)    // UART1 [Bus 0, Device 20, Function 5]\r
{\r
    Name(_ADR,0x00140005)            // Device (HI WORD)=20, Func (LO WORD)=5\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (ENT0)    // Ethernet0 [Bus 0, Device 20, Function 6]\r
{\r
    Name(_ADR,0x00140006)            // Device (HI WORD)=20, Func (LO WORD)=6\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (ENT1)    // Ethernet1 [Bus 0, Device 20, Function 7]\r
{\r
    Name(_ADR,0x00140007)            // Device (HI WORD)=20, Func (LO WORD)=7\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (SPI0)    // SPI0 [Bus 0, Device 21, Function 0]\r
{\r
    Name(_ADR,0x00150000)            // Device (HI WORD)=21, Func (LO WORD)=0\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (SPI1)    // SPI1 [Bus 0, Device 21, Function 1]\r
{\r
    Name(_ADR,0x00150001)            // Device (HI WORD)=21, Func (LO WORD)=1\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
}\r
\r
Device (GIP0)    // I2C/GPIO [Bus 0, Device 21, Function 2]\r
{\r
    Name(_ADR,0x00150002)            // Device (HI WORD)=21, Func (LO WORD)=2\r
    Name(_STA,0xF)                   // Enabled, do Display\r
    Name(_PRW,Package(){0x0F,0x03})  // GPE pin 0x0F, Wake from S3 -- PCI PME#\r
\r
    Device(GPO_)  // GPIO Virtual Child Device- for BAR0 resources\r
    {\r
        Name(_ADR, 0)\r
        Name(_STA, 0xf)\r
        Name(_PRW, Package(0x2)\r
        {\r
            0xf,\r
            0x3\r
        })\r
    }\r
    Device(I2C_)  // I2C Controller Virtual Child Device- for BAR1 resources\r
    {\r
        Name(_ADR, 1)\r
        Name(_STA, 0xf)\r
        Name(_PRW, Package(0x2)\r
        {\r
            0xf,\r
            0x3\r
        })\r
    }\r
}\r
#endif\r