[mirror_edk2.git] / QuarkPlatformPkg / Acpi / AcpiTables / Fadt / Fadt2.0.aslc

/** @file\r
This file describes the contents of the ACPI Fixed ACPI Description Table\r
(FADT).  Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.\r
All changes to the FADT contents should be done in this file.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "Fadt.h"\r
\r
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {\r
  {\r
    EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
    sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
    EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
    0,                    // to make sum of entire table == 0\r
    {EFI_ACPI_OEM_ID},    // OEMID is a 6 bytes long field\r
    EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long)\r
    EFI_ACPI_OEM_REVISION,// OEM revision number\r
    EFI_ACPI_CREATOR_ID,  // ASL compiler vendor ID\r
    EFI_ACPI_CREATOR_REVISION  // ASL compiler revision number\r
  },\r
  0,                    // Physical addesss of FACS\r
  0,                    // Physical address of DSDT\r
  RESERVED,             // reserved\r
  PM_PROFILE,           // Preferred powermanagement profile\r
  SCI_INT_VECTOR,       // System vector of SCI interrupt\r
  ACPI_RUNTIME_UPDATE,  // Port address of SMI command port\r
  ACPI_ENABLE,          // value to write to port smi_cmd to enable ACPI\r
  ACPI_DISABLE,         // value to write to port smi_cmd to disable ACPI\r
  S4BIOS_REQ,           // Value to write to SMI CMD port to enter the S4BIOS state\r
  RESERVED,             // reserved - must be zero\r
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 1a Event Reg Blk\r
  PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk\r
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 1a Ctrl Reg Blk\r
  PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk\r
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 2  Ctrl Reg Blk\r
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt Timer Ctrl Reg Blk\r
  ACPI_RUNTIME_UPDATE,  // Port addr of General Purpose Event 0 Reg Blk\r
  GPE1_BLK_ADDRESS,     // Port addr of General Purpose Event 1 Reg Blk\r
  PM1_EVT_LEN,          // Byte Length of ports at pm1X_evt_blk\r
  PM1_CNT_LEN,          // Byte Length of ports at pm1X_cnt_blk\r
  PM2_CNT_LEN,          // Byte Length of ports at pm2_cnt_blk\r
  PM_TM_LEN,            // Byte Length of ports at pm_tm_blk\r
  GPE0_BLK_LEN,         // Byte Length of ports at gpe0_blk\r
  GPE1_BLK_LEN,         // Byte Length of ports at gpe1_blk\r
  GPE1_BASE,            // offset in gpe model where gpe1 events start\r
  RESERVED,             // reserved\r
  P_LVL2_LAT,           // worst case HW latency to enter/exit C2 state\r
  P_LVL3_LAT,           // worst case HW latency to enter/exit C3 state\r
  FLUSH_SIZE,           // Size of area read to flush caches\r
  FLUSH_STRIDE,         // Stride used in flushing caches\r
  DUTY_OFFSET,          // bit location of duty cycle field in p_cnt reg\r
  DUTY_WIDTH,           // bit width of duty cycle field in p_cnt reg\r
  DAY_ALRM,             // index to day-of-month alarm in RTC CMOS RAM\r
  MON_ALRM,             // index to month-of-year alarm in RTC CMOS RAM\r
  CENTURY,              // index to century in RTC CMOS RAM\r
  IAPC_BOOT_ARCH,       // IA-PC Boot Architecture Flags\r
  RESERVED,             // reserved\r
  FLAG2,                // Fixed feature flags\r
\r
  {\r
    RESET_REG_ADDRESS_SPACE_ID,  // Address of the reset register\r
    RESET_REG_BIT_WIDTH,\r
    RESET_REG_BIT_OFFSET,\r
    RESERVED,\r
    RESET_REG_ADDRESS\r
  },\r
  RESET_VALUE,          // Value to write to the RESET_REG port\r
  {\r
    RESERVED,\r
    RESERVED,\r
    RESERVED\r
  },\r
  0,                // 64Bit physical addesss of FACS\r
  0,                // 64Bit physical address of DSDT\r
\r
  {\r
    PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk\r
    PM1a_EVT_BLK_BIT_WIDTH,\r
    PM1a_EVT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk\r
    PM1b_EVT_BLK_BIT_WIDTH,\r
    PM1b_EVT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    PM1b_EVT_BLK_ADDRESS\r
  },\r
\r
  {\r
    PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk\r
    PM1a_CNT_BLK_BIT_WIDTH,\r
    PM1a_CNT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk\r
    PM1b_CNT_BLK_BIT_WIDTH,\r
    PM1b_CNT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    PM1b_CNT_BLK_ADDRESS\r
  },\r
\r
  {\r
    PM2_CNT_BLK_ADDRESS_SPACE_ID,  // Extended Port address of Power Mgt 2  Ctrl Reg Blk\r
    PM2_CNT_BLK_BIT_WIDTH,\r
    PM2_CNT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    PM_TMR_BLK_ADDRESS_SPACE_ID,   // Extended Port address of Power Mgt Timer Ctrl Reg Blk\r
    PM_TMR_BLK_BIT_WIDTH,\r
    PM_TMR_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    GPE0_BLK_ADDRESS_SPACE_ID,   // Extended Port address of General Purpose Event 0 Reg Blk\r
    GPE0_BLK_BIT_WIDTH,\r
    GPE0_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    GPE1_BLK_ADDRESS_SPACE_ID,   // Extended Port address of General Purpose Event 1 Reg Blk\r
    GPE1_BLK_BIT_WIDTH,\r
    GPE1_BLK_BIT_OFFSET,\r
    RESERVED,\r
    GPE1_BLK_ADDRESS\r
  }\r
};\r
\r
VOID*\r
ReferenceAcpiTable (\r
  VOID\r
  )\r
\r
{\r
  //\r
  // Reference the table being generated to prevent the optimizer from removing the\r
  // data structure from the exeutable\r
  //\r
  return (VOID*)&FADT;\r
}\r
Commit	Line	Data
b303605e MK	1	/** @file\r
	2	This file describes the contents of the ACPI Fixed ACPI Description Table\r
	3	(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.\r
	4	All changes to the FADT contents should be done in this file.\r
	5	\r
	6	Copyright (c) 2013-2015 Intel Corporation.\r
	7	\r
0eb3de2e	8	SPDX-License-Identifier: BSD-2-Clause-Patent\r
b303605e MK	9	\r
	10	**/\r
	11	\r
	12	#include "Fadt.h"\r
	13	\r
	14	EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {\r
	15	{\r
	16	EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
	17	sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
	18	EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
	19	0, // to make sum of entire table == 0\r
	20	{EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field\r
	21	EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long)\r
	22	EFI_ACPI_OEM_REVISION,// OEM revision number\r
	23	EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
	24	EFI_ACPI_CREATOR_REVISION // ASL compiler revision number\r
	25	},\r
	26	0, // Physical addesss of FACS\r
	27	0, // Physical address of DSDT\r
	28	RESERVED, // reserved\r
	29	PM_PROFILE, // Preferred powermanagement profile\r
	30	SCI_INT_VECTOR, // System vector of SCI interrupt\r
	31	ACPI_RUNTIME_UPDATE, // Port address of SMI command port\r
	32	ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
	33	ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
	34	S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
	35	RESERVED, // reserved - must be zero\r
	36	ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Event Reg Blk\r
	37	PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk\r
	38	ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Ctrl Reg Blk\r
	39	PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk\r
	40	ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 2 Ctrl Reg Blk\r
	41	ACPI_RUNTIME_UPDATE, // Port address of Power Mgt Timer Ctrl Reg Blk\r
	42	ACPI_RUNTIME_UPDATE, // Port addr of General Purpose Event 0 Reg Blk\r
	43	GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk\r
	44	PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
	45	PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
	46	PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r
	47	PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
	48	GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
	49	GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
	50	GPE1_BASE, // offset in gpe model where gpe1 events start\r
	51	RESERVED, // reserved\r
	52	P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
	53	P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
	54	FLUSH_SIZE, // Size of area read to flush caches\r
	55	FLUSH_STRIDE, // Stride used in flushing caches\r
	56	DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r
	57	DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r
	58	DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
	59	MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
	60	CENTURY, // index to century in RTC CMOS RAM\r
	61	IAPC_BOOT_ARCH, // IA-PC Boot Architecture Flags\r
	62	RESERVED, // reserved\r
	63	FLAG2, // Fixed feature flags\r
	64	\r
	65	{\r
	66	RESET_REG_ADDRESS_SPACE_ID, // Address of the reset register\r
	67	RESET_REG_BIT_WIDTH,\r
	68	RESET_REG_BIT_OFFSET,\r
	69	RESERVED,\r
	70	RESET_REG_ADDRESS\r
	71	},\r
	72	RESET_VALUE, // Value to write to the RESET_REG port\r
73	{\r
74	RESERVED,\r
75	RESERVED,\r
76	RESERVED\r
77	},\r
78	0, // 64Bit physical addesss of FACS\r
79	0, // 64Bit physical address of DSDT\r
80	\r
81	{\r
82	PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk\r
83	PM1a_EVT_BLK_BIT_WIDTH,\r
84	PM1a_EVT_BLK_BIT_OFFSET,\r
85	RESERVED,\r
86	ACPI_RUNTIME_UPDATE\r
87	},\r
88	\r
89	{\r
90	PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk\r
91	PM1b_EVT_BLK_BIT_WIDTH,\r
92	PM1b_EVT_BLK_BIT_OFFSET,\r
93	RESERVED,\r
94	PM1b_EVT_BLK_ADDRESS\r
95	},\r
96	\r
97	{\r
98	PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk\r
99	PM1a_CNT_BLK_BIT_WIDTH,\r
100	PM1a_CNT_BLK_BIT_OFFSET,\r
101	RESERVED,\r
102	ACPI_RUNTIME_UPDATE\r
103	},\r
104	\r
105	{\r
106	PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk\r
107	PM1b_CNT_BLK_BIT_WIDTH,\r
108	PM1b_CNT_BLK_BIT_OFFSET,\r
109	RESERVED,\r
110	PM1b_CNT_BLK_ADDRESS\r
111	},\r
112	\r
113	{\r
114	PM2_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 2 Ctrl Reg Blk\r
115	PM2_CNT_BLK_BIT_WIDTH,\r
116	PM2_CNT_BLK_BIT_OFFSET,\r
117	RESERVED,\r
118	ACPI_RUNTIME_UPDATE\r
119	},\r
120	\r
121	{\r
122	PM_TMR_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt Timer Ctrl Reg Blk\r
123	PM_TMR_BLK_BIT_WIDTH,\r
124	PM_TMR_BLK_BIT_OFFSET,\r
125	RESERVED,\r
126	ACPI_RUNTIME_UPDATE\r
127	},\r
128	\r
129	{\r
130	GPE0_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 0 Reg Blk\r
131	GPE0_BLK_BIT_WIDTH,\r
132	GPE0_BLK_BIT_OFFSET,\r
133	RESERVED,\r
134	ACPI_RUNTIME_UPDATE\r
135	},\r
136	\r
137	{\r
138	GPE1_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 1 Reg Blk\r
139	GPE1_BLK_BIT_WIDTH,\r
140	GPE1_BLK_BIT_OFFSET,\r
141	RESERVED,\r
142	GPE1_BLK_ADDRESS\r
143	}\r
144	};\r
145	\r
146	VOID*\r
147	ReferenceAcpiTable (\r
148	VOID\r
149	)\r
150	\r
151	{\r
152	//\r
153	// Reference the table being generated to prevent the optimizer from removing the\r
154	// data structure from the exeutable\r
155	//\r
156	return (VOID*)&FADT;\r
157	}\r