[mirror_edk2.git] / QuarkPlatformPkg / Acpi / AcpiTables / Fadt / Fadt2.0.aslc

/** @file\r
This file describes the contents of the ACPI Fixed ACPI Description Table\r
(FADT).  Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.\r
All changes to the FADT contents should be done in this file.\r
\r
Copyright (c) 2013-2015 Intel Corporation.\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "Fadt.h"\r
\r
EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {\r
  {\r
    EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
    sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
    EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
    0,                    // to make sum of entire table == 0\r
    {EFI_ACPI_OEM_ID},    // OEMID is a 6 bytes long field\r
    EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long)\r
    EFI_ACPI_OEM_REVISION,// OEM revision number\r
    EFI_ACPI_CREATOR_ID,  // ASL compiler vendor ID\r
    EFI_ACPI_CREATOR_REVISION  // ASL compiler revision number\r
  },\r
  0,                    // Physical addesss of FACS\r
  0,                    // Physical address of DSDT\r
  RESERVED,             // reserved\r
  PM_PROFILE,           // Preferred powermanagement profile\r
  SCI_INT_VECTOR,       // System vector of SCI interrupt\r
  ACPI_RUNTIME_UPDATE,  // Port address of SMI command port\r
  ACPI_ENABLE,          // value to write to port smi_cmd to enable ACPI\r
  ACPI_DISABLE,         // value to write to port smi_cmd to disable ACPI\r
  S4BIOS_REQ,           // Value to write to SMI CMD port to enter the S4BIOS state\r
  RESERVED,             // reserved - must be zero\r
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 1a Event Reg Blk\r
  PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk\r
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 1a Ctrl Reg Blk\r
  PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk\r
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt 2  Ctrl Reg Blk\r
  ACPI_RUNTIME_UPDATE,  // Port address of Power Mgt Timer Ctrl Reg Blk\r
  ACPI_RUNTIME_UPDATE,  // Port addr of General Purpose Event 0 Reg Blk\r
  GPE1_BLK_ADDRESS,     // Port addr of General Purpose Event 1 Reg Blk\r
  PM1_EVT_LEN,          // Byte Length of ports at pm1X_evt_blk\r
  PM1_CNT_LEN,          // Byte Length of ports at pm1X_cnt_blk\r
  PM2_CNT_LEN,          // Byte Length of ports at pm2_cnt_blk\r
  PM_TM_LEN,            // Byte Length of ports at pm_tm_blk\r
  GPE0_BLK_LEN,         // Byte Length of ports at gpe0_blk\r
  GPE1_BLK_LEN,         // Byte Length of ports at gpe1_blk\r
  GPE1_BASE,            // offset in gpe model where gpe1 events start\r
  RESERVED,             // reserved\r
  P_LVL2_LAT,           // worst case HW latency to enter/exit C2 state\r
  P_LVL3_LAT,           // worst case HW latency to enter/exit C3 state\r
  FLUSH_SIZE,           // Size of area read to flush caches\r
  FLUSH_STRIDE,         // Stride used in flushing caches\r
  DUTY_OFFSET,          // bit location of duty cycle field in p_cnt reg\r
  DUTY_WIDTH,           // bit width of duty cycle field in p_cnt reg\r
  DAY_ALRM,             // index to day-of-month alarm in RTC CMOS RAM\r
  MON_ALRM,             // index to month-of-year alarm in RTC CMOS RAM\r
  CENTURY,              // index to century in RTC CMOS RAM\r
  IAPC_BOOT_ARCH,       // IA-PC Boot Architecture Flags\r
  RESERVED,             // reserved\r
  FLAG2,                // Fixed feature flags\r
\r
  {\r
    RESET_REG_ADDRESS_SPACE_ID,  // Address of the reset register\r
    RESET_REG_BIT_WIDTH,\r
    RESET_REG_BIT_OFFSET,\r
    RESERVED,\r
    RESET_REG_ADDRESS\r
  },\r
  RESET_VALUE,          // Value to write to the RESET_REG port\r
  {\r
    RESERVED,\r
    RESERVED,\r
    RESERVED\r
  },\r
  0,                // 64Bit physical addesss of FACS\r
  0,                // 64Bit physical address of DSDT\r
\r
  {\r
    PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk\r
    PM1a_EVT_BLK_BIT_WIDTH,\r
    PM1a_EVT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk\r
    PM1b_EVT_BLK_BIT_WIDTH,\r
    PM1b_EVT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    PM1b_EVT_BLK_ADDRESS\r
  },\r
\r
  {\r
    PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk\r
    PM1a_CNT_BLK_BIT_WIDTH,\r
    PM1a_CNT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk\r
    PM1b_CNT_BLK_BIT_WIDTH,\r
    PM1b_CNT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    PM1b_CNT_BLK_ADDRESS\r
  },\r
\r
  {\r
    PM2_CNT_BLK_ADDRESS_SPACE_ID,  // Extended Port address of Power Mgt 2  Ctrl Reg Blk\r
    PM2_CNT_BLK_BIT_WIDTH,\r
    PM2_CNT_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    PM_TMR_BLK_ADDRESS_SPACE_ID,   // Extended Port address of Power Mgt Timer Ctrl Reg Blk\r
    PM_TMR_BLK_BIT_WIDTH,\r
    PM_TMR_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    GPE0_BLK_ADDRESS_SPACE_ID,   // Extended Port address of General Purpose Event 0 Reg Blk\r
    GPE0_BLK_BIT_WIDTH,\r
    GPE0_BLK_BIT_OFFSET,\r
    RESERVED,\r
    ACPI_RUNTIME_UPDATE\r
  },\r
\r
  {\r
    GPE1_BLK_ADDRESS_SPACE_ID,   // Extended Port address of General Purpose Event 1 Reg Blk\r
    GPE1_BLK_BIT_WIDTH,\r
    GPE1_BLK_BIT_OFFSET,\r
    RESERVED,\r
    GPE1_BLK_ADDRESS\r
  }\r
};\r
\r
VOID*\r
ReferenceAcpiTable (\r
  VOID\r
  )\r
\r
{\r
  //\r
  // Reference the table being generated to prevent the optimizer from removing the\r
  // data structure from the exeutable\r
  //\r
  return (VOID*)&FADT;\r
}\r
Commit	Line	Data
b303605e MK	1	/** @file\r
	2	This file describes the contents of the ACPI Fixed ACPI Description Table\r
	3	(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.\r
	4	All changes to the FADT contents should be done in this file.\r
	5	\r
	6	Copyright (c) 2013-2015 Intel Corporation.\r
	7	\r
	8	This program and the accompanying materials\r
	9	are licensed and made available under the terms and conditions of the BSD License\r
	10	which accompanies this distribution. The full text of the license may be found at\r
	11	http://opensource.org/licenses/bsd-license.php\r
	12	\r
	13	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	14	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	15	\r
	16	**/\r
	17	\r
	18	#include "Fadt.h"\r
	19	\r
	20	EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {\r
	21	{\r
	22	EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
	23	sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
	24	EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
	25	0, // to make sum of entire table == 0\r
	26	{EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field\r
	27	EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long)\r
	28	EFI_ACPI_OEM_REVISION,// OEM revision number\r
	29	EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
	30	EFI_ACPI_CREATOR_REVISION // ASL compiler revision number\r
	31	},\r
	32	0, // Physical addesss of FACS\r
	33	0, // Physical address of DSDT\r
	34	RESERVED, // reserved\r
	35	PM_PROFILE, // Preferred powermanagement profile\r
	36	SCI_INT_VECTOR, // System vector of SCI interrupt\r
	37	ACPI_RUNTIME_UPDATE, // Port address of SMI command port\r
	38	ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
	39	ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
	40	S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
	41	RESERVED, // reserved - must be zero\r
	42	ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Event Reg Blk\r
	43	PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk\r
	44	ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Ctrl Reg Blk\r
	45	PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk\r
	46	ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 2 Ctrl Reg Blk\r
	47	ACPI_RUNTIME_UPDATE, // Port address of Power Mgt Timer Ctrl Reg Blk\r
	48	ACPI_RUNTIME_UPDATE, // Port addr of General Purpose Event 0 Reg Blk\r
	49	GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk\r
	50	PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
	51	PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
	52	PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r
	53	PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
	54	GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
	55	GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
	56	GPE1_BASE, // offset in gpe model where gpe1 events start\r
	57	RESERVED, // reserved\r
	58	P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
	59	P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
	60	FLUSH_SIZE, // Size of area read to flush caches\r
	61	FLUSH_STRIDE, // Stride used in flushing caches\r
	62	DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r
	63	DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r
	64	DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
65	MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
66	CENTURY, // index to century in RTC CMOS RAM\r
67	IAPC_BOOT_ARCH, // IA-PC Boot Architecture Flags\r
68	RESERVED, // reserved\r
69	FLAG2, // Fixed feature flags\r
70	\r
71	{\r
72	RESET_REG_ADDRESS_SPACE_ID, // Address of the reset register\r
73	RESET_REG_BIT_WIDTH,\r
74	RESET_REG_BIT_OFFSET,\r
75	RESERVED,\r
76	RESET_REG_ADDRESS\r
77	},\r
78	RESET_VALUE, // Value to write to the RESET_REG port\r
79	{\r
80	RESERVED,\r
81	RESERVED,\r
82	RESERVED\r
83	},\r
84	0, // 64Bit physical addesss of FACS\r
85	0, // 64Bit physical address of DSDT\r
86	\r
87	{\r
88	PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk\r
89	PM1a_EVT_BLK_BIT_WIDTH,\r
90	PM1a_EVT_BLK_BIT_OFFSET,\r
91	RESERVED,\r
92	ACPI_RUNTIME_UPDATE\r
93	},\r
94	\r
95	{\r
96	PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk\r
97	PM1b_EVT_BLK_BIT_WIDTH,\r
98	PM1b_EVT_BLK_BIT_OFFSET,\r
99	RESERVED,\r
100	PM1b_EVT_BLK_ADDRESS\r
101	},\r
102	\r
103	{\r
104	PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk\r
105	PM1a_CNT_BLK_BIT_WIDTH,\r
106	PM1a_CNT_BLK_BIT_OFFSET,\r
107	RESERVED,\r
108	ACPI_RUNTIME_UPDATE\r
109	},\r
110	\r
111	{\r
112	PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk\r
113	PM1b_CNT_BLK_BIT_WIDTH,\r
114	PM1b_CNT_BLK_BIT_OFFSET,\r
115	RESERVED,\r
116	PM1b_CNT_BLK_ADDRESS\r
117	},\r
118	\r
119	{\r
120	PM2_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 2 Ctrl Reg Blk\r
121	PM2_CNT_BLK_BIT_WIDTH,\r
122	PM2_CNT_BLK_BIT_OFFSET,\r
123	RESERVED,\r
124	ACPI_RUNTIME_UPDATE\r
125	},\r
126	\r
127	{\r
128	PM_TMR_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt Timer Ctrl Reg Blk\r
129	PM_TMR_BLK_BIT_WIDTH,\r
130	PM_TMR_BLK_BIT_OFFSET,\r
131	RESERVED,\r
132	ACPI_RUNTIME_UPDATE\r
133	},\r
134	\r
135	{\r
136	GPE0_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 0 Reg Blk\r
137	GPE0_BLK_BIT_WIDTH,\r
138	GPE0_BLK_BIT_OFFSET,\r
139	RESERVED,\r
140	ACPI_RUNTIME_UPDATE\r
141	},\r
142	\r
143	{\r
144	GPE1_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 1 Reg Blk\r
145	GPE1_BLK_BIT_WIDTH,\r
146	GPE1_BLK_BIT_OFFSET,\r
147	RESERVED,\r
148	GPE1_BLK_ADDRESS\r
149	}\r
150	};\r
151	\r
152	VOID*\r
153	ReferenceAcpiTable (\r
154	VOID\r
155	)\r
156	\r
157	{\r
158	//\r
159	// Reference the table being generated to prevent the optimizer from removing the\r
160	// data structure from the exeutable\r
161	//\r
162	return (VOID*)&FADT;\r
163	}\r