[mirror_edk2.git] / QuarkPlatformPkg / Feature / Capsule / Library / PlatformFlashAccessLib / SpiFlashDevice.c

/** @file\r
  SPI flash device description.\r
\r
  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
\r
**/\r
\r
#include "SpiFlashDevice.h"\r
\r
#define FLASH_SIZE  (FixedPcdGet32 (PcdFlashAreaSize))\r
\r
SPI_INIT_TABLE  mSpiInitTable[] = {\r
  //\r
  // Macronix 32Mbit part\r
  //\r
  {\r
    SPI_MX25L3205_ID1,\r
    SPI_MX25L3205_ID2,\r
    SPI_MX25L3205_ID3,\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle20MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
    },\r
    (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
  //\r
  // Winbond 32Mbit part\r
  //\r
  {\r
    SPI_W25X32_ID1,\r
    SF_DEVICE_ID0_W25QXX,\r
    SF_DEVICE_ID1_W25Q32,\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
    },\r
    (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
  //\r
  // Winbond 32Mbit part\r
  //\r
  {\r
    SPI_W25X32_ID1,\r
    SPI_W25X32_ID2,\r
    SPI_W25X32_ID3,\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
    },\r
    (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
  //\r
  // Atmel 32Mbit part\r
  //\r
  {\r
    SPI_AT26DF321_ID1,\r
    SPI_AT26DF321_ID2,  // issue: byte 2 identifies family/density for Atmel\r
    SPI_AT26DF321_ID3,\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
    },\r
    (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
\r
  //\r
  // Intel 32Mbit part bottom boot\r
  //\r
  {\r
    SPI_QH25F320_ID1,\r
    SPI_QH25F320_ID2,\r
    SPI_QH25F320_ID3,\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_ENABLE\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
    },\r
    0,           // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
  //\r
  // SST 64Mbit part\r
  //\r
  {\r
    SPI_SST25VF080B_ID1,      // VendorId\r
    SF_DEVICE_ID0_25VF064C,   // DeviceId 0\r
    SF_DEVICE_ID1_25VF064C,   // DeviceId 1\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
    },\r
    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
  //\r
  // NUMONYX 64Mbit part\r
  //\r
  {\r
    SF_VENDOR_ID_NUMONYX,     // VendorId\r
    SF_DEVICE_ID0_M25PX64,    // DeviceId 0\r
    SF_DEVICE_ID1_M25PX64,    // DeviceId 1\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
    },\r
    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
  //\r
  // Atmel 64Mbit part\r
  //\r
  {\r
    SF_VENDOR_ID_ATMEL,       // VendorId\r
    SF_DEVICE_ID0_AT25DF641,  // DeviceId 0\r
    SF_DEVICE_ID1_AT25DF641,  // DeviceId 1\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
    },\r
    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
\r
  //\r
  // Spansion 64Mbit part\r
  //\r
  {\r
    SF_VENDOR_ID_SPANSION,       // VendorId\r
    SF_DEVICE_ID0_S25FL064K,  // DeviceId 0\r
    SF_DEVICE_ID1_S25FL064K,  // DeviceId 1\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
    },\r
    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
\r
  //\r
  // Macronix 64Mbit part bottom boot\r
  //\r
  {\r
    SF_VENDOR_ID_MX,          // VendorId\r
    SF_DEVICE_ID0_25L6405D,   // DeviceId 0\r
    SF_DEVICE_ID1_25L6405D,   // DeviceId 1\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
    },\r
    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
  //\r
  // Winbond 64Mbit part bottom boot\r
  //\r
  {\r
    SPI_W25X64_ID1,\r
    SF_DEVICE_ID0_W25QXX,\r
    SF_DEVICE_ID1_W25Q64,\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
    },\r
    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
  //\r
  // Winbond 64Mbit part bottom boot\r
  //\r
  {\r
    SPI_W25X64_ID1,\r
    SPI_W25X64_ID2,\r
    SPI_W25X64_ID3,\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle50MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_ERASE,       EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
    },\r
    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  },\r
  //\r
  // Intel 64Mbit part bottom boot\r
  //\r
  {\r
    SPI_QH25F640_ID1,\r
    SPI_QH25F640_ID2,\r
    SPI_QH25F640_ID3,\r
    {\r
      SPI_COMMAND_WRITE_ENABLE,\r
      SPI_COMMAND_WRITE_S_EN\r
    },\r
    {\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_JEDEC_ID,    EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ_ID,     EnumSpiCycle33MHz, EnumSpiOperationOther},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S,     EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_WRITE,       EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
      {EnumSpiOpcodeRead,        SPI_COMMAND_READ,        EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
      {EnumSpiOpcodeWrite,       SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
      {EnumSpiOpcodeReadNoAddr,  SPI_COMMAND_READ_S,      EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
      {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE,  EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
    },\r
    0x800000 - FLASH_SIZE,          // BIOS Start Offset\r
    FLASH_SIZE   // BIOS image size in flash\r
  }\r
};\r
Commit	Line	Data
63b9a685 JY	1	/** @file\r
	2	SPI flash device description.\r
	3	\r
	4	Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
0eb3de2e	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
63b9a685 JY	6	\r
	7	\r
	8	**/\r
	9	\r
	10	#include "SpiFlashDevice.h"\r
	11	\r
	12	#define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize))\r
	13	\r
	14	SPI_INIT_TABLE mSpiInitTable[] = {\r
	15	//\r
	16	// Macronix 32Mbit part\r
	17	//\r
	18	{\r
	19	SPI_MX25L3205_ID1,\r
	20	SPI_MX25L3205_ID2,\r
	21	SPI_MX25L3205_ID3,\r
	22	{\r
	23	SPI_COMMAND_WRITE_ENABLE,\r
	24	SPI_COMMAND_WRITE_S_EN\r
	25	},\r
	26	{\r
	27	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
	28	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
	29	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
	30	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
	31	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData},\r
	32	{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
	33	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
	34	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
	35	},\r
	36	(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
	37	FLASH_SIZE // BIOS image size in flash\r
	38	},\r
	39	//\r
	40	// Winbond 32Mbit part\r
	41	//\r
	42	{\r
	43	SPI_W25X32_ID1,\r
	44	SF_DEVICE_ID0_W25QXX,\r
	45	SF_DEVICE_ID1_W25Q32,\r
	46	{\r
	47	SPI_COMMAND_WRITE_ENABLE,\r
	48	SPI_COMMAND_WRITE_S_EN\r
	49	},\r
	50	{\r
	51	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
	52	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
	53	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
	54	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
	55	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
	56	{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
	57	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
	58	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
	59	},\r
	60	(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
	61	FLASH_SIZE // BIOS image size in flash\r
	62	},\r
	63	//\r
	64	// Winbond 32Mbit part\r
	65	//\r
	66	{\r
	67	SPI_W25X32_ID1,\r
	68	SPI_W25X32_ID2,\r
	69	SPI_W25X32_ID3,\r
70	{\r
71	SPI_COMMAND_WRITE_ENABLE,\r
72	SPI_COMMAND_WRITE_S_EN\r
73	},\r
74	{\r
75	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
76	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
77	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
78	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
79	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
80	{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},\r
81	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
82	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
83	},\r
84	(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
85	FLASH_SIZE // BIOS image size in flash\r
86	},\r
87	//\r
88	// Atmel 32Mbit part\r
89	//\r
90	{\r
91	SPI_AT26DF321_ID1,\r
92	SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel\r
93	SPI_AT26DF321_ID3,\r
94	{\r
95	SPI_COMMAND_WRITE_ENABLE,\r
96	SPI_COMMAND_WRITE_S_EN\r
97	},\r
98	{\r
99	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
100	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
101	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
102	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
103	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
104	{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
105	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
106	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
107	},\r
108	(UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
109	FLASH_SIZE // BIOS image size in flash\r
110	},\r
111	\r
112	//\r
113	// Intel 32Mbit part bottom boot\r
114	//\r
115	{\r
116	SPI_QH25F320_ID1,\r
117	SPI_QH25F320_ID2,\r
118	SPI_QH25F320_ID3,\r
119	{\r
120	SPI_COMMAND_WRITE_ENABLE,\r
121	SPI_COMMAND_WRITE_ENABLE\r
122	},\r
123	{\r
124	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
125	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
126	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
127	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
128	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
129	{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
130	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
131	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
132	},\r
133	0, // BIOS Start Offset\r
134	FLASH_SIZE // BIOS image size in flash\r
135	},\r
136	//\r
137	// SST 64Mbit part\r
138	//\r
139	{\r
140	SPI_SST25VF080B_ID1, // VendorId\r
141	SF_DEVICE_ID0_25VF064C, // DeviceId 0\r
142	SF_DEVICE_ID1_25VF064C, // DeviceId 1\r
143	{\r
144	SPI_COMMAND_WRITE_ENABLE,\r
145	SPI_COMMAND_WRITE_S_EN\r
146	},\r
147	{\r
148	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
149	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
150	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
151	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
152	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
153	{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
154	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
155	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
156	},\r
157	0x800000 - FLASH_SIZE, // BIOS Start Offset\r
158	FLASH_SIZE // BIOS image size in flash\r
159	},\r
160	//\r
161	// NUMONYX 64Mbit part\r
162	//\r
163	{\r
164	SF_VENDOR_ID_NUMONYX, // VendorId\r
165	SF_DEVICE_ID0_M25PX64, // DeviceId 0\r
166	SF_DEVICE_ID1_M25PX64, // DeviceId 1\r
167	{\r
168	SPI_COMMAND_WRITE_ENABLE,\r
169	SPI_COMMAND_WRITE_S_EN\r
170	},\r
171	{\r
172	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
173	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
174	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
175	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
176	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
177	{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
178	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
179	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
180	},\r
181	0x800000 - FLASH_SIZE, // BIOS Start Offset\r
182	FLASH_SIZE // BIOS image size in flash\r
183	},\r
184	//\r
185	// Atmel 64Mbit part\r
186	//\r
187	{\r
188	SF_VENDOR_ID_ATMEL, // VendorId\r
189	SF_DEVICE_ID0_AT25DF641, // DeviceId 0\r
190	SF_DEVICE_ID1_AT25DF641, // DeviceId 1\r
191	{\r
192	SPI_COMMAND_WRITE_ENABLE,\r
193	SPI_COMMAND_WRITE_S_EN\r
194	},\r
195	{\r
196	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
197	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
198	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
199	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
200	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
201	{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
202	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
203	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
204	},\r
205	0x800000 - FLASH_SIZE, // BIOS Start Offset\r
206	FLASH_SIZE // BIOS image size in flash\r
207	},\r
208	\r
209	//\r
210	// Spansion 64Mbit part\r
211	//\r
212	{\r
213	SF_VENDOR_ID_SPANSION, // VendorId\r
214	SF_DEVICE_ID0_S25FL064K, // DeviceId 0\r
215	SF_DEVICE_ID1_S25FL064K, // DeviceId 1\r
216	{\r
217	SPI_COMMAND_WRITE_ENABLE,\r
218	SPI_COMMAND_WRITE_S_EN\r
219	},\r
220	{\r
221	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
222	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
223	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
224	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
225	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
226	{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
227	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
228	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
229	},\r
230	0x800000 - FLASH_SIZE, // BIOS Start Offset\r
231	FLASH_SIZE // BIOS image size in flash\r
232	},\r
233	\r
234	//\r
235	// Macronix 64Mbit part bottom boot\r
236	//\r
237	{\r
238	SF_VENDOR_ID_MX, // VendorId\r
239	SF_DEVICE_ID0_25L6405D, // DeviceId 0\r
240	SF_DEVICE_ID1_25L6405D, // DeviceId 1\r
241	{\r
242	SPI_COMMAND_WRITE_ENABLE,\r
243	SPI_COMMAND_WRITE_S_EN\r
244	},\r
245	{\r
246	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
247	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
248	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
249	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
250	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
251	{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},\r
252	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
253	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
254	},\r
255	0x800000 - FLASH_SIZE, // BIOS Start Offset\r
256	FLASH_SIZE // BIOS image size in flash\r
257	},\r
258	//\r
259	// Winbond 64Mbit part bottom boot\r
260	//\r
261	{\r
262	SPI_W25X64_ID1,\r
263	SF_DEVICE_ID0_W25QXX,\r
264	SF_DEVICE_ID1_W25Q64,\r
265	{\r
266	SPI_COMMAND_WRITE_ENABLE,\r
267	SPI_COMMAND_WRITE_S_EN\r
268	},\r
269	{\r
270	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
271	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
272	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
273	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
274	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
275	{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
276	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
277	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
278	},\r
279	0x800000 - FLASH_SIZE, // BIOS Start Offset\r
280	FLASH_SIZE // BIOS image size in flash\r
281	},\r
282	//\r
283	// Winbond 64Mbit part bottom boot\r
284	//\r
285	{\r
286	SPI_W25X64_ID1,\r
287	SPI_W25X64_ID2,\r
288	SPI_W25X64_ID3,\r
289	{\r
290	SPI_COMMAND_WRITE_ENABLE,\r
291	SPI_COMMAND_WRITE_S_EN\r
292	},\r
293	{\r
294	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
295	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
296	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
297	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
298	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
299	{EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
300	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
301	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
302	},\r
303	0x800000 - FLASH_SIZE, // BIOS Start Offset\r
304	FLASH_SIZE // BIOS image size in flash\r
305	},\r
306	//\r
307	// Intel 64Mbit part bottom boot\r
308	//\r
309	{\r
310	SPI_QH25F640_ID1,\r
311	SPI_QH25F640_ID2,\r
312	SPI_QH25F640_ID3,\r
313	{\r
314	SPI_COMMAND_WRITE_ENABLE,\r
315	SPI_COMMAND_WRITE_S_EN\r
316	},\r
317	{\r
318	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
319	{EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
320	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
321	{EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
322	{EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
323	{EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
324	{EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
325	{EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
326	},\r
327	0x800000 - FLASH_SIZE, // BIOS Start Offset\r
328	FLASH_SIZE // BIOS image size in flash\r
329	}\r
330	};\r