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1 | /** @file\r |
2 | Quark platform specific information.\r | |
3 | \r | |
4 | Copyright (c) 2013 Intel Corporation.\r | |
5 | \r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | \r | |
15 | **/\r | |
16 | #include "Uefi.h"\r | |
17 | \r | |
18 | #ifndef __PLATFORM_H__\r | |
19 | #define __PLATFORM_H__\r | |
20 | \r | |
21 | //\r | |
22 | // Constant definition\r | |
23 | //\r | |
24 | #define MAX_SMRAM_RANGES 4\r | |
25 | #define MAX_NODE 1\r | |
26 | \r | |
27 | #define QUARK_STAGE1_IMAGE_TYPE_MASK 0xF0\r | |
28 | #define QUARK_STAGE1_BOOT_IMAGE_TYPE 0x00 // Stage1 Boot images 0x00 -> 0x0F.\r | |
29 | #define QUARK_STAGE1_RECOVERY_IMAGE_TYPE 0x10 // Stage1 Recovery images 0x10 -> 0x1F.\r | |
30 | \r | |
31 | #define QUARK_BOOTROM_BASE_ADDRESS 0xFFFE0000 // Base address of Quark ROM in memory map.\r | |
32 | #define QUARK_BOOTROM_SIZE_BYTES 0x20000 // Quark ROM is 128KB.\r | |
33 | #define SMM_DEFAULT_SMBASE 0x30000 // Default SMBASE address.\r | |
34 | #define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM.\r | |
35 | \r | |
36 | //\r | |
37 | // Gpio to be used to assert / deassert PCI express PERST# signal.\r | |
38 | //\r | |
39 | #define PCIEXP_PERST_RESUMEWELL_GPIO 3\r | |
40 | \r | |
41 | //\r | |
42 | // Minimum time in microseconds for assertion of PERST# signal.\r | |
43 | //\r | |
44 | #define PCIEXP_PERST_MIN_ASSERT_US 100\r | |
45 | \r | |
46 | //\r | |
47 | // Microsecond delay post issueing common lane reset.\r | |
48 | //\r | |
49 | #define PCIEXP_DELAY_US_POST_CMNRESET_RESET 1\r | |
50 | \r | |
51 | //\r | |
52 | // Microsecond delay to wait for PLL to lock.\r | |
53 | //\r | |
54 | #define PCIEXP_DELAY_US_WAIT_PLL_LOCK 80\r | |
55 | \r | |
56 | //\r | |
57 | // Microsecond delay post issueing sideband interface reset.\r | |
58 | //\r | |
59 | #define PCIEXP_DELAY_US_POST_SBI_RESET 20\r | |
60 | \r | |
61 | //\r | |
62 | // Microsecond delay post deasserting PERST#.\r | |
63 | //\r | |
64 | #define PCIEXP_DELAY_US_POST_PERST_DEASSERT 10\r | |
65 | \r | |
66 | //\r | |
67 | // Catastrophic Trip point in degrees Celsius for this platform.\r | |
68 | //\r | |
69 | #define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105\r | |
70 | \r | |
71 | //\r | |
72 | // Platform flash update LED common definitions.\r | |
73 | //\r | |
74 | #define PLATFORM_FLASH_UPDATE_LED_TOGGLE_COUNT 7\r | |
75 | #define PLATFORM_FLASH_UPDATE_LED_TOGGLE_DELTA (1000 * 1000) // In Microseconds for EFI_STALL.\r | |
76 | \r | |
77 | //\r | |
78 | // This structure stores the base and size of the ACPI reserved memory used when\r | |
79 | // resuming from S3. This region must be allocated by the platform code.\r | |
80 | //\r | |
81 | typedef struct {\r | |
82 | UINT32 AcpiReservedMemoryBase;\r | |
83 | UINT32 AcpiReservedMemorySize;\r | |
84 | UINT32 SystemMemoryLength;\r | |
85 | } RESERVED_ACPI_S3_RANGE;\r | |
86 | \r | |
87 | #define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_ACPI_S3_RANGE))\r | |
88 | \r | |
89 | //\r | |
90 | // Define valid platform types.\r | |
91 | // First add value before TypePlatformMax in EFI_PLATFORM_TYPE definition\r | |
92 | // and then add string description to end of EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION.\r | |
93 | // Value shown for supported platforms to help sanity checking with build tools\r | |
94 | // and ACPI method usage.\r | |
95 | //\r | |
96 | typedef enum {\r | |
97 | TypeUnknown = 0, // !!! SHOULD BE THE FIRST ENTRY !!!\r | |
98 | QuarkEmulation = 1,\r | |
99 | ClantonPeakSVP = 2,\r | |
100 | KipsBay = 3,\r | |
101 | CrossHill = 4,\r | |
102 | ClantonHill = 5,\r | |
103 | Galileo = 6,\r | |
104 | TypePlatformRsv7 = 7,\r | |
105 | GalileoGen2 = 8,\r | |
106 | TypePlatformMax // !!! SHOULD BE THE LAST ENTRY !!!\r | |
107 | } EFI_PLATFORM_TYPE;\r | |
108 | \r | |
109 | #define EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION \\r | |
110 | L"TypeUnknown",\\r | |
111 | L"QuarkEmulation",\\r | |
112 | L"ClantonPeakSVP",\\r | |
113 | L"KipsBay",\\r | |
114 | L"CrossHill",\\r | |
115 | L"ClantonHill",\\r | |
116 | L"Galileo",\\r | |
117 | L"TypePlatformRsv7",\\r | |
118 | L"GalileoGen2",\\r | |
119 | \r | |
120 | typedef struct {\r | |
121 | UINT32 EntryOffset;\r | |
122 | UINT8 ImageIndex;\r | |
123 | } QUARK_EDKII_STAGE1_HEADER;\r | |
124 | \r | |
125 | #endif\r |