projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| b303605e MK |
1 | /** @file\r |
| 2 | Platform Pcie Helper Lib.\r | |
| 3 | \r | |
| 4 | Copyright (c) 2013 Intel Corporation.\r | |
| 5 | \r | |
| 0eb3de2e | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| b303605e MK |
7 | \r |
| 8 | **/\r | |
| 9 | \r | |
| 10 | #include "CommonHeader.h"\r | |
| 11 | \r | |
| 12 | //\r | |
| 13 | // Routines local to this source module.\r | |
| 14 | //\r | |
| 15 | VOID\r | |
| 16 | LegacyGpioSetLevel (\r | |
| 17 | IN CONST UINT32 LevelRegOffset,\r | |
| 18 | IN CONST UINT32 GpioNum,\r | |
| 19 | IN CONST BOOLEAN HighLevel\r | |
| 20 | )\r | |
| 21 | {\r | |
| 22 | UINT32 RegValue;\r | |
| 23 | UINT32 GpioBaseAddress;\r | |
| 24 | UINT32 GpioNumMask;\r | |
| 25 | \r | |
| 26 | GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;\r | |
| 27 | ASSERT (GpioBaseAddress > 0);\r | |
| 28 | \r | |
| 29 | RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);\r | |
| 30 | GpioNumMask = (1 << GpioNum);\r | |
| 31 | if (HighLevel) {\r | |
| 32 | RegValue |= (GpioNumMask);\r | |
| 33 | } else {\r | |
| 34 | RegValue &= ~(GpioNumMask);\r | |
| 35 | }\r | |
| 36 | IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, RegValue);\r | |
| 37 | }\r | |
| 38 | \r | |
| 39 | //\r | |
| 40 | // Routines exported by this component.\r | |
| 41 | //\r | |
| 42 | \r | |
| 43 | /**\r | |
| 44 | Platform assert PCI express PERST# signal.\r | |
| 45 | \r | |
| 46 | @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r | |
| 47 | \r | |
| 48 | **/\r | |
| 49 | VOID\r | |
| 50 | EFIAPI\r | |
| 51 | PlatformPERSTAssert (\r | |
| 52 | IN CONST EFI_PLATFORM_TYPE PlatformType\r | |
| 53 | )\r | |
| 54 | {\r | |
| 55 | if (PlatformType == GalileoGen2) {\r | |
| 56 | LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);\r | |
| 57 | } else {\r | |
| 58 | LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);\r | |
| 59 | }\r | |
| 60 | }\r | |
| 61 | \r | |
| 62 | /**\r | |
| 63 | Platform de assert PCI express PERST# signal.\r | |
| 64 | \r | |
| 65 | @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r | |
| 66 | \r | |
| 67 | **/\r | |
| 68 | VOID\r | |
| 69 | EFIAPI\r | |
| 70 | PlatformPERSTDeAssert (\r | |
| 71 | IN CONST EFI_PLATFORM_TYPE PlatformType\r | |
| 72 | )\r | |
| 73 | {\r | |
| 74 | if (PlatformType == GalileoGen2) {\r | |
| 75 | LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);\r | |
| 76 | } else {\r | |
| 77 | LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);\r | |
| 78 | }\r | |
| 79 | }\r | |
| 80 | \r | |
| 81 | /** Early initialisation of the PCIe controller.\r | |
| 82 | \r | |
| 83 | @param PlatformType See EFI_PLATFORM_TYPE enum definitions.\r | |
| 84 | \r | |
| 85 | @retval EFI_SUCCESS Operation success.\r | |
| 86 | \r | |
| 87 | **/\r | |
| 88 | EFI_STATUS\r | |
| 89 | EFIAPI\r | |
| 90 | PlatformPciExpressEarlyInit (\r | |
| 91 | IN CONST EFI_PLATFORM_TYPE PlatformType\r | |
| 92 | )\r | |
| 93 | {\r | |
| 94 | \r | |
| 95 | //\r | |
| 96 | // Release and wait for PCI controller to come out of reset.\r | |
| 97 | //\r | |
| 98 | SocUnitReleasePcieControllerPreWaitPllLock (PlatformType);\r | |
| 99 | MicroSecondDelay (PCIEXP_DELAY_US_WAIT_PLL_LOCK);\r | |
| 100 | SocUnitReleasePcieControllerPostPllLock (PlatformType);\r | |
| 101 | \r | |
| 102 | //\r | |
| 103 | // Early PCIe initialisation\r | |
| 104 | //\r | |
| 105 | SocUnitEarlyInitialisation ();\r | |
| 106 | \r | |
| 107 | //\r | |
| 108 | // Do North cluster early PCIe init.\r | |
| 109 | //\r | |
| 110 | PciExpressEarlyInit ();\r | |
| 111 | \r | |
| 112 | return EFI_SUCCESS;\r | |
| 113 | }\r | |
| 114 | \r |