projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| b303605e MK |
1 | /** @file\r |
| 2 | Register initialization table for Ich.\r | |
| 3 | \r | |
| 4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
| 5 | \r | |
| 0eb3de2e | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| b303605e MK |
7 | \r |
| 8 | \r | |
| 9 | **/\r | |
| 10 | \r | |
| 11 | \r | |
| 12 | #include "CommonHeader.h"\r | |
| 13 | \r | |
| 14 | VOID\r | |
| 15 | PlatformInitQNCRegs (\r | |
| 16 | VOID\r | |
| 17 | )\r | |
| 18 | {\r | |
| 19 | //\r | |
| 20 | // All devices on bus 0.\r | |
| 21 | // Device 0:\r | |
| 22 | // FNC 0: Host Bridge\r | |
| 23 | // Device 20:\r | |
| 24 | // FNC 0: IOSF2AHB Bridge\r | |
| 25 | // Device 21:\r | |
| 26 | // FNC 0: IOSF2AHB Bridge\r | |
| 27 | // Device 23:\r | |
| 28 | // FNC 0: PCIe Port 0\r | |
| 29 | // Device 24:\r | |
| 30 | // FNC 0: PCIe Port 1\r | |
| 31 | \r | |
| 32 | // Device 31:\r | |
| 33 | // FNC 0: PCI-LPC Bridge\r | |
| 34 | //\r | |
| 35 | S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_FWH_BIOS_DEC),\r | |
| 36 | B_QNC_LPC_FWH_BIOS_DEC_F0 | B_QNC_LPC_FWH_BIOS_DEC_F8 |\r | |
| 37 | B_QNC_LPC_FWH_BIOS_DEC_E0 | B_QNC_LPC_FWH_BIOS_DEC_E8 |\r | |
| 38 | B_QNC_LPC_FWH_BIOS_DEC_D0 | B_QNC_LPC_FWH_BIOS_DEC_D8 |\r | |
| 39 | B_QNC_LPC_FWH_BIOS_DEC_C0 | B_QNC_LPC_FWH_BIOS_DEC_C8\r | |
| 40 | );\r | |
| 41 | \r | |
| 42 | //\r | |
| 43 | // Program SCI Interrupt for IRQ9\r | |
| 44 | //\r | |
| 45 | S3PciWrite8 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_QNC_LPC_ACTL),\r | |
| 46 | V_QNC_LPC_ACTL_SCIS_IRQ9\r | |
| 47 | );\r | |
| 48 | \r | |
| 49 | //\r | |
| 50 | // Program Quark Interrupt Route Registers\r | |
| 51 | //\r | |
| 52 | S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT0IR,\r | |
| 53 | PcdGet16(PcdQuarkAgent0IR)\r | |
| 54 | );\r | |
| 55 | S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT1IR,\r | |
| 56 | PcdGet16(PcdQuarkAgent1IR)\r | |
| 57 | );\r | |
| 58 | S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT2IR,\r | |
| 59 | PcdGet16(PcdQuarkAgent2IR)\r | |
| 60 | );\r | |
| 61 | S3MmioWrite16 ((UINTN)PcdGet64(PcdRcbaMmioBaseAddress) + R_QNC_RCRB_AGENT3IR,\r | |
| 62 | PcdGet16(PcdQuarkAgent3IR)\r | |
| 63 | );\r | |
| 64 | \r | |
| 65 | //\r | |
| 66 | // Program SVID and SID for QNC PCI devices. In order to boost performance, we\r | |
| 67 | // combine two 16 bit PCI_WRITE into one 32 bit PCI_WRITE. The programmed LPC SVID\r | |
| 68 | // will reflect on all internal devices's SVID registers\r | |
| 69 | //\r | |
| 70 | S3PciWrite32 (PCI_LIB_ADDRESS (PCI_BUS_NUMBER_QNC, PCI_DEVICE_NUMBER_QNC_LPC, PCI_FUNCTION_NUMBER_QNC_LPC, R_EFI_PCI_SVID),\r | |
| 71 | (UINT32)(V_INTEL_VENDOR_ID + (QUARK_V_LPC_DEVICE_ID_0 << 16))\r | |
| 72 | );\r | |
| 73 | \r | |
| 74 | //\r | |
| 75 | // Write once on Element Self Description Register before OS boot\r | |
| 76 | //\r | |
| 77 | QNCMmio32And (PcdGet64(PcdRcbaMmioBaseAddress), 0x04, 0xFF00FFFF);\r | |
| 78 | \r | |
| 79 | return;\r | |
| 80 | }\r |