ArmPkg/CompilerIntrinsicsLib: Add uread, uwrite GCC assembly sources

[mirror_edk2.git] / QuarkPlatformPkg / Platform / Pei / PlatformInit / PlatformErratas.c

/** @file\r
Platform Erratas performed by early init PEIM driver.\r
\r
Copyright (c) 2013 Intel Corporation.\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "CommonHeader.h"\r
#include "PlatformEarlyInit.h"\r
\r
//\r
// Constants.\r
//\r
\r
//\r
// Platform EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs.\r
//\r
#define EHCI_OUT_THRESHOLD_VALUE              (0x7f)\r
#define EHCI_IN_THRESHOLD_VALUE               (0x7f)\r
\r
//\r
// Platform init USB device interrupt masks.\r
//\r
#define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG    (0x0000007f)\r
#define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG   (B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK | B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK)\r
\r
//\r
// Global variables defined within this source module.\r
//\r
\r
UINTN IohEhciPciReg[IOH_MAX_EHCI_USB_CONTROLLERS] = {\r
  PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, 0),\r
};\r
\r
UINTN IohUsbDevicePciReg[IOH_MAX_USBDEVICE_USB_CONTROLLERS] = {\r
  PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER, IOH_USBDEVICE_DEVICE_NUMBER, IOH_USBDEVICE_FUNCTION_NUMBER, 0),\r
};\r
\r
//\r
// Routines local to this source module.\r
//\r
\r
/** Perform USB erratas after MRC init.\r
\r
**/\r
VOID\r
PlatformUsbErratasPostMrc (\r
  VOID\r
  )\r
{\r
  UINT32                            Index;\r
  UINT32                            TempBar0Addr;\r
  UINT16                            SaveCmdReg;\r
  UINT32                            SaveBar0Reg;\r
\r
  TempBar0Addr = PcdGet32(PcdPeiQNCUsbControllerMemoryBaseAddress);\r
\r
  //\r
  // Apply EHCI controller erratas.\r
  //\r
  for (Index = 0; Index < IOH_MAX_EHCI_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) {\r
\r
    if ((PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) {\r
      continue;  // Device not enabled, skip.\r
    }\r
\r
    //\r
    // Save current settings for PCI CMD/BAR0 registers\r
    //\r
    SaveCmdReg = PciRead16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND);\r
    SaveBar0Reg = PciRead32 (IohEhciPciReg[Index] + R_IOH_USB_MEMBAR);\r
\r
    //\r
    // Temp. assign base address register, Enable Memory Space.\r
    //\r
    PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr);\r
    PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE);\r
\r
\r
    //\r
    // Set packet buffer OUT/IN thresholds.\r
    //\r
    MmioAndThenOr32 (\r
      TempBar0Addr + R_IOH_EHCI_INSNREG01,\r
      (UINT32) (~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK | B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK)),\r
      (UINT32) ((EHCI_OUT_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP) | (EHCI_IN_THRESHOLD_VALUE << B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP))\r
      );\r
\r
    //\r
    // Restore settings for PCI CMD/BAR0 registers\r
    //\r
    PciWrite32 ((IohEhciPciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg);\r
    PciWrite16 (IohEhciPciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg);\r
  }\r
\r
  //\r
  // Apply USB device controller erratas.\r
  //\r
  for (Index = 0; Index < IOH_MAX_USBDEVICE_USB_CONTROLLERS; Index++, TempBar0Addr += IOH_USB_CONTROLLER_MMIO_RANGE) {\r
\r
    if ((PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_VENDOR_ID)) != V_IOH_USB_VENDOR_ID) {\r
      continue;  // Device not enabled, skip.\r
    }\r
\r
    //\r
    // Save current settings for PCI CMD/BAR0 registers\r
    //\r
    SaveCmdReg = PciRead16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND);\r
    SaveBar0Reg = PciRead32 (IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR);\r
\r
    //\r
    // Temp. assign base address register, Enable Memory Space.\r
    //\r
    PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), TempBar0Addr);\r
    PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg | B_IOH_USB_COMMAND_MSE);\r
\r
    //\r
    // Erratas for USB Device interrupt registers.\r
    //\r
\r
    //\r
    // 1st Mask interrupts.\r
    //\r
    MmioWrite32 (\r
      TempBar0Addr + R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG,\r
      V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG\r
      );\r
    //\r
    // 2nd RW/1C of equivalent status bits.\r
    //\r
    MmioWrite32 (\r
      TempBar0Addr + R_IOH_USBDEVICE_D_INTR_UDC_REG,\r
      V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG\r
      );\r
\r
    //\r
    // 1st Mask end point interrupts.\r
    //\r
    MmioWrite32 (\r
      TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG,\r
      V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG\r
      );\r
    //\r
    // 2nd RW/1C of equivalent end point status bits.\r
    //\r
    MmioWrite32 (\r
      TempBar0Addr + R_IOH_USBDEVICE_EP_INTR_UDC_REG,\r
      V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG\r
      );\r
\r
    //\r
    // Restore settings for PCI CMD/BAR0 registers\r
    //\r
    PciWrite32 ((IohUsbDevicePciReg[Index] + R_IOH_USB_MEMBAR), SaveBar0Reg);\r
    PciWrite16 (IohUsbDevicePciReg[Index] + R_IOH_USB_COMMAND, SaveCmdReg);\r
  }\r
}\r
\r
//\r
// Routines exported by this source module.\r
//\r
\r
/** Perform Platform Erratas after MRC.\r
\r
  @retval   EFI_SUCCESS               Operation success.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
PlatformErratasPostMrc (\r
  VOID\r
  )\r
{\r
  PlatformUsbErratasPostMrc ();\r
  return EFI_SUCCESS;\r
}\r