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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2013-2015 Intel Corporation.\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _SPI_FLASH_DEVICE_H_\r | |
17 | #define _SPI_FLASH_DEVICE_H_\r | |
18 | \r | |
19 | #include <PiDxe.h>\r | |
20 | #include <Protocol/Spi.h>\r | |
21 | #include <Protocol/FirmwareVolumeBlock.h>\r | |
22 | \r | |
23 | //\r | |
24 | // Supported SPI Flash Devices\r | |
25 | //\r | |
26 | typedef enum {\r | |
27 | EnumSpiFlash25L3205D, // Macronix 32Mbit part\r | |
28 | EnumSpiFlashW25Q32, // Winbond 32Mbit part\r | |
29 | EnumSpiFlashW25X32, // Winbond 32Mbit part\r | |
30 | EnumSpiFlashAT25DF321, // Atmel 32Mbit part\r | |
31 | EnumSpiFlashQH25F320, // Intel 32Mbit part\r | |
32 | EnumSpiFlash25VF064C, // SST 64Mbit part\r | |
33 | EnumSpiFlashM25PX64, // NUMONYX 64Mbit part\r | |
34 | EnumSpiFlashAT25DF641, // Atmel 64Mbit part\r | |
35 | EnumSpiFlashS25FL064K, // Spansion 64Mbit part\r | |
36 | EnumSpiFlash25L6405D, // Macronix 64Mbit part\r | |
37 | EnumSpiFlashW25Q64, // Winbond 64Mbit part\r | |
38 | EnumSpiFlashW25X64, // Winbond 64Mbit part\r | |
39 | EnumSpiFlashQH25F640, // Intel 64Mbit part\r | |
40 | EnumSpiFlashMax\r | |
41 | } SPI_FLASH_TYPES_SUPPORTED;\r | |
42 | \r | |
43 | //\r | |
44 | // Flash Device commands\r | |
45 | //\r | |
46 | // If a supported device uses a command different from the list below, a device specific command\r | |
47 | // will be defined just below it's JEDEC id section.\r | |
48 | //\r | |
49 | #define SPI_COMMAND_WRITE 0x02\r | |
50 | #define SPI_COMMAND_WRITE_AAI 0xAD\r | |
51 | #define SPI_COMMAND_READ 0x03\r | |
52 | #define SPI_COMMAND_ERASE 0x20\r | |
53 | #define SPI_COMMAND_WRITE_DISABLE 0x04\r | |
54 | #define SPI_COMMAND_READ_S 0x05\r | |
55 | #define SPI_COMMAND_WRITE_ENABLE 0x06\r | |
56 | #define SPI_COMMAND_READ_ID 0xAB\r | |
57 | #define SPI_COMMAND_JEDEC_ID 0x9F\r | |
58 | #define SPI_COMMAND_WRITE_S_EN 0x50\r | |
59 | #define SPI_COMMAND_WRITE_S 0x01\r | |
60 | #define SPI_COMMAND_CHIP_ERASE 0xC7\r | |
61 | #define SPI_COMMAND_BLOCK_ERASE 0xD8\r | |
62 | \r | |
63 | //\r | |
64 | // Flash JEDEC device ids\r | |
65 | //\r | |
66 | // SST 8Mbit part\r | |
67 | //\r | |
68 | #define SPI_SST25VF080B_ID1 0xBF\r | |
69 | #define SPI_SST25VF080B_ID2 0x25\r | |
70 | #define SPI_SST25VF080B_ID3 0x8E\r | |
71 | //\r | |
72 | // SST 16Mbit part\r | |
73 | //\r | |
74 | #define SPI_SST25VF016B_ID1 0xBF\r | |
75 | #define SPI_SST25VF016B_ID2 0x25\r | |
76 | #define SPI_SST25V016BF_ID3 0x41\r | |
77 | //\r | |
78 | // Macronix 32Mbit part\r | |
79 | //\r | |
80 | // MX25 part does not support WRITE_AAI comand (0xAD)\r | |
81 | //\r | |
82 | #define SPI_MX25L3205_ID1 0xC2\r | |
83 | #define SPI_MX25L3205_ID2 0x20\r | |
84 | #define SPI_MX25L3205_ID3 0x16\r | |
85 | //\r | |
86 | // Intel 32Mbit part bottom boot\r | |
87 | //\r | |
88 | #define SPI_QH25F320_ID1 0x89\r | |
89 | #define SPI_QH25F320_ID2 0x89\r | |
90 | #define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot\r | |
91 | //\r | |
92 | // Intel 64Mbit part bottom boot\r | |
93 | //\r | |
94 | #define SPI_QH25F640_ID1 0x89\r | |
95 | #define SPI_QH25F640_ID2 0x89\r | |
96 | #define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot\r | |
97 | //\r | |
98 | // QH part does not support command 0x20 for erase; only 0xD8 (sector erase)\r | |
99 | // QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)\r | |
100 | // 0x40 command ignored if address outside of parameter block range\r | |
101 | //\r | |
102 | #define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40\r | |
103 | //\r | |
104 | // Winbond 32Mbit part\r | |
105 | //\r | |
106 | #define SPI_W25X32_ID1 0xEF\r | |
107 | #define SPI_W25X32_ID2 0x30 // Memory Type\r | |
108 | #define SPI_W25X32_ID3 0x16 // Capacity\r | |
109 | #define SF_DEVICE_ID1_W25Q32 0x16\r | |
110 | \r | |
111 | //\r | |
112 | // Winbond 64Mbit part\r | |
113 | //\r | |
114 | #define SPI_W25X64_ID1 0xEF\r | |
115 | #define SPI_W25X64_ID2 0x30 // Memory Type\r | |
116 | #define SPI_W25X64_ID3 0x17 // Capacity\r | |
117 | #define SF_DEVICE_ID0_W25QXX 0x40\r | |
118 | #define SF_DEVICE_ID1_W25Q64 0x17\r | |
119 | //\r | |
120 | // Winbond 128Mbit part\r | |
121 | //\r | |
122 | #define SF_DEVICE_ID0_W25Q128 0x40\r | |
123 | #define SF_DEVICE_ID1_W25Q128 0x18\r | |
124 | \r | |
125 | //\r | |
126 | // Atmel 32Mbit part\r | |
127 | //\r | |
128 | #define SPI_AT26DF321_ID1 0x1F\r | |
129 | #define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density\r | |
130 | #define SPI_AT26DF321_ID3 0x00\r | |
131 | \r | |
132 | #define SF_VENDOR_ID_ATMEL 0x1F\r | |
133 | #define SF_DEVICE_ID0_AT25DF641 0x48\r | |
134 | #define SF_DEVICE_ID1_AT25DF641 0x00\r | |
135 | \r | |
136 | //\r | |
137 | // SST 8Mbit part\r | |
138 | //\r | |
139 | #define SPI_SST25VF080B_ID1 0xBF\r | |
140 | #define SPI_SST25VF080B_ID2 0x25\r | |
141 | #define SPI_SST25VF080B_ID3 0x8E\r | |
142 | #define SF_DEVICE_ID0_25VF064C 0x25\r | |
143 | #define SF_DEVICE_ID1_25VF064C 0x4B\r | |
144 | \r | |
145 | //\r | |
146 | // SST 16Mbit part\r | |
147 | //\r | |
148 | #define SPI_SST25VF016B_ID1 0xBF\r | |
149 | #define SPI_SST25VF016B_ID2 0x25\r | |
150 | #define SPI_SST25V016BF_ID3 0x41\r | |
151 | \r | |
152 | //\r | |
153 | // Winbond 32Mbit part\r | |
154 | //\r | |
155 | #define SPI_W25X32_ID1 0xEF\r | |
156 | #define SPI_W25X32_ID2 0x30 // Memory Type\r | |
157 | #define SPI_W25X32_ID3 0x16 // Capacity\r | |
158 | \r | |
159 | #define SF_VENDOR_ID_MX 0xC2\r | |
160 | #define SF_DEVICE_ID0_25L6405D 0x20\r | |
161 | #define SF_DEVICE_ID1_25L6405D 0x17\r | |
162 | \r | |
163 | #define SF_VENDOR_ID_NUMONYX 0x20\r | |
164 | #define SF_DEVICE_ID0_M25PX64 0x71\r | |
165 | #define SF_DEVICE_ID1_M25PX64 0x17\r | |
166 | \r | |
167 | //\r | |
168 | // Spansion 64Mbit part\r | |
169 | //\r | |
170 | #define SF_VENDOR_ID_SPANSION 0xEF\r | |
171 | #define SF_DEVICE_ID0_S25FL064K 0x40\r | |
172 | #define SF_DEVICE_ID1_S25FL064K 0x00\r | |
173 | \r | |
174 | //\r | |
175 | // index for prefix opcodes\r | |
176 | //\r | |
177 | #define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE\r | |
178 | #define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN\r | |
179 | #define BIOS_CTRL 0xDC\r | |
180 | \r | |
181 | #define PFAB_CARD_DEVICE_ID 0x5150\r | |
182 | #define PFAB_CARD_VENDOR_ID 0x8086\r | |
183 | #define PFAB_CARD_SETUP_REGISTER 0x40\r | |
184 | #define PFAB_CARD_SETUP_BYTE 0x0d\r | |
185 | \r | |
186 | \r | |
187 | #endif\r |